static int hsi_set_tx(struct hsi_port *sport, struct hst_ctx *cfg)
{
struct hsi_dev *hsi_ctrl = sport->hsi_controller;
void __iomem *base = hsi_ctrl->base;
int port = sport->port_number;
struct platform_device *pdev = to_platform_device(hsi_ctrl->dev);
unsigned int max_divisor = hsi_driver_device_is_hsi(pdev) ?
HSI_MAX_TX_DIVISOR : HSI_SSI_MAX_TX_DIVISOR;
if (((cfg->mode & HSI_MODE_VAL_MASK) != HSI_MODE_STREAM) &&
((cfg->mode & HSI_MODE_VAL_MASK) != HSI_MODE_FRAME) &&
(cfg->mode != NOT_SET))
return -EINVAL;
if (hsi_driver_device_is_hsi(pdev)) {
/* HSI only supports payload size of 32bits */
if ((cfg->frame_size != HSI_FRAMESIZE_MAX) &&
(cfg->frame_size != NOT_SET))
return -EINVAL;
} else {
if ((cfg->frame_size > HSI_FRAMESIZE_MAX) &&
(cfg->frame_size != NOT_SET))
return -EINVAL;
}
if ((cfg->channels == 0) ||
((cfg->channels > sport->max_ch) && (cfg->channels != NOT_SET)))
return -EINVAL;
if ((cfg->divisor > max_divisor) && (cfg->divisor != NOT_SET))
return -EINVAL;
if ((cfg->arb_mode != HSI_ARBMODE_ROUNDROBIN) &&
(cfg->arb_mode != HSI_ARBMODE_PRIORITY) && (cfg->mode != NOT_SET))
return -EINVAL;
if (cfg->mode != NOT_SET)
hsi_outl(cfg->mode | HSI_HST_MODE_WAKE_CTRL_SW, base,
HSI_HST_MODE_REG(port));
if (cfg->frame_size != NOT_SET)
hsi_outl(cfg->frame_size, base, HSI_HST_FRAMESIZE_REG(port));
if (cfg->channels != NOT_SET) {
if ((cfg->channels & (-cfg->channels)) ^ cfg->channels)
return -EINVAL;
else
hsi_outl(cfg->channels, base,
HSI_HST_CHANNELS_REG(port));
}
if (cfg->divisor != NOT_SET)
hsi_outl(cfg->divisor, base, HSI_HST_DIVISOR_REG(port));
if (cfg->arb_mode != NOT_SET)
hsi_outl(cfg->arb_mode, base, HSI_HST_ARBMODE_REG(port));
return 0;
}
void hsi_set_pm_default(struct hsi_dev *hsi_ctrl)
{
/* Set default SYSCONFIG PM settings */
hsi_outl((HSI_AUTOIDLE | HSI_SIDLEMODE_SMART_WAKEUP |
HSI_MIDLEMODE_SMART_WAKEUP),
hsi_ctrl->base, HSI_SYS_SYSCONFIG_REG);
hsi_outl(HSI_CLK_AUTOGATING_ON, hsi_ctrl->base, HSI_GDD_GCR_REG);
/* HSI_TODO : use the HWMOD API : omap_hwmod_set_slave_idlemode() */
}
void hsi_set_pm_force_hsi_on(struct hsi_dev *hsi_ctrl)
{
/* Force HSI to ON by never acknowledging a PRCM idle request */
/* SIdleAck and MStandby are never asserted */
hsi_outl((HSI_AUTOIDLE | HSI_SIDLEMODE_NO |
HSI_MIDLEMODE_NO),
hsi_ctrl->base, HSI_SYS_SYSCONFIG_REG);
hsi_outl(HSI_CLK_AUTOGATING_ON, hsi_ctrl->base, HSI_GDD_GCR_REG);
/* HSI_TODO : use the HWMOD API : omap_hwmod_set_slave_idlemode() */
}
void hsi_set_pm_force_hsi_on(struct hsi_dev *hsi_ctrl)
{
dpr_0("hsi_driver.c:%s. hsi_ctrl->id=%d,hsi_mode=0x%08X;\n",__func__,hsi_ctrl->id,hsi_ctrl->hsi_port[hsi_ctrl->id].hsi_mode); //Add for Flashless 3HSI dbg
/* Force HSI to ON by never acknowledging a PRCM idle request */
/* SIdleAck and MStandby are never asserted */
hsi_outl((HSI_AUTOIDLE | HSI_SIDLEMODE_NO |
HSI_MIDLEMODE_NO),
hsi_ctrl->base, HSI_SYS_SYSCONFIG_REG);
hsi_outl(HSI_CLK_AUTOGATING_ON, hsi_ctrl->base, HSI_GDD_GCR_REG);
/* HSI_TODO : use the HWMOD API : omap_hwmod_set_slave_idlemode() */
}
static void hsi_restore_mode(struct platform_device *pdev)
{
struct hsi_platform_data *pdata = pdev->dev.platform_data;
void __iomem *base = OMAP2_IO_ADDRESS(pdev->resource[0].start);
struct port_ctx *p;
int port;
for (port = 1; port <= pdata->num_ports; port++) {
p = &pdata->ctx.pctx[port - 1];
hsi_outl(p->hst.mode, base + HSI_HST_MODE_REG(port));
hsi_outl(p->hsr.mode, base + HSI_HSR_MODE_REG(port));
}
}
static void hsi_set_mode(struct platform_device *pdev, u32 mode)
{
struct hsi_platform_data *pdata = pdev->dev.platform_data;
void __iomem *base = OMAP2_IO_ADDRESS(pdev->resource[0].start);
int port;
for (port = 1; port <= pdata->num_ports; port++) {
/* FIXME - to update: need read/modify/write or something else:
* this register now also contains flow and wake ctrl
*/
hsi_outl(mode, base + HSI_HST_MODE_REG(port));
hsi_outl(mode, base + HSI_HSR_MODE_REG(port));
}
}
/**
* hsi_driver_int_proc - check all channels / ports for interrupts events
* @hsi_ctrl - HSI controler data
* @status_offset: interrupt status register offset
* @enable_offset: interrupt enable regiser offset
* @start: interrupt index to start on
* @stop: interrupt index to stop on
*
* This function calls the related processing functions and triggered events
*/
static void hsi_driver_int_proc(struct hsi_port *pport,
unsigned long status_offset, unsigned long enable_offset,
unsigned int start, unsigned int stop)
{
struct hsi_dev *hsi_ctrl = pport->hsi_controller;
void __iomem *base = hsi_ctrl->base;
unsigned int port = pport->port_number;
unsigned int channel;
u32 status_reg;
u32 hsr_err_reg;
u32 channels_served = 0;
status_reg = hsi_inl(base, status_offset);
status_reg &= hsi_inl(base, enable_offset);
for (channel = start; channel < stop; channel++) {
if (status_reg & HSI_HST_DATAACCEPT(channel)) {
do_channel_tx(&pport->hsi_channel[channel]);
channels_served |= HSI_HST_DATAACCEPT(channel);
}
if (status_reg & HSI_HSR_DATAAVAILABLE(channel)) {
do_channel_rx(&pport->hsi_channel[channel]);
channels_served |= HSI_HSR_DATAAVAILABLE(channel);
}
}
if (status_reg & HSI_BREAKDETECTED) {
dev_info(hsi_ctrl->dev, "Hardware BREAK on port %d\n", port);
hsi_outl(0, base, HSI_HSR_BREAK_REG(port));
hsi_port_event_handler(pport, HSI_EVENT_BREAK_DETECTED, NULL);
channels_served |= HSI_BREAKDETECTED;
}
if (status_reg & HSI_ERROROCCURED) {
hsr_err_reg = hsi_inl(base, HSI_HSR_ERROR_REG(port));
dev_err(hsi_ctrl->dev, "HSI ERROR Port %d: 0x%x\n",
port, hsr_err_reg);
hsi_outl(hsr_err_reg, base, HSI_HSR_ERRORACK_REG(port));
if (hsr_err_reg) /* ignore spurious errors */
hsi_port_event_handler(pport, HSI_EVENT_ERROR, NULL);
else
dev_dbg(hsi_ctrl->dev, "Spurious HSI error!\n");
channels_served |= HSI_ERROROCCURED;
}
hsi_outl(channels_served, base, status_offset);
}
/* HST_ACCEPTED interrupt processing */
static void hsi_do_channel_tx(struct hsi_channel *ch)
{
struct hsi_dev *hsi_ctrl = ch->hsi_port->hsi_controller;
void __iomem *base = hsi_ctrl->base;
unsigned int n_ch;
unsigned int n_p;
unsigned int irq;
long buff_offset;
n_ch = ch->channel_number;
n_p = ch->hsi_port->port_number;
irq = ch->hsi_port->n_irq;
dev_dbg(hsi_ctrl->dev,
"Data Accepted interrupt for channel %d.\n", n_ch);
hsi_driver_disable_write_interrupt(ch);
if (ch->write_data.addr == NULL) {
dev_err(hsi_ctrl->dev, "Error, NULL Write address.\n");
hsi_reset_ch_write(ch);
} else {
buff_offset = hsi_hst_buffer_reg(hsi_ctrl, n_p, n_ch);
if (buff_offset >= 0) {
hsi_outl(*(ch->write_data.addr), base, buff_offset);
ch->write_data.addr = NULL;
}
}
spin_unlock(&hsi_ctrl->lock);
dev_dbg(hsi_ctrl->dev, "Calling ch %d write callback.\n", n_ch);
(*ch->write_done) (ch->dev, 1);
spin_lock(&hsi_ctrl->lock);
}
int hsi_runtime_resume(struct device *dev)
{
struct platform_device *pd = to_platform_device(dev);
struct hsi_dev *hsi_ctrl = platform_get_drvdata(pd);
struct hsi_platform_data *pdata = hsi_ctrl->dev->platform_data;
unsigned int i;
dev_dbg(dev, "%s\n", __func__);
if (hsi_ctrl->clock_enabled)
dev_warn(dev, "Warning: clock status mismatch vs runtime PM\n");
hsi_ctrl->clock_enabled = true;
/* Restore context */
hsi_restore_ctx(hsi_ctrl);
/* Restore HSR_MODE register value */
/* WARNING: works only in this configuration: */
/* - Flow = Synchronized */
/* - Mode = frame */
hsi_outl(HSI_HSR_MODE_FRAME, hsi_ctrl->base,
HSI_HSR_MODE_REG(HSI_PORT1));
/* When HSI is ON, no need for IO wakeup mechanism on any HSI port */
for (i = 0; i < hsi_ctrl->max_p; i++)
pdata->wakeup_disable(hsi_ctrl->hsi_port[i].port_number);
/* HSI device is now fully operational and _must_ be able to */
/* complete I/O operations */
return 0;
}
static u32 hsi_process_dma_event(struct hsi_dev *hsi_ctrl)
{
void __iomem *base = hsi_ctrl->base;
unsigned int gdd_lch = 0;
u32 status_reg = 0;
u32 lch_served = 0;
unsigned int gdd_max_count = hsi_ctrl->gdd_chan_count;
status_reg = hsi_inl(base, HSI_SYS_GDD_MPU_IRQ_STATUS_REG);
status_reg &= hsi_inl(base, HSI_SYS_GDD_MPU_IRQ_ENABLE_REG);
if (!status_reg) {
dev_dbg(hsi_ctrl->dev, "DMA : no event, exit.\n");
return 0;
}
for (gdd_lch = 0; gdd_lch < gdd_max_count; gdd_lch++) {
if (status_reg & HSI_GDD_LCH(gdd_lch)) {
do_hsi_gdd_lch(hsi_ctrl, gdd_lch);
lch_served |= HSI_GDD_LCH(gdd_lch);
}
}
/* Acknowledge interrupt for DMA channel */
hsi_outl(lch_served, base, HSI_SYS_GDD_MPU_IRQ_STATUS_REG);
return status_reg;
}
static void do_channel_tx(struct hsi_channel *ch)
{
struct hsi_dev *hsi_ctrl = ch->hsi_port->hsi_controller;
void __iomem *base = hsi_ctrl->base;
unsigned int n_ch;
unsigned int n_p;
unsigned int irq;
long buff_offset;
n_ch = ch->channel_number;
n_p = ch->hsi_port->port_number;
irq = ch->hsi_port->n_irq;
spin_lock(&hsi_ctrl->lock);
if (ch->write_data.addr == NULL) {
hsi_outl_and(~HSI_HST_DATAACCEPT(n_ch), base,
HSI_SYS_MPU_ENABLE_CH_REG(n_p, irq, n_ch));
hsi_reset_ch_write(ch);
spin_unlock(&hsi_ctrl->lock);
(*ch->write_done)(ch->dev, 1);
} else {
buff_offset = hsi_hst_buffer_reg(hsi_ctrl, n_p, n_ch);
if (buff_offset >= 0) {
hsi_outl(*(ch->write_data.addr), base, buff_offset);
ch->write_data.addr = NULL;
}
spin_unlock(&hsi_ctrl->lock);
}
}
/* hsi_driver_ack_interrupt - Acknowledge the CAWAKE, BREAK, or ERROR interrupt
for the given port
* @backup - indicate whether we shall look for the backup status interrupt
* register (HSI_Pp_M_IRQrU_STATUS) or the normal status interrupt
* register (HSI_Pp_M_IRQr_STATUS)
* Backup status interrupt register is used for CAWAKE only.
*/
void hsi_driver_ack_interrupt(struct hsi_port *pport, u32 flag, bool backup)
{
hsi_outl(flag, pport->hsi_controller->base,
HSI_SYS_MPU_STATUS_CH_REG(pport->port_number,
pport->n_irq,
backup ? HSI_SSI_CHANNELS_MAX :
0));
}
/**
* hsi_softreset - Force a SW RESET of HSI (core + DMA)
*
* @hsi_ctrl - reference to the hsi controller to be reset.
*
*/
int hsi_softreset(struct hsi_dev *hsi_ctrl)
{
unsigned int ind = 0;
unsigned int port;
void __iomem *base = hsi_ctrl->base;
u32 status;
/* HSI-C1BUG00088: i696 : HSI: Issue with SW reset
* No recovery from SW reset under specific circumstances
* If a SW RESET is done while some HSI errors are still not
* acknowledged, the HSR FSM is stucked. */
if (is_hsi_errata(hsi_ctrl, HSI_ERRATUM_i696_SW_RESET_FSM_STUCK)) {
for (port = 1; port <= hsi_ctrl->max_p; port++) {
hsi_outl_and(HSI_HSR_MODE_MODE_VAL_SLEEP, base,
HSI_HSR_MODE_REG(port));
hsi_outl(HSI_HSR_ERROR_ALL, base,
HSI_HSR_ERRORACK_REG(port));
}
}
/* Reseting HSI Block */
hsi_outl_or(HSI_SOFTRESET, base, HSI_SYS_SYSCONFIG_REG);
do {
status = hsi_inl(base, HSI_SYS_SYSSTATUS_REG);
ind++;
} while ((!(status & HSI_RESETDONE)) &&
(ind < HSI_RESETDONE_MAX_RETRIES));
if (ind >= HSI_RESETDONE_MAX_RETRIES) {
dev_err(hsi_ctrl->dev, "HSI SW_RESET failed to complete within"
" %d retries.\n", HSI_RESETDONE_MAX_RETRIES);
return -EIO;
} else if (ind > HSI_RESETDONE_NORMAL_RETRIES) {
dev_warn(hsi_ctrl->dev, "HSI SW_RESET abnormally long:"
" %d retries to complete.\n", ind);
}
ind = 0;
/* Reseting DMA Engine */
hsi_outl_or(HSI_GDD_GRST_SWRESET, base, HSI_GDD_GRST_REG);
do {
status = hsi_inl(base, HSI_GDD_GRST_REG);
ind++;
} while ((status & HSI_GDD_GRST_SWRESET) &&
(ind < HSI_RESETDONE_MAX_RETRIES));
if (ind >= HSI_RESETDONE_MAX_RETRIES) {
dev_err(hsi_ctrl->dev, "HSI DMA SW_RESET failed to complete"
" within %d retries.\n", HSI_RESETDONE_MAX_RETRIES);
return -EIO;
}
if (ind > HSI_RESETDONE_NORMAL_RETRIES) {
dev_warn(hsi_ctrl->dev, "HSI DMA SW_RESET abnormally long:"
" %d retries to complete.\n", ind);
}
return 0;
}
void hsi_set_pm_default(struct hsi_dev *hsi_ctrl)
{
#if 0 /* Huawei 3-wire HSI tests ... Remove later ****/
dpr_0("hsi_driver.c:%s. hsi_ctrl->id=%d,hsi_mode=0x%08X;\n",__func__,hsi_ctrl->id,hsi_ctrl->hsi_port[hsi_ctrl->id].hsi_mode); //Add for Flashless 3HSI dbg
if( (bool)(hsi_ctrl->hsi_port[hsi_ctrl->id].hsi_mode&XMM_HSI_PM_UNDFT)==true ) {//XMM_HSI_PM_UNDFT, HSI PM_unset_default标志;
hsi_set_pm_force_hsi_on(hsi_ctrl);
return;
}
#endif /* Huawei 3-wire HSI tests ... Remove later ****/
/* Set default SYSCONFIG PM settings */
hsi_outl((HSI_AUTOIDLE | HSI_SIDLEMODE_SMART_WAKEUP |
HSI_MIDLEMODE_SMART_WAKEUP),
hsi_ctrl->base, HSI_SYS_SYSCONFIG_REG);
hsi_outl(HSI_CLK_AUTOGATING_ON, hsi_ctrl->base, HSI_GDD_GCR_REG);
/* HSI_TODO : use the HWMOD API : omap_hwmod_set_slave_idlemode() */
}
/**
* hsi_softreset - Force a SW RESET of HSI (core + DMA)
*
* @hsi_ctrl - reference to the hsi controller to be reset.
*
*/
int hsi_softreset(struct hsi_dev *hsi_ctrl)
{
unsigned int ind = 0;
unsigned int port;
void __iomem *base = hsi_ctrl->base;
u32 status;
/* SW WA for HSI-C1BUG00088 OMAP4430 HSI : No recovery from SW reset */
/* under specific circumstances */
for (port = 1; port <= hsi_ctrl->max_p; port++) {
hsi_outl_and(HSI_HSR_MODE_MODE_VAL_SLEEP, base,
HSI_HSR_MODE_REG(port));
hsi_outl(HSI_HSR_ERROR_ALL, base, HSI_HSR_ERRORACK_REG(port));
}
/* Reseting HSI Block */
hsi_outl_or(HSI_SOFTRESET, base, HSI_SYS_SYSCONFIG_REG);
do {
status = hsi_inl(base, HSI_SYS_SYSSTATUS_REG);
ind++;
} while ((!(status & HSI_RESETDONE)) &&
(ind < HSI_RESETDONE_MAX_RETRIES));
if (ind >= HSI_RESETDONE_MAX_RETRIES) {
dev_err(hsi_ctrl->dev, "HSI SW_RESET failed to complete within"
" %d retries.\n", HSI_RESETDONE_MAX_RETRIES);
return -EIO;
} else if (ind > HSI_RESETDONE_NORMAL_RETRIES) {
dev_warn(hsi_ctrl->dev, "HSI SW_RESET abnormally long:"
" %d retries to complete.\n", ind);
}
ind = 0;
/* Reseting DMA Engine */
hsi_outl_or(HSI_GDD_GRST_SWRESET, base, HSI_GDD_GRST_REG);
do {
status = hsi_inl(base, HSI_GDD_GRST_REG);
ind++;
} while ((status & HSI_GDD_GRST_SWRESET) &&
(ind < HSI_RESETDONE_MAX_RETRIES));
if (ind >= HSI_RESETDONE_MAX_RETRIES) {
dev_err(hsi_ctrl->dev, "HSI DMA SW_RESET failed to complete"
" within %d retries.\n", HSI_RESETDONE_MAX_RETRIES);
return -EIO;
}
if (ind > HSI_RESETDONE_NORMAL_RETRIES) {
dev_warn(hsi_ctrl->dev, "HSI DMA SW_RESET abnormally long:"
" %d retries to complete.\n", ind);
}
return 0;
}
void hsi_hsr_resume(struct hsi_dev *hsi_ctrl)
{
struct hsi_platform_data *pdata = hsi_ctrl->dev->platform_data;
void __iomem *base = hsi_ctrl->base;
struct hsi_port_ctx *p;
int port;
dev_dbg(hsi_ctrl->dev, "%s\n", __func__);
for (port = 1; port <= pdata->num_ports; port++) {
p = &pdata->ctx->pctx[port - 1];
hsi_outl(p->hsr.mode, base, HSI_HSR_MODE_REG(port));
}
}
static void __init set_hsi_ports_default(struct hsi_dev *hsi_ctrl,
struct platform_device *pd)
{
struct port_ctx *cfg;
struct hsi_platform_data *pdata = pd->dev.platform_data;
unsigned int port = 0;
void __iomem *base = hsi_ctrl->base;
struct platform_device *pdev = to_platform_device(hsi_ctrl->dev);
for (port = 1; port <= pdata->num_ports; port++) {
cfg = &pdata->ctx.pctx[port - 1];
hsi_outl(cfg->hst.mode | cfg->hst.flow | HSI_MODE_WAKE_CTRL_SW,
base, HSI_HST_MODE_REG(port));
if (!hsi_driver_device_is_hsi(pdev))
hsi_outl(cfg->hst.frame_size, base,
HSI_HST_FRAMESIZE_REG(port));
hsi_outl(cfg->hst.divisor, base, HSI_HST_DIVISOR_REG(port));
hsi_outl(cfg->hst.channels, base, HSI_HST_CHANNELS_REG(port));
hsi_outl(cfg->hst.arb_mode, base, HSI_HST_ARBMODE_REG(port));
hsi_outl(cfg->hsr.mode | cfg->hsr.flow, base,
HSI_HSR_MODE_REG(port));
hsi_outl(cfg->hsr.frame_size, base,
HSI_HSR_FRAMESIZE_REG(port));
hsi_outl(cfg->hsr.channels, base, HSI_HSR_CHANNELS_REG(port));
if (hsi_driver_device_is_hsi(pdev))
hsi_outl(cfg->hsr.divisor, base,
HSI_HSR_DIVISOR_REG(port));
hsi_outl(cfg->hsr.timeout, base, HSI_HSR_COUNTERS_REG(port));
}
if (hsi_driver_device_is_hsi(pdev)) {
/* SW strategy for HSI fifo management can be changed here */
hsi_fifo_mapping(hsi_ctrl, HSI_FIFO_MAPPING_DEFAULT);
}
}
/**
* hsi_driver_cancel_write_dma - Cancel an ongoing GDD [DMA] write for the
* specified hsi channel.
* @hsi_ch - pointer to the hsi_channel to cancel DMA write.
*
* hsi_controller lock must be held before calling this function.
*
* Return: -ENXIO : No DMA channel found for specified HSI channel
* -ECANCELED : DMA cancel success, data not transfered to TX FIFO
* 0 : DMA transfer is already over, data already transfered to TX FIFO
*
* Note: whatever returned value, write callback will not be called after
* write cancel.
*/
int hsi_driver_cancel_write_dma(struct hsi_channel *hsi_ch)
{
int lch = hsi_ch->write_data.lch;
unsigned int port = hsi_ch->hsi_port->port_number;
unsigned int channel = hsi_ch->channel_number;
struct hsi_dev *hsi_ctrl = hsi_ch->hsi_port->hsi_controller;
u16 ccr, gdd_csr;
long buff_offset;
u32 status_reg;
dma_addr_t dma_h;
size_t size;
if (lch < 0) {
dev_err(&hsi_ch->dev->device, "No DMA channel found for HSI "
"channel %d\n", hsi_ch->channel_number);
return -ENXIO;
}
ccr = hsi_inw(hsi_ctrl->base, HSI_GDD_CCR_REG(lch));
if (!(ccr & HSI_CCR_ENABLE)) {
dev_dbg(&hsi_ch->dev->device, "Write cancel on not "
"enabled logical channel %d CCR REG 0x%04X\n",
lch, ccr);
}
status_reg = hsi_inl(hsi_ctrl->base, HSI_SYS_GDD_MPU_IRQ_STATUS_REG);
status_reg &= hsi_inl(hsi_ctrl->base, HSI_SYS_GDD_MPU_IRQ_ENABLE_REG);
hsi_outw_and(~HSI_CCR_ENABLE, hsi_ctrl->base, HSI_GDD_CCR_REG(lch));
/* Clear CSR register by reading it, as it is cleared automaticaly */
/* by HW after SW read. */
gdd_csr = hsi_inw(hsi_ctrl->base, HSI_GDD_CSR_REG(lch));
hsi_outl_and(~HSI_GDD_LCH(lch), hsi_ctrl->base,
HSI_SYS_GDD_MPU_IRQ_ENABLE_REG);
hsi_outl(HSI_GDD_LCH(lch), hsi_ctrl->base,
HSI_SYS_GDD_MPU_IRQ_STATUS_REG);
/* Unmap DMA region */
dma_h = hsi_inl(hsi_ctrl->base, HSI_GDD_CSSA_REG(lch));
size = hsi_inw(hsi_ctrl->base, HSI_GDD_CEN_REG(lch)) * 4;
dma_unmap_single(hsi_ctrl->dev, dma_h, size, DMA_TO_DEVICE);
buff_offset = hsi_hst_bufstate_f_reg(hsi_ctrl, port, channel);
if (buff_offset >= 0)
hsi_outl_and(~HSI_BUFSTATE_CHANNEL(channel), hsi_ctrl->base,
buff_offset);
hsi_reset_ch_write(hsi_ch);
return status_reg & HSI_GDD_LCH(lch) ? 0 : -ECANCELED;
}
void hsi_hsr_resume(struct hsi_dev *hsi_ctrl)
{
struct hsi_platform_data *pdata = hsi_ctrl->dev->platform_data;
void __iomem *base = hsi_ctrl->base;
struct hsi_port_ctx *p;
int port;
dev_dbg(hsi_ctrl->dev, "%s\n", __func__);
/* Move HSR from MODE_VAL.SLEEP to the relevant mode. */
/* This will enable the ACREADY flow control mechanism. */
for (port = 1; port <= pdata->num_ports; port++) {
p = &pdata->ctx->pctx[port - 1];
hsi_outl(p->hsr.mode, base, HSI_HSR_MODE_REG(port));
}
}
/**
* hsi_driver_cancel_read_dma - Cancel an ongoing GDD [DMA] read for the
* specified hsi channel.
* @hsi_ch - pointer to the hsi_channel to cancel DMA read.
*
* hsi_controller lock must be held before calling this function.
*
* Return: -ENXIO : No DMA channel found for specified HSI channel
* -ECANCELED : DMA cancel success, data not available at expected
* address.
* 0 : DMA transfer is already over, data already available at
* expected address.
*
* Note: whatever returned value, read callback will not be called after cancel.
*/
int hsi_driver_cancel_read_dma(struct hsi_channel *hsi_ch)
{
int lch = hsi_ch->read_data.lch;
struct hsi_dev *hsi_ctrl = hsi_ch->hsi_port->hsi_controller;
u16 ccr, gdd_csr;
u32 status_reg;
dma_addr_t dma_h;
size_t size;
/* Re-enable interrupts for polling if needed */
if (hsi_ch->flags & HSI_CH_RX_POLL)
hsi_driver_enable_read_interrupt(hsi_ch, NULL);
if (lch < 0) {
dev_err(&hsi_ch->dev->device, "No DMA channel found for HSI "
"channel %d\n", hsi_ch->channel_number);
return -ENXIO;
}
ccr = hsi_inw(hsi_ctrl->base, HSI_GDD_CCR_REG(lch));
if (!(ccr & HSI_CCR_ENABLE)) {
dev_dbg(&hsi_ch->dev->device, "Read cancel on not "
"enabled logical channel %d CCR REG 0x%04X\n",
lch, ccr);
}
status_reg = hsi_inl(hsi_ctrl->base, HSI_SYS_GDD_MPU_IRQ_STATUS_REG);
status_reg &= hsi_inl(hsi_ctrl->base, HSI_SYS_GDD_MPU_IRQ_ENABLE_REG);
hsi_outw_and(~HSI_CCR_ENABLE, hsi_ctrl->base, HSI_GDD_CCR_REG(lch));
/* Clear CSR register by reading it, as it is cleared automaticaly */
/* by HW after SW read */
gdd_csr = hsi_inw(hsi_ctrl->base, HSI_GDD_CSR_REG(lch));
hsi_outl_and(~HSI_GDD_LCH(lch), hsi_ctrl->base,
HSI_SYS_GDD_MPU_IRQ_ENABLE_REG);
hsi_outl(HSI_GDD_LCH(lch), hsi_ctrl->base,
HSI_SYS_GDD_MPU_IRQ_STATUS_REG);
/* Unmap DMA region - Access to the buffer is now safe */
dma_h = hsi_inl(hsi_ctrl->base, HSI_GDD_CDSA_REG(lch));
size = hsi_inw(hsi_ctrl->base, HSI_GDD_CEN_REG(lch)) * 4;
dma_unmap_single(hsi_ctrl->dev, dma_h, size, DMA_FROM_DEVICE);
hsi_reset_ch_read(hsi_ch);
return status_reg & HSI_GDD_LCH(lch) ? 0 : -ECANCELED;
}
/* Manage HSR divisor update
* A special divisor value allows switching to auto-divisor mode in Rx
* (but with error counters deactivated). This function implements the
* the transitions to/from this mode.
*/
int hsi_set_rx_divisor(struct hsi_port *sport, struct hsr_ctx *cfg)
{
struct hsi_dev *hsi_ctrl = sport->hsi_controller;
void __iomem *base = hsi_ctrl->base;
int port = sport->port_number;
struct platform_device *pdev = to_platform_device(hsi_ctrl->dev);
if (cfg->divisor == NOT_SET)
return 0;
if (hsi_driver_device_is_hsi(pdev)) {
if (cfg->divisor == HSI_HSR_DIVISOR_AUTO &&
sport->counters_on) {
/* auto mode: deactivate counters + set divisor = 0 */
sport->reg_counters = hsi_inl(base, HSI_HSR_COUNTERS_REG
(port));
sport->counters_on = 0;
hsi_outl(0, base, HSI_HSR_COUNTERS_REG(port));
hsi_outl(0, base, HSI_HSR_DIVISOR_REG(port));
dev_dbg(hsi_ctrl->dev, "Switched to HSR auto mode\n");
} else if (cfg->divisor != HSI_HSR_DIVISOR_AUTO) {
/* Divisor set mode: use counters */
/* Leave auto mode: use new counters values */
sport->reg_counters = cfg->counters;
sport->counters_on = 1;
hsi_outl(cfg->counters, base,
HSI_HSR_COUNTERS_REG(port));
hsi_outl(cfg->divisor, base, HSI_HSR_DIVISOR_REG(port));
dev_dbg(hsi_ctrl->dev, "Left HSR auto mode. "
"Counters=0x%08x, Divisor=0x%08x\n",
cfg->counters, cfg->divisor);
}
} else {
if (cfg->divisor == HSI_HSR_DIVISOR_AUTO &&
sport->counters_on) {
/* auto mode: deactivate timeout */
sport->reg_counters = hsi_inl(base,
SSI_TIMEOUT_REG(port));
sport->counters_on = 0;
hsi_outl(0, base, SSI_TIMEOUT_REG(port));
dev_dbg(hsi_ctrl->dev, "Deactivated SSR timeout\n");
} else if (cfg->divisor == HSI_SSR_DIVISOR_USE_TIMEOUT) {
/* Leave auto mode: use new counters values */
sport->reg_counters = cfg->counters;
sport->counters_on = 1;
hsi_outl(cfg->counters, base, SSI_TIMEOUT_REG(port));
dev_dbg(hsi_ctrl->dev, "Left SSR auto mode. "
"Timeout=0x%08x\n", cfg->counters);
}
}
return 0;
}
int hsi_set_rx(struct hsi_port *sport, struct hsr_ctx *cfg)
{
struct hsi_dev *hsi_ctrl = sport->hsi_controller;
void __iomem *base = hsi_ctrl->base;
int port = sport->port_number;
struct platform_device *pdev = to_platform_device(hsi_ctrl->dev);
if (((cfg->mode & HSI_MODE_VAL_MASK) != HSI_MODE_STREAM) &&
((cfg->mode & HSI_MODE_VAL_MASK) != HSI_MODE_FRAME) &&
((cfg->mode & HSI_MODE_VAL_MASK) != HSI_MODE_SLEEP) &&
(cfg->mode != NOT_SET))
return -EINVAL;
if (hsi_driver_device_is_hsi(pdev)) {
if (((cfg->flow & HSI_FLOW_VAL_MASK) != HSI_FLOW_SYNCHRONIZED)
&& ((cfg->flow & HSI_FLOW_VAL_MASK) != HSI_FLOW_PIPELINED)
&& (cfg->flow != NOT_SET))
return -EINVAL;
/* HSI only supports payload size of 32bits */
if ((cfg->frame_size != HSI_FRAMESIZE_MAX) &&
(cfg->frame_size != NOT_SET))
return -EINVAL;
} else {
if (((cfg->flow & HSI_FLOW_VAL_MASK) != HSI_FLOW_SYNCHRONIZED)
&& (cfg->flow != NOT_SET))
return -EINVAL;
/* HSI only supports payload size of 32bits */
if ((cfg->frame_size != HSI_FRAMESIZE_MAX) &&
(cfg->frame_size != NOT_SET))
return -EINVAL;
}
if ((cfg->channels == 0) ||
((cfg->channels > sport->max_ch) && (cfg->channels != NOT_SET)))
return -EINVAL;
if (hsi_driver_device_is_hsi(pdev)) {
if ((cfg->divisor > HSI_MAX_RX_DIVISOR) &&
(cfg->divisor != HSI_HSR_DIVISOR_AUTO) &&
(cfg->divisor != NOT_SET))
return -EINVAL;
}
if ((cfg->mode != NOT_SET) && (cfg->flow != NOT_SET))
hsi_outl(cfg->mode | ((cfg->flow & HSI_FLOW_VAL_MASK)
<< HSI_FLOW_OFFSET), base,
HSI_HSR_MODE_REG(port));
if (cfg->frame_size != NOT_SET)
hsi_outl(cfg->frame_size, base, HSI_HSR_FRAMESIZE_REG(port));
if (cfg->channels != NOT_SET) {
if ((cfg->channels & (-cfg->channels)) ^ cfg->channels)
return -EINVAL;
else
hsi_outl(cfg->channels, base,
HSI_HSR_CHANNELS_REG(port));
}
return hsi_set_rx_divisor(sport, cfg);
}
/**
* hsi_ioctl - HSI I/O control
* @dev - hsi device channel reference to apply the I/O control
* (or port associated to it)
* @command - HSI I/O control command
* @arg - parameter associated to the control command. NULL, if no parameter.
*
* Return 0 on success, a negative value on failure.
*
*/
int hsi_ioctl(struct hsi_device *dev, unsigned int command, void *arg)
{
struct hsi_channel *ch;
struct hsi_dev *hsi_ctrl;
struct hsi_port *pport;
void __iomem *base;
unsigned int port, channel;
u32 acwake;
int err = 0;
int fifo = 0;
u8 ret;
struct hsi_platform_data *pdata;
if (unlikely((!dev) ||
(!dev->ch) ||
(!dev->ch->hsi_port) ||
(!dev->ch->hsi_port->hsi_controller)) ||
(!(dev->ch->flags & HSI_CH_OPEN))) {
pr_err(LOG_NAME "HSI IOCTL Invalid parameter\n");
return -EINVAL;
}
ch = dev->ch;
pport = ch->hsi_port;
hsi_ctrl = ch->hsi_port->hsi_controller;
port = ch->hsi_port->port_number;
channel = ch->channel_number;
base = hsi_ctrl->base;
dev_dbg(hsi_ctrl->dev, "IOCTL: ch %d, command %d\n", channel, command);
spin_lock_bh(&hsi_ctrl->lock);
hsi_clocks_enable_channel(hsi_ctrl->dev, channel, __func__);
switch (command) {
case HSI_IOCTL_ACWAKE_UP:
/* Wake up request to Modem (typically OMAP initiated) */
/* Symetrical disable will be done in HSI_IOCTL_ACWAKE_DOWN */
if (ch->flags & HSI_CH_ACWAKE) {
dev_dbg(hsi_ctrl->dev, "Duplicate ACWAKE UP\n");
err = -EPERM;
goto out;
}
ch->flags |= HSI_CH_ACWAKE;
pport->acwake_status |= BIT(channel);
/* We only claim once the wake line per channel */
acwake = hsi_inl(base, HSI_SYS_WAKE_REG(port));
if (!(acwake & HSI_WAKE(channel))) {
hsi_outl(HSI_SET_WAKE(channel), base,
HSI_SYS_SET_WAKE_REG(port));
}
goto out;
break;
case HSI_IOCTL_ACWAKE_DOWN:
/* Low power request initiation (OMAP initiated, typically */
/* following inactivity timeout) */
/* ACPU HSI block shall still be capable of receiving */
if (!(ch->flags & HSI_CH_ACWAKE)) {
dev_dbg(hsi_ctrl->dev, "Duplicate ACWAKE DOWN\n");
err = -EPERM;
goto out;
}
acwake = hsi_inl(base, HSI_SYS_WAKE_REG(port));
if (unlikely(pport->acwake_status !=
(acwake & HSI_WAKE_MASK))) {
dev_warn(hsi_ctrl->dev,
"ACWAKE shadow register mismatch"
" acwake_status: 0x%x, HSI_SYS_WAKE_REG: 0x%x",
pport->acwake_status, acwake);
pport->acwake_status = acwake & HSI_WAKE_MASK;
}
/* SSI_TODO: add safety check for SSI also */
ch->flags &= ~HSI_CH_ACWAKE;
pport->acwake_status &= ~BIT(channel);
/* Release the wake line per channel */
if ((acwake & HSI_WAKE(channel))) {
hsi_outl(HSI_CLEAR_WAKE(channel), base,
HSI_SYS_CLEAR_WAKE_REG(port));
}
goto out;
break;
case HSI_IOCTL_SEND_BREAK:
hsi_outl(1, base, HSI_HST_BREAK_REG(port));
/*HSI_TODO : need to deactivate clock after BREAK frames sent*/
/*Use interrupt ? (if TX BREAK INT exists)*/
break;
case HSI_IOCTL_GET_ACWAKE:
if (!arg) {
err = -EINVAL;
goto out;
}
*(u32 *)arg = hsi_inl(base, HSI_SYS_WAKE_REG(port));
break;
case HSI_IOCTL_FLUSH_RX:
ret = hsi_hsr_fifo_flush_channel(hsi_ctrl, port, channel);
if (arg)
*(size_t *)arg = ret;
/* Ack the RX Int */
hsi_outl_and(~HSI_HSR_DATAAVAILABLE(channel), base,
HSI_SYS_MPU_STATUS_CH_REG(port, pport->n_irq,
channel));
break;
case HSI_IOCTL_FLUSH_TX:
ret = hsi_hst_fifo_flush_channel(hsi_ctrl, port, channel);
if (arg)
*(size_t *)arg = ret;
/* Ack the TX Int */
hsi_outl_and(~HSI_HST_DATAACCEPT(channel), base,
HSI_SYS_MPU_STATUS_CH_REG(port, pport->n_irq,
channel));
break;
case HSI_IOCTL_GET_CAWAKE:
if (!arg) {
err = -EINVAL;
goto out;
}
err = hsi_get_cawake(dev->ch->hsi_port);
if (err < 0) {
err = -ENODEV;
goto out;
}
*(u32 *)arg = err;
break;
case HSI_IOCTL_SET_RX:
if (!arg) {
err = -EINVAL;
goto out;
}
err = hsi_set_rx(dev->ch->hsi_port, (struct hsr_ctx *)arg);
break;
case HSI_IOCTL_GET_RX:
if (!arg) {
err = -EINVAL;
goto out;
}
hsi_get_rx(dev->ch->hsi_port, (struct hsr_ctx *)arg);
break;
case HSI_IOCTL_SET_TX:
if (!arg) {
err = -EINVAL;
goto out;
}
err = hsi_set_tx(dev->ch->hsi_port, (struct hst_ctx *)arg);
break;
case HSI_IOCTL_GET_TX:
if (!arg) {
err = -EINVAL;
goto out;
}
hsi_get_tx(dev->ch->hsi_port, (struct hst_ctx *)arg);
break;
case HSI_IOCTL_SW_RESET:
dev_info(hsi_ctrl->dev, "SW Reset\n");
err = hsi_softreset(hsi_ctrl);
/* Reset HSI config to default */
hsi_softreset_driver(hsi_ctrl);
break;
case HSI_IOCTL_GET_FIFO_OCCUPANCY:
if (!arg) {
err = -EINVAL;
goto out;
}
fifo = hsi_fifo_get_id(hsi_ctrl, channel, port);
if (unlikely(fifo < 0)) {
dev_err(hsi_ctrl->dev, "No valid FIFO id found for "
"channel %d.\n", channel);
err = -EFAULT;
goto out;
}
*(size_t *)arg = hsi_get_rx_fifo_occupancy(hsi_ctrl, fifo);
break;
case HSI_IOCTL_SET_WAKE_RX_3WIRES_MODE:
dev_info(hsi_ctrl->dev,
"Entering RX wakeup in 3 wires mode (no CAWAKE)\n");
pport->wake_rx_3_wires_mode = 1;
/* HSI-C1BUG00085: ixxx: HSI wakeup issue in 3 wires mode
* HSI will NOT generate the Swakeup for 2nd frame if it entered
* IDLE after 1st received frame */
if (is_hsi_errata(hsi_ctrl, HSI_ERRATUM_ixxx_3WIRES_NO_SWAKEUP))
if (hsi_driver_device_is_hsi(to_platform_device
(hsi_ctrl->dev)))
hsi_set_pm_force_hsi_on(hsi_ctrl);
/* When WAKE is not available, ACREADY must be set to 1 at
* reset else remote will never have a chance to transmit. */
hsi_outl_or(HSI_SET_WAKE_3_WIRES | HSI_SET_WAKE_READY_LVL_1,
base, HSI_SYS_SET_WAKE_REG(port));
hsi_driver_disable_interrupt(pport, HSI_CAWAKEDETECTED);
break;
case HSI_IOCTL_SET_WAKE_RX_4WIRES_MODE:
dev_info(hsi_ctrl->dev, "Entering RX wakeup in 4 wires mode\n");
pport->wake_rx_3_wires_mode = 0;
/* HSI-C1BUG00085: ixxx: HSI wakeup issue in 3 wires mode
* HSI will NOT generate the Swakeup for 2nd frame if it entered
* IDLE after 1st received frame */
if (is_hsi_errata(hsi_ctrl, HSI_ERRATUM_ixxx_3WIRES_NO_SWAKEUP))
if (hsi_driver_device_is_hsi(to_platform_device
(hsi_ctrl->dev)))
hsi_set_pm_default(hsi_ctrl);
hsi_driver_enable_interrupt(pport, HSI_CAWAKEDETECTED);
hsi_outl_and(HSI_SET_WAKE_3_WIRES_MASK, base,
HSI_SYS_SET_WAKE_REG(port));
break;
case HSI_IOCTL_SET_HI_SPEED:
if (!arg) {
err = -EINVAL;
goto out;
}
hsi_ctrl->hsi_fclk_req = *(unsigned int *)arg ?
HSI_FCLK_HI_SPEED : HSI_FCLK_LOW_SPEED;
if (hsi_ctrl->hsi_fclk_req == hsi_ctrl->hsi_fclk_current) {
dev_dbg(hsi_ctrl->dev, "HSI FClk already @%ldHz\n",
hsi_ctrl->hsi_fclk_current);
goto out;
}
if (hsi_is_controller_transfer_ongoing(hsi_ctrl)) {
err = -EBUSY;
goto out;
}
hsi_ctrl->clock_change_ongoing = true;
spin_unlock_bh(&hsi_ctrl->lock);
pdata = dev_get_platdata(hsi_ctrl->dev);
/* Set the HSI FCLK to requested value. */
err = pdata->device_scale(hsi_ctrl->dev, hsi_ctrl->dev,
hsi_ctrl->hsi_fclk_req);
if (err < 0) {
dev_err(hsi_ctrl->dev, "%s: Cannot set HSI FClk to"
" %ldHz, err %d\n", __func__,
hsi_ctrl->hsi_fclk_req, err);
} else {
dev_info(hsi_ctrl->dev, "HSI FClk changed from %ldHz to"
" %ldHz\n", hsi_ctrl->hsi_fclk_current,
hsi_ctrl->hsi_fclk_req);
hsi_ctrl->hsi_fclk_current = hsi_ctrl->hsi_fclk_req;
}
spin_lock_bh(&hsi_ctrl->lock);
hsi_ctrl->clock_change_ongoing = false;
break;
case HSI_IOCTL_GET_SPEED:
if (!arg) {
err = -EINVAL;
goto out;
}
*(unsigned long *)arg = hsi_ctrl->hsi_fclk_current;
break;
default:
err = -ENOIOCTLCMD;
break;
}
out:
/* All IOCTL end by disabling the clocks, except ACWAKE high. */
hsi_clocks_disable_channel(hsi_ctrl->dev, channel, __func__);
spin_unlock_bh(&hsi_ctrl->lock);
return err;
}
void hsi_restore_ctx(struct hsi_dev *hsi_ctrl)
{
struct hsi_platform_data *pdata = hsi_ctrl->dev->platform_data;
struct platform_device *pdev = to_platform_device(hsi_ctrl->dev);
void __iomem *base = hsi_ctrl->base;
struct hsi_port_ctx *p;
int port;
hsi_outl(pdata->ctx->sysconfig, base, HSI_SYS_SYSCONFIG_REG);
hsi_outl(pdata->ctx->gdd_gcr, base, HSI_GDD_GCR_REG);
if (hsi_driver_device_is_hsi(pdev))
hsi_outl(pdata->ctx->dll, base, HSI_HSR_DLL_REG);
for (port = 1; port <= pdata->num_ports; port++) {
p = &pdata->ctx->pctx[port - 1];
/* HSI TOP */
hsi_outl(p->sys_mpu_enable[0], base,
HSI_SYS_MPU_ENABLE_REG(port, 0));
hsi_outl(p->sys_mpu_enable[1], base,
HSI_SYS_MPU_U_ENABLE_REG(port, 0));
/* HST */
hsi_outl(p->hst.mode, base, HSI_HST_MODE_REG(port));
if (!hsi_driver_device_is_hsi(pdev))
hsi_outl(p->hst.frame_size, base,
HSI_HST_FRAMESIZE_REG(port));
hsi_outl(p->hst.divisor, base, HSI_HST_DIVISOR_REG(port));
hsi_outl(p->hst.channels, base, HSI_HST_CHANNELS_REG(port));
hsi_outl(p->hst.arb_mode, base, HSI_HST_ARBMODE_REG(port));
/* HSR */
if (!hsi_driver_device_is_hsi(pdev))
hsi_outl(p->hsr.frame_size, base,
HSI_HSR_FRAMESIZE_REG(port));
hsi_outl(p->hsr.divisor, base, HSI_HSR_DIVISOR_REG(port));
hsi_outl(p->hsr.channels, base, HSI_HSR_CHANNELS_REG(port));
hsi_outl(p->hsr.counters, base, HSI_HSR_COUNTERS_REG(port));
}
if (hsi_driver_device_is_hsi(pdev)) {
/* SW strategy for HSI fifo management can be changed here */
hsi_fifo_mapping(hsi_ctrl, hsi_ctrl->fifo_mapping_strategy);
}
/* As a last step move HSR from MODE_VAL.SLEEP to the relevant mode. */
/* This will enable the ACREADY flow control mechanism. */
for (port = 1; port <= pdata->num_ports; port++) {
p = &pdata->ctx->pctx[port - 1];
hsi_outl(p->hsr.mode, base, HSI_HSR_MODE_REG(port));
}
}
/**
* hsi_ioctl - HSI I/O control
* @dev - hsi device channel reference to apply the I/O control
* (or port associated to it)
* @command - HSI I/O control command
* @arg - parameter associated to the control command. NULL, if no parameter.
*
* Return 0 on success, a negative value on failure.
*
*/
int hsi_ioctl(struct hsi_device *dev, unsigned int command, void *arg)
{
struct hsi_channel *ch;
struct hsi_dev *hsi_ctrl;
struct hsi_port *pport;
void __iomem *base;
unsigned int port, channel;
u32 acwake;
int err = 0;
int fifo = 0;
if (unlikely((!dev) ||
(!dev->ch) ||
(!dev->ch->hsi_port) ||
(!dev->ch->hsi_port->hsi_controller)) ||
(!(dev->ch->flags & HSI_CH_OPEN))) {
pr_err(LOG_NAME "HSI IOCTL Invalid parameter\n");
return -EINVAL;
}
ch = dev->ch;
pport = ch->hsi_port;
hsi_ctrl = ch->hsi_port->hsi_controller;
port = ch->hsi_port->port_number;
channel = ch->channel_number;
base = hsi_ctrl->base;
dev_dbg(dev->device.parent, "IOCTL: ch %d, command %d\n",
channel, command);
spin_lock_bh(&hsi_ctrl->lock);
hsi_clocks_enable_channel(dev->device.parent, channel, __func__);
switch (command) {
case HSI_IOCTL_ACWAKE_UP:
if (ch->flags & HSI_CH_ACWAKE) {
dev_dbg(dev->device.parent, "Duplicate ACWAKE UP\n");
err = -EPERM;
goto out;
}
/* Wake up request to Modem (typically OMAP initiated) */
/* Symetrical disable will be done in HSI_IOCTL_ACWAKE_DOWN */
ch->flags |= HSI_CH_ACWAKE;
pport->acwake_status |= BIT(channel);
/* We only claim once the wake line per channel */
acwake = hsi_inl(base, HSI_SYS_WAKE_REG(port));
if (!(acwake & HSI_WAKE(channel))) {
hsi_outl(HSI_SET_WAKE(channel), base,
HSI_SYS_SET_WAKE_REG(port));
}
goto out;
break;
case HSI_IOCTL_ACWAKE_DOWN:
/* Low power request initiation (OMAP initiated, typically */
/* following inactivity timeout) */
/* ACPU HSI block shall still be capable of receiving */
if (!(ch->flags & HSI_CH_ACWAKE)) {
dev_dbg(dev->device.parent, "Duplicate ACWAKE DOWN\n");
err = -EPERM;
goto out;
}
acwake = hsi_inl(base, HSI_SYS_WAKE_REG(port));
if (unlikely(pport->acwake_status !=
(acwake & HSI_WAKE_MASK))) {
dev_warn(dev->device.parent,
"ACWAKE shadow register mismatch"
" acwake_status: 0x%x, HSI_SYS_WAKE_REG: 0x%x",
pport->acwake_status, acwake);
pport->acwake_status = acwake & HSI_WAKE_MASK;
}
/* SSI_TODO: add safety check for SSI also */
ch->flags &= ~HSI_CH_ACWAKE;
pport->acwake_status &= ~BIT(channel);
/* Release the wake line per channel */
if ((acwake & HSI_WAKE(channel))) {
hsi_outl(HSI_CLEAR_WAKE(channel), base,
HSI_SYS_CLEAR_WAKE_REG(port));
}
goto out;
break;
case HSI_IOCTL_SEND_BREAK:
hsi_outl(1, base, HSI_HST_BREAK_REG(port));
/*HSI_TODO : need to deactivate clock after BREAK frames sent*/
/*Use interrupt ? (if TX BREAK INT exists)*/
break;
case HSI_IOCTL_GET_ACWAKE:
if (!arg) {
err = -EINVAL;
goto out;
}
*(u32 *)arg = hsi_inl(base, HSI_SYS_WAKE_REG(port));
break;
case HSI_IOCTL_FLUSH_RX:
hsi_outl(0, base, HSI_HSR_RXSTATE_REG(port));
break;
case HSI_IOCTL_FLUSH_TX:
hsi_outl(0, base, HSI_HST_TXSTATE_REG(port));
break;
case HSI_IOCTL_GET_CAWAKE:
if (!arg) {
err = -EINVAL;
goto out;
}
err = hsi_get_cawake(dev->ch->hsi_port);
if (err < 0) {
err = -ENODEV;
goto out;
}
*(u32 *)arg = err;
break;
case HSI_IOCTL_SET_RX:
if (!arg) {
err = -EINVAL;
goto out;
}
err = hsi_set_rx(dev->ch->hsi_port, (struct hsr_ctx *)arg);
break;
case HSI_IOCTL_GET_RX:
if (!arg) {
err = -EINVAL;
goto out;
}
hsi_get_rx(dev->ch->hsi_port, (struct hsr_ctx *)arg);
break;
case HSI_IOCTL_SET_TX:
if (!arg) {
err = -EINVAL;
goto out;
}
err = hsi_set_tx(dev->ch->hsi_port, (struct hst_ctx *)arg);
break;
case HSI_IOCTL_GET_TX:
if (!arg) {
err = -EINVAL;
goto out;
}
hsi_get_tx(dev->ch->hsi_port, (struct hst_ctx *)arg);
break;
case HSI_IOCTL_SW_RESET:
dev_info(dev->device.parent, "SW Reset\n");
err = hsi_softreset(hsi_ctrl);
/* Reset HSI config to default */
hsi_softreset_driver(hsi_ctrl);
break;
case HSI_IOCTL_GET_FIFO_OCCUPANCY:
if (!arg) {
err = -EINVAL;
goto out;
}
fifo = hsi_fifo_get_id(hsi_ctrl, channel, port);
if (unlikely(fifo < 0)) {
dev_err(hsi_ctrl->dev, "No valid FIFO id found for "
"channel %d.\n", channel);
err = -EFAULT;
goto out;
}
*(size_t *)arg = hsi_get_rx_fifo_occupancy(hsi_ctrl, fifo);
break;
default:
err = -ENOIOCTLCMD;
break;
}
out:
/* All IOCTL end by disabling the clocks, except ACWAKE high. */
hsi_clocks_disable_channel(dev->device.parent, channel, __func__);
spin_unlock_bh(&hsi_ctrl->lock);
return err;
}
void hsi_restore_ctx(struct hsi_dev *hsi_ctrl)
{
struct hsi_platform_data *pdata = hsi_ctrl->dev->platform_data;
struct platform_device *pdev = to_platform_device(hsi_ctrl->dev);
void __iomem *base = hsi_ctrl->base;
struct port_ctx *p;
int port;
hsi_outl(pdata->ctx->sysconfig, base, HSI_SYS_SYSCONFIG_REG);
hsi_outl(pdata->ctx->gdd_gcr, base, HSI_GDD_GCR_REG);
if (hsi_driver_device_is_hsi(pdev))
hsi_outl(pdata->ctx->dll, base, HSI_HSR_DLL_REG);
for (port = 1; port <= pdata->num_ports; port++) {
p = &pdata->ctx->pctx[port - 1];
/* HSI TOP */
hsi_outl(p->sys_mpu_enable[0], base,
HSI_SYS_MPU_ENABLE_REG(port, 0));
hsi_outl(p->sys_mpu_enable[1], base,
HSI_SYS_MPU_U_ENABLE_REG(port, 0));
/* HST */
hsi_outl(p->hst.mode, base, HSI_HST_MODE_REG(port));
if (!hsi_driver_device_is_hsi(pdev))
hsi_outl(p->hst.frame_size, base,
HSI_HST_FRAMESIZE_REG(port));
hsi_outl(p->hst.divisor, base, HSI_HST_DIVISOR_REG(port));
hsi_outl(p->hst.channels, base, HSI_HST_CHANNELS_REG(port));
hsi_outl(p->hst.arb_mode, base, HSI_HST_ARBMODE_REG(port));
/* HSR */
hsi_outl(p->hsr.mode, base, HSI_HSR_MODE_REG(port));
if (!hsi_driver_device_is_hsi(pdev))
hsi_outl(p->hsr.frame_size, base,
HSI_HSR_FRAMESIZE_REG(port));
hsi_outl(p->hsr.divisor, base, HSI_HSR_DIVISOR_REG(port));
hsi_outl(p->hsr.channels, base, HSI_HSR_CHANNELS_REG(port));
hsi_outl(p->hsr.counters, base, HSI_HSR_COUNTERS_REG(port));
}
if (hsi_driver_device_is_hsi(pdev)) {
/* SW strategy for HSI fifo management can be changed here */
hsi_fifo_mapping(hsi_ctrl, HSI_FIFO_MAPPING_DEFAULT);
}
}
static void hsi_set_ports_default(struct hsi_dev *hsi_ctrl,
struct platform_device *pd)
{
struct hsi_port_ctx *cfg;
struct hsi_platform_data *pdata = dev_get_platdata(hsi_ctrl->dev);
struct platform_device *pdev = to_platform_device(hsi_ctrl->dev);
unsigned int port = 0;
void __iomem *base = hsi_ctrl->base;
for (port = 1; port <= pdata->num_ports; port++) {
cfg = &pdata->ctx->pctx[port - 1];
/* HST */
hsi_outl(cfg->hst.mode | cfg->hst.flow |
HSI_HST_MODE_WAKE_CTRL_SW, base,
HSI_HST_MODE_REG(port));
if (!hsi_driver_device_is_hsi(pdev))
hsi_outl(cfg->hst.frame_size, base,
HSI_HST_FRAMESIZE_REG(port));
hsi_outl(cfg->hst.divisor, base, HSI_HST_DIVISOR_REG(port));
hsi_outl(cfg->hst.channels, base, HSI_HST_CHANNELS_REG(port));
hsi_outl(cfg->hst.arb_mode, base, HSI_HST_ARBMODE_REG(port));
/* HSR */
hsi_outl(cfg->hsr.mode | cfg->hsr.flow, base,
HSI_HSR_MODE_REG(port));
if (!hsi_driver_device_is_hsi(pdev))
hsi_outl(cfg->hsr.frame_size, base,
HSI_HSR_FRAMESIZE_REG(port));
hsi_outl(cfg->hsr.channels, base, HSI_HSR_CHANNELS_REG(port));
if (hsi_driver_device_is_hsi(pdev))
hsi_outl(cfg->hsr.divisor, base,
HSI_HSR_DIVISOR_REG(port));
hsi_outl(cfg->hsr.counters, base, HSI_HSR_COUNTERS_REG(port));
}
if (hsi_driver_device_is_hsi(pdev)) {
/* SW strategy for HSI fifo management can be changed here */
hsi_fifo_mapping(hsi_ctrl, hsi_ctrl->fifo_mapping_strategy);
hsi_outl(pdata->ctx->dll, base, HSI_HSR_DLL_REG);
}
}
static int __init hsi_probe(struct platform_device *pd)
{
struct hsi_platform_data *pdata = pd->dev.platform_data;
struct hsi_dev *hsi_ctrl;
u32 revision;
int err;
dev_dbg(&pd->dev, "The platform device probed is an %s\n",
hsi_driver_device_is_hsi(pd) ? "HSI" : "SSI");
if (!pdata) {
pr_err(LOG_NAME "No platform_data found on hsi device\n");
return -ENXIO;
}
hsi_ctrl = kzalloc(sizeof(*hsi_ctrl), GFP_KERNEL);
if (hsi_ctrl == NULL) {
dev_err(&pd->dev, "Could not allocate memory for"
" struct hsi_dev\n");
return -ENOMEM;
}
platform_set_drvdata(pd, hsi_ctrl);
err = hsi_controller_init(hsi_ctrl, pd);
if (err < 0) {
dev_err(&pd->dev, "Could not initialize hsi controller:"
" %d\n", err);
goto rollback1;
}
err = hsi_softreset(hsi_ctrl);
if (err < 0)
goto rollback2;
/* Set default PM settings */
hsi_outl((HSI_AUTOIDLE | HSI_SIDLEMODE_SMART | HSI_MIDLEMODE_SMART),
hsi_ctrl->base, HSI_SYS_SYSCONFIG_REG);
hsi_outl(HSI_CLK_AUTOGATING_ON, hsi_ctrl->base, HSI_GDD_GCR_REG);
/* Configure HSI ports */
set_hsi_ports_default(hsi_ctrl, pd);
/* Gather info from registers for the driver.(REVISION) */
revision = hsi_inl(hsi_ctrl->base, HSI_SYS_REVISION_REG);
if (hsi_driver_device_is_hsi(pd))
dev_info(hsi_ctrl->dev, "HSI Hardware REVISION 0x%x\n",
revision);
else
dev_info(hsi_ctrl->dev, "SSI Hardware REVISION %d.%d\n",
(revision & HSI_SSI_REV_MAJOR) >> 4,
(revision & HSI_SSI_REV_MINOR));
err = hsi_debug_add_ctrl(hsi_ctrl);
if (err < 0)
goto rollback2;
err = register_hsi_devices(hsi_ctrl);
if (err < 0)
goto rollback3;
return err;
rollback3:
hsi_debug_remove_ctrl(hsi_ctrl);
rollback2:
hsi_controller_exit(hsi_ctrl);
rollback1:
kfree(hsi_ctrl);
return err;
}
static void hsi_restore_ctx(struct platform_device *pdev)
{
struct hsi_platform_data *pdata = pdev->dev.platform_data;
void __iomem *base = OMAP2_IO_ADDRESS(pdev->resource[0].start);
struct port_ctx *p;
int port;
int loss_count;
loss_count = omap_pm_get_dev_context_loss_count(&pdev->dev);
if (loss_count == pdata->ctx.loss_count)
return;
hsi_outl(pdata->ctx.sysconfig, base + HSI_SYS_SYSCONFIG_REG);
hsi_outl(pdata->ctx.gdd_gcr, base + HSI_GDD_GCR_REG);
for (port = 1; port <= pdata->num_ports; port++) {
p = &pdata->ctx.pctx[port - 1];
hsi_outl(p->sys_mpu_enable[0], base +
HSI_SYS_MPU_ENABLE_REG(port, 0));
hsi_outl(p->sys_mpu_enable[1], base +
HSI_SYS_MPU_U_ENABLE_REG(port, 0));
hsi_outl(p->hst.frame_size, base +
HSI_HST_FRAMESIZE_REG(port));
hsi_outl(p->hst.divisor, base + HSI_HST_DIVISOR_REG(port));
hsi_outl(p->hst.channels, base + HSI_HST_CHANNELS_REG(port));
hsi_outl(p->hst.arb_mode, base + HSI_HST_ARBMODE_REG(port));
hsi_outl(p->hsr.frame_size, base +
HSI_HSR_FRAMESIZE_REG(port));
/* FIXME - check this register */
hsi_outl(p->hsr.timeout, base + HSI_HSR_COUNTERS_REG(port));
hsi_outl(p->hsr.channels, base + HSI_HSR_CHANNELS_REG(port));
}
}
/**
* hsi_driver_int_proc - check all channels / ports for interrupts events
* @hsi_ctrl - HSI controler data
* @status_offset: interrupt status register offset
* @enable_offset: interrupt enable regiser offset
* @start: interrupt index to start on
* @stop: interrupt index to stop on
*
* returns the bitmap of processed events
*
* This function calls the related processing functions and triggered events.
* Events are cleared after corresponding function has been called.
*/
static u32 hsi_driver_int_proc(struct hsi_port *pport,
unsigned long status_offset,
unsigned long enable_offset, unsigned int start,
unsigned int stop,
bool cawake_double_int)
{
struct hsi_dev *hsi_ctrl = pport->hsi_controller;
void __iomem *base = hsi_ctrl->base;
unsigned int port = pport->port_number;
unsigned int channel;
u32 status_reg;
u32 hsr_err_reg;
u32 channels_served = 0;
/* Get events status */
status_reg = hsi_inl(base, status_offset);
status_reg &= hsi_inl(base, enable_offset);
/* Check if we need to process an additional CAWAKE interrupt */
if (cawake_double_int)
status_reg |= HSI_CAWAKEDETECTED;
if (pport->cawake_off_event) {
dev_dbg(hsi_ctrl->dev, "CAWAKE detected from OFF mode.\n");
} else if (!status_reg) {
dev_dbg(hsi_ctrl->dev, "Channels [%d,%d] : no event, exit.\n",
start, stop);
return 0;
} else {
dev_dbg(hsi_ctrl->dev, "Channels [%d,%d] : Events 0x%08x\n",
start, stop, status_reg);
}
if (status_reg & HSI_BREAKDETECTED) {
dev_info(hsi_ctrl->dev, "Hardware BREAK on port %d\n", port);
spin_unlock(&hsi_ctrl->lock);
hsi_port_event_handler(pport, HSI_EVENT_BREAK_DETECTED, NULL);
spin_lock(&hsi_ctrl->lock);
channels_served |= HSI_BREAKDETECTED;
}
if (status_reg & HSI_ERROROCCURED) {
hsr_err_reg = hsi_inl(base, HSI_HSR_ERROR_REG(port));
if (hsr_err_reg & HSI_HSR_ERROR_SIG)
dev_err(hsi_ctrl->dev, "HSI ERROR Port %d: 0x%x: %s\n",
port, hsr_err_reg, "Signal Error");
if (hsr_err_reg & HSI_HSR_ERROR_FTE)
dev_err(hsi_ctrl->dev, "HSI ERROR Port %d: 0x%x: %s\n",
port, hsr_err_reg, "Frame Timeout Error");
if (hsr_err_reg & HSI_HSR_ERROR_TBE)
dev_err(hsi_ctrl->dev, "HSI ERROR Port %d: 0x%x: %s\n",
port, hsr_err_reg, "Tailing Bit Error");
if (hsr_err_reg & HSI_HSR_ERROR_RME)
dev_err(hsi_ctrl->dev, "HSI ERROR Port %d: 0x%x: %s\n",
port, hsr_err_reg, "RX Mapping Error");
if (hsr_err_reg & HSI_HSR_ERROR_TME)
dev_err(hsi_ctrl->dev, "HSI ERROR Port %d: 0x%x: %s\n",
port, hsr_err_reg, "TX Mapping Error");
/* Clear error event bit */
hsi_outl(hsr_err_reg, base, HSI_HSR_ERRORACK_REG(port));
if (hsr_err_reg) { /* ignore spurious errors */
spin_unlock(&hsi_ctrl->lock);
hsi_port_event_handler(pport, HSI_EVENT_ERROR, NULL);
spin_lock(&hsi_ctrl->lock);
} else
dev_dbg(hsi_ctrl->dev, "Spurious HSI error!\n");
channels_served |= HSI_ERROROCCURED;
}
for (channel = start; channel <= stop; channel++) {
if (status_reg & HSI_HST_DATAACCEPT(channel)) {
hsi_do_channel_tx(&pport->hsi_channel[channel]);
channels_served |= HSI_HST_DATAACCEPT(channel);
}
if (status_reg & HSI_HSR_DATAAVAILABLE(channel)) {
hsi_do_channel_rx(&pport->hsi_channel[channel]);
channels_served |= HSI_HSR_DATAAVAILABLE(channel);
}
if (status_reg & HSI_HSR_DATAOVERRUN(channel)) {
/*HSI_TODO : Data overrun handling*/
dev_err(hsi_ctrl->dev,
"Data overrun in real time mode !\n");
}
}
/* CAWAKE falling or rising edge detected */
if ((status_reg & HSI_CAWAKEDETECTED) || pport->cawake_off_event) {
if (hsi_do_cawake_process(pport) == -EAGAIN)
goto proc_done;
channels_served |= HSI_CAWAKEDETECTED;
pport->cawake_off_event = false;
}
proc_done:
/* Reset status bits */
hsi_outl(channels_served, base, status_offset);
return channels_served;
}
