/// @brief HSPI read using FIFO
/// @param[in] *data: receive buffer
/// @param[in] count: number of bytes to read
/// @return void
void hspi_RX(uint8_t *data, int count)
{
int bytes;
while(count > 0)
{
// we will never have zero - we already checked
bytes = count;
if(bytes > HSPI_FIFO_SIZE)
bytes = HSPI_FIFO_SIZE;
// discard TX data
hspi_config(CONFIG_FOR_RX_TX);
// Writes are ignored, so we set data to 0xff
memset(data, 0xff, bytes);
hspi_writeFIFO(data, bytes);
hspi_startSend();
hspi_waitReady();
// read result
hspi_readFIFO(data, bytes);
data += bytes;
count -= bytes;
}
}
/// @brief HSPI Configuration for tranasmit and receive
/// @param[in] configState: CONFIG_FOR_RX_TX or CONFIG_FOR_RX
/// @return void
static void hspi_config(int configState)
{
uint32_t valueOfRegisters = 0;
hspi_waitReady();
if (configState == CONFIG_FOR_TX)
{
valueOfRegisters |= SPI_FLASH_DOUT;
//clear bit 2 see example IoT_Demo
valueOfRegisters &= \
~(BIT2 | SPI_FLASH_USR_ADDR | SPI_FLASH_USR_DUMMY | \
SPI_FLASH_USR_DIN | SPI_USR_COMMAND | SPI_DOUTDIN);
}
else if (configState == CONFIG_FOR_RX_TX)
{
valueOfRegisters |= SPI_FLASH_DOUT | SPI_DOUTDIN | SPI_CK_I_EDGE;
//clear bit 2 see example IoT_Demo
valueOfRegisters &= \
~(BIT2 | SPI_FLASH_USR_ADDR | SPI_FLASH_USR_DUMMY | \
SPI_FLASH_USR_DIN | SPI_USR_COMMAND);
}
else
{
return; // Error
}
WRITE_PERI_REG(SPI_FLASH_USER(HSPI), valueOfRegisters);
}
/// @brief Obtain SPI bus for TFT display, assert chip select
/// return: void
void tft_spi_begin()
{
hspi_waitReady();
hspi_init(tft_clock, 0);
hspi_cs_enable(TFT_CS_PIN);
//TFT_CS_ACTIVE;
}
/// @brief Transmit and read 8 bit data array
/// @param[in] *data: data buffer to send
/// @param[in] bytes: data buffer size
/// @param[in] command: 1 = command, 0 = data
/// return: void
void tft_spi_TXRX(uint8_t * data, int bytes, uint8_t command)
{
hspi_waitReady();
if(command)
TFT_COMMAND;
else
TFT_DATA;
hspi_TXRX(data,bytes);
}
void esp_yield()
{
// FIXME DEBUG
hspi_waitReady();
if (cont_can_yield(&g_cont))
{
cont_yield(&g_cont);
}
}
void hspi_TXRX(uint8_t *data, int count)
{
int bytes;
while(count > 0)
{
// we will never have zero - we already checked
bytes = count;
if(bytes > HSPI_FIFO_SIZE)
bytes = HSPI_FIFO_SIZE;
hspi_config(CONFIG_FOR_RX_TX); // Does hspi_waitReady(); first
hspi_writeFIFO(data, bytes);
hspi_startSend();
hspi_waitReady();
hspi_readFIFO(data, bytes);
data += bytes;
count -= bytes;
}
}
void loop_wrapper()
{
extern void loop(void);
extern void web_task();
if(!setup_done)
{
setup();
setup_done = true;
}
// FIXME DEBUG
REG_SET_BIT(0x3ff00014, BIT(0));
hspi_waitReady();
#ifdef WEBSERVER
web_task();
#endif
// USER TASK
loop();
esp_schedule();
}
/// @brief Release SPI bus from TFT display, deassert chip select
/// return: void
void tft_spi_end()
{
hspi_waitReady();
hspi_cs_disable(TFT_CS_PIN);
//TFT_CS_DEACTIVE;
}
