/*******************************************************************************
* gprtGetPortCtr
*
* DESCRIPTION:
* This routine gets the port rx/tx counters.
*
* INPUTS:
* port - the logical port number.
*
* OUTPUTS:
* ctr - the counters value.
*
* RETURNS:
* GT_OK - on success
* GT_FAIL - on error
*
* COMMENTS:
*
*
* GalTis:
*
*******************************************************************************/
GT_STATUS gprtGetPortCtr
(
IN GT_QD_DEV *dev,
IN GT_LPORT port,
OUT GT_PORT_STAT *ctr
)
{
GT_U16 count; /* counters current value */
GT_U8 hwPort; /* physical port number */
DBG_INFO(("gprtGetPortCtr Called.\n"));
if (IS_IN_DEV_GROUP(dev,DEV_88E6093_FAMILY))
{
DBG_INFO(("GT_NOT_SUPPORTED\n"));
return GT_NOT_SUPPORTED;
}
if(ctr == NULL)
{
DBG_INFO(("Failed.\n"));
return GT_BAD_PARAM;
}
/* translate logical port to physical port */
hwPort = GT_LPORT_2_PORT(port);
/* get rx counter value */
if(hwReadPortReg(dev,hwPort, QD_REG_RX_COUNTER, &count) != GT_OK)
{
DBG_INFO(("Failed (Read Rx).\n"));
return GT_FAIL;
}
ctr->rxCtr = count;
/* get tx counter value */
if(hwReadPortReg(dev,hwPort, QD_REG_TX_COUNTER, &count) != GT_OK)
{
DBG_INFO(("Failed (Read Tx).\n"));
return GT_FAIL;
}
ctr->txCtr = count;
if (IS_IN_DEV_GROUP(dev,DEV_ENHANCED_FE_SWITCH))
{
/* get dropped counter value */
if(hwReadPortReg(dev,hwPort, QD_REG_DROPPED_COUNTER, &count) != GT_OK)
{
DBG_INFO(("Failed (Read Tx).\n"));
return GT_FAIL;
}
ctr->dropped = count;
}
else
ctr->dropped = 0;
DBG_INFO(("OK.\n"));
return GT_OK;
}
/*******************************************************************************
* gprtGetPortQueueCtr
*
* DESCRIPTION:
* This routine gets the port queue counters.
*
* INPUTS:
* port - the logical port number.
*
* OUTPUTS:
* ctr - the counters value.
*
* RETURNS:
* GT_OK - on success
* GT_FAIL - on error
*
* COMMENTS:
*
*
* GalTis:
*
*******************************************************************************/
GT_STATUS gprtGetPortQueueCtr
(
IN GT_QD_DEV *dev,
IN GT_LPORT port,
OUT GT_PORT_Q_STAT *ctr
)
{
GT_U16 count; /* counters current value */
GT_U8 hwPort; /* physical port number */
DBG_INFO(("gprtGetPortQueueCtr Called.\n"));
if(ctr == NULL)
{
DBG_INFO(("Failed.\n"));
return GT_BAD_PARAM;
}
/* translate logical port to physical port */
hwPort = GT_LPORT_2_PORT(port);
/* get queue counter value */
if(hwReadPortReg(dev,hwPort, QD_REG_Q_COUNTER, &count) != GT_OK)
{
DBG_INFO(("Failed (Read Rx).\n"));
return GT_FAIL;
}
/* the fist 5 bits(4:0) are OutQ_Size */
ctr->OutQ_Size = count & 0x1F;
/* the Rsv_Size are bits 15:8 */
ctr->Rsv_Size = count >> 8;
DBG_INFO(("OK.\n"));
return GT_OK;
}
/*******************************************************************************
* gprtGetPortCtr2
*
* DESCRIPTION:
* This routine gets the port InDiscards, InFiltered, and OutFiltered counters.
*
* INPUTS:
* port - the logical port number.
*
* OUTPUTS:
* ctr - the counters value.
*
* RETURNS:
* GT_OK - on success
* GT_FAIL - on error
*
* COMMENTS:
*
*
* GalTis:
*
*******************************************************************************/
GT_STATUS gprtGetPortCtr2
(
IN GT_QD_DEV *dev,
IN GT_LPORT port,
OUT GT_PORT_STAT2 *ctr
)
{
#ifndef GT_RMGMT_ACCESS
GT_U16 count; /* counters current value */
#endif
GT_U8 hwPort; /* physical port number */
DBG_INFO(("gprtGetPortCtr2 Called.\n"));
if (!IS_IN_DEV_GROUP(dev,DEV_88E6093_FAMILY))
{
DBG_INFO(("GT_NOT_SUPPORTED\n"));
return GT_NOT_SUPPORTED;
}
if(ctr == NULL)
{
DBG_INFO(("Failed.\n"));
return GT_BAD_PARAM;
}
/* translate logical port to physical port */
hwPort = GT_LPORT_2_PORT(port);
#ifdef GT_RMGMT_ACCESS
{
HW_DEV_REG_ACCESS regAccess;
regAccess.entries = 4;
regAccess.rw_reg_list[0].cmd = HW_REG_READ;
regAccess.rw_reg_list[0].addr = CALC_SMI_DEV_ADDR(dev, hwPort, PORT_ACCESS);
regAccess.rw_reg_list[0].reg = QD_REG_INDISCARD_LO_COUNTER;
regAccess.rw_reg_list[0].data = 0;
regAccess.rw_reg_list[1].cmd = HW_REG_READ;
regAccess.rw_reg_list[1].addr = CALC_SMI_DEV_ADDR(dev, hwPort, PORT_ACCESS);
regAccess.rw_reg_list[1].reg = QD_REG_INDISCARD_HI_COUNTER;
regAccess.rw_reg_list[1].data = 0;
regAccess.rw_reg_list[2].cmd = HW_REG_READ;
regAccess.rw_reg_list[2].addr = CALC_SMI_DEV_ADDR(dev, hwPort, PORT_ACCESS);
regAccess.rw_reg_list[2].reg = QD_REG_INFILTERED_COUNTER;
regAccess.rw_reg_list[2].data = 0;
regAccess.rw_reg_list[3].cmd = HW_REG_READ;
regAccess.rw_reg_list[3].addr = CALC_SMI_DEV_ADDR(dev, hwPort, PORT_ACCESS);
regAccess.rw_reg_list[3].reg = QD_REG_OUTFILTERED_COUNTER;
regAccess.rw_reg_list[3].data = 0;
if(hwAccessMultiRegs(dev, ®Access) != GT_OK)
{
return GT_FAIL;
}
ctr->inDiscardLo = regAccess.rw_reg_list[0].data;
ctr->inDiscardHi = regAccess.rw_reg_list[1].data;
ctr->inFiltered = regAccess.rw_reg_list[2].data;
ctr->outFiltered = regAccess.rw_reg_list[3].data;
}
#else
/* get InDiscard Low counter value */
if(hwReadPortReg(dev,hwPort, QD_REG_INDISCARD_LO_COUNTER, &count) != GT_OK)
{
DBG_INFO(("Failed (Read inDiscardLo).\n"));
return GT_FAIL;
}
ctr->inDiscardLo = count;
/* get InDiscard High counter value */
if(hwReadPortReg(dev,hwPort, QD_REG_INDISCARD_HI_COUNTER, &count) != GT_OK)
{
DBG_INFO(("Failed (Read inDiscardHi).\n"));
return GT_FAIL;
}
ctr->inDiscardHi = count;
/* get InFiltered counter value */
if(hwReadPortReg(dev,hwPort, QD_REG_INFILTERED_COUNTER, &count) != GT_OK)
{
DBG_INFO(("Failed (Read inFiltered).\n"));
return GT_FAIL;
}
ctr->inFiltered = count;
/* get OutFiltered counter value */
if(hwReadPortReg(dev,hwPort, QD_REG_OUTFILTERED_COUNTER, &count) != GT_OK)
{
DBG_INFO(("Failed (Read outFiltered).\n"));
return GT_FAIL;
}
ctr->outFiltered = count;
#endif
DBG_INFO(("OK.\n"));
return GT_OK;
}
GT_STATUS qdInit(void)
{
GT_STATUS status = GT_OK;
unsigned int i;
status = qdStart();
if (GT_OK != status)
{
gtOsPrintf("qdStart is failed: status = 0x%x\n", status);
return status;
}
#ifdef DB_6093_88E6218
/* start 88E6090 device, assumes SMI Address 0x11 and CPU Port 10 */
if(loadDev(qd_ext, SMI_MULTI_ADDR_MODE, 0x11, 10) == NULL)
{
gtOsPrintf("Failed to start External Device. Please check the SMI Address 0x11!\n");
}
/* allow larger than 1522 bytes of frame (header + marvell tag) */
gsysSetMaxFrameSize(qd_dev,GT_FALSE);
#endif
for (i=0; i<qd_dev->numOfPorts; i++)
{
/* default port prio to three */
gcosSetPortDefaultTc(qd_dev, i, 3);
/* disable IP TOS Prio */
gqosIpPrioMapEn(qd_dev, i, GT_FALSE);
/* disable QOS Prio */
gqosUserPrioMapEn(qd_dev, i, GT_FALSE);
/* Force flow control for all ports */
gprtSetForceFc(qd_dev, i, GT_FALSE);
}
/* Enable port #6 */
status = gstpSetPortState(qd_dev, 6, GT_PORT_FORWARDING);
if((status = gprtClearAllCtr(qd_dev)) != GT_OK)
{
return status;
}
for (i=0; i<GT_CPU_SWITCH_PORT; i++)
{
gprtSetMcRateLimit(qd_dev, i, GT_MC_100_PERCENT_RL);
}
#ifdef QD_DEBUG
for (i=0; i<qd_dev->numOfPorts; i++)
{
short sdata;
hwReadPortReg(qd_dev, i, 0x4, &sdata);
gtOsPrintf("Control reg for port[%d] is: %x\n",i,sdata);
hwReadPortReg(qd_dev, i, 0x0, &sdata);
gtOsPrintf("Status reg for port[%d] is: %x\n",i,sdata);
}
qdStatus();
#endif /* QD_DEBUG */
gtOsPrintf("QD initiated\n");
return status;
}
/*******************************************************************************
* gpcsSetRGMIITimingDelay
*
* DESCRIPTION:
* RGMII receive/transmit Timing Control. This api adds delay to RXCLK for
* IND inputs and GTXCLK for OUTD outputs when port is in RGMII mode.
* Change to this bit are disruptive to normal operation. Hence any changes
* to this register must be done only while the port's link is down.
*
* INPUTS:
* port - the logical port number.
* rxmode - GT_FALSE for default setup, GT_TRUE for adding delay to rxclk
* txmode - GT_FALSE for default setup, GT_TRUE for adding delay to txclk
*
* OUTPUTS:
* None
*
* RETURNS:
* GT_OK - on success
* GT_FAIL - on error
* GT_NOT_SUPPORTED - if current device does not support this feature.
*
* COMMENTS:
*
*******************************************************************************/
GT_STATUS gpcsSetRGMIITimingDelay
(
IN GT_QD_DEV *dev,
IN GT_LPORT port,
IN GT_BOOL rxmode,
IN GT_BOOL txmode
)
{
GT_U16 data;
GT_STATUS retVal; /* Functions return value. */
GT_U8 hwPort; /* the physical port number */
DBG_INFO(("gpcsSetRGMIITimingDelay Called.\n"));
if (!IS_IN_DEV_GROUP(dev,DEV_RGMII_TIMING))
{
DBG_INFO(("GT_NOT_SUPPORTED\n"));
return GT_NOT_SUPPORTED;
}
/* translate LPORT to hardware port */
hwPort = GT_LPORT_2_PORT(port);
if (hwPort < (dev->maxPorts - 2))
{
DBG_INFO(("GT_NOT_SUPPORTED\n"));
return GT_NOT_SUPPORTED;
}
if(((dev->devName==DEV_88E6165)||(dev->devName==DEV_88E6161))&&
((hwPort==4)||((hwPort==5)&&(dev->revision==2)))) /* 88E6123 revision A2 */
{
if(hwWritePortReg(dev,4,0x1A,0x81E7) != GT_OK)
{
DBG_INFO(("Failed.\n"));
return GT_FAIL;
}
if(hwReadPortReg(dev,5,0x1A,&data) != GT_OK)
{
DBG_INFO(("Failed.\n"));
return GT_FAIL;
}
if((hwPort==5)&&(dev->revision==2)) /* 88E6123 revision A2 */
{
data &= 0xfff9;
data |= (rxmode) ? 0x2 : 0;
data |= (txmode) ? 0x1: 0;
}
else
{
data &= 0xffe7;
data |= (rxmode) ? 0x10 : 0;
data |= (txmode) ? 0x8: 0;
}
if(hwWritePortReg(dev,5,0x1A, data) != GT_OK)
{
DBG_INFO(("Failed.\n"));
return GT_FAIL;
}
if(hwWritePortReg(dev,4,0x1A,0xC1E7) != GT_OK)
{
DBG_INFO(("Failed.\n"));
return GT_FAIL;
}
}
else
{
data = (rxmode) ? 2 : 0;
data |= (txmode) ? 1 : 0;
/* Set the register bit(s). */
retVal = hwSetPortRegField(dev,hwPort, QD_REG_PCS_CONTROL,14,2,data);
if(retVal != GT_OK)
{
DBG_INFO(("Failed.\n"));
}
else
{
DBG_INFO(("OK.\n"));
}
}
/* return */
return retVal;
}
