static unsigned bfin_jtag_io_read_buffer (struct hw *me, void *dest, int space, address_word addr, unsigned nr_bytes) { struct bfin_jtag *jtag = hw_data (me); bu32 mmr_off; bu32 value; bu32 *valuep; mmr_off = addr - jtag->base; valuep = (void *)((unsigned long)jtag + mmr_base() + mmr_off); HW_TRACE_READ (); switch (mmr_off) { case mmr_offset(dbgstat): case mmr_offset(dspid): value = *valuep; break; default: while (1) /* Core MMRs -> exception -> doesn't return. */ dv_bfin_mmr_invalid (me, addr, nr_bytes, false); break; } dv_store_4 (dest, value); return nr_bytes; }
static unsigned bfin_wdog_io_read_buffer (struct hw *me, void *dest, int space, address_word addr, unsigned nr_bytes) { struct bfin_wdog *wdog = hw_data (me); bu32 mmr_off; bu16 *value16p; bu32 *value32p; void *valuep; mmr_off = addr - wdog->base; valuep = (void *)((unsigned long)wdog + mmr_base() + mmr_off); value16p = valuep; value32p = valuep; HW_TRACE_READ (); switch (mmr_off) { case mmr_offset(ctl): dv_bfin_mmr_require_16 (me, addr, nr_bytes, false); dv_store_2 (dest, *value16p); break; case mmr_offset(cnt): case mmr_offset(stat): dv_store_4 (dest, *value32p); break; } return nr_bytes; }
static void bfin_gpio_port_event (struct hw *me, int my_port, struct hw *source, int source_port, int level) { struct bfin_gpio *port = hw_data (me); bu32 bit = (1 << my_port); /* Normalize the level value. A simulated device can send any value it likes to us, but in reality we only care about 0 and 1. This lets us assume only those two values below. */ level = !!level; HW_TRACE ((me, "pin %i set to %i", my_port, level)); /* Only screw with state if this pin is set as an input, and the input is actually enabled, and it isn't in peripheral mode. */ if ((port->dir & bit) || !(port->inen & bit) || !(port->fer & bit)) { HW_TRACE ((me, "ignoring level due to DIR=%i INEN=%i FER=%i", !!(port->dir & bit), !!(port->inen & bit), !!(port->fer & bit))); return; } hw_port_event (me, my_port, level); }
static unsigned bfin_ppi_io_read_buffer (struct hw *me, void *dest, int space, address_word addr, unsigned nr_bytes) { struct bfin_ppi *ppi = hw_data (me); bu32 mmr_off; bu16 *valuep; mmr_off = addr - ppi->base; valuep = (void *)((unsigned long)ppi + mmr_base() + mmr_off); HW_TRACE_READ (); dv_bfin_mmr_require_16 (me, addr, nr_bytes, false); switch (mmr_off) { case mmr_offset(control): case mmr_offset(count): case mmr_offset(delay): case mmr_offset(frame): case mmr_offset(status): dv_store_2 (dest, *valuep); break; default: dv_bfin_mmr_invalid (me, addr, nr_bytes, false); break; } return nr_bytes; }
/* All reads to the flash address space come here. Using the state machine, we figure out what to return -- actual data stored in the flash, the CFI query structure, some status info, or something else ? Any requests that we can't handle are passed to the command set- specific read function. */ static unsigned cfi_io_read_buffer (struct hw *me, void *dest, int space, address_word addr, unsigned nr_bytes) { struct cfi *cfi = hw_data (me); unsigned char *sdest = dest; unsigned offset, shifted_offset; offset = addr & (cfi->dev_size - 1); shifted_offset = cfi_unshift_addr (cfi, offset); /* XXX: Is this OK to enforce ? */ #if 0 if (cfi->state != CFI_STATE_READ && cfi->width != nr_bytes) { HW_TRACE ((me, "read 0x%08lx length %u does not match flash width %u", (unsigned long) addr, nr_bytes, cfi->width)); return nr_bytes; } #endif HW_TRACE ((me, "%s read 0x%08lx length %u", state_names[cfi->state], (unsigned long) addr, nr_bytes)); switch (cfi->state) { case CFI_STATE_READ: memcpy (dest, cfi->data + offset, nr_bytes); break; case CFI_STATE_CFI_QUERY: if (shifted_offset >= CFI_ADDR_CFI_QUERY_RESULT && shifted_offset < CFI_ADDR_CFI_QUERY_RESULT + sizeof (cfi->query) + (cfi->query.num_erase_regions * 4)) { unsigned char *qry; shifted_offset -= CFI_ADDR_CFI_QUERY_RESULT; if (shifted_offset >= sizeof (cfi->query)) { qry = cfi->erase_region_info; shifted_offset -= sizeof (cfi->query); } else qry = (void *) &cfi->query; sdest[0] = qry[shifted_offset]; memset (sdest + 1, 0, nr_bytes - 1); break; } default: if (!cfi->cmdset->read (me, cfi, dest, offset, shifted_offset, nr_bytes)) HW_TRACE ((me, "unhandled state %s", state_names[cfi->state])); break; } return nr_bytes; }
static unsigned bfin_jtag_io_write_buffer (struct hw *me, const void *source, int space, address_word addr, unsigned nr_bytes) { struct bfin_jtag *jtag = hw_data (me); bu32 mmr_off; bu32 value; bu32 *valuep; value = dv_load_4 (source); mmr_off = addr - jtag->base; valuep = (void *)((unsigned long)jtag + mmr_base() + mmr_off); HW_TRACE_WRITE (); switch (mmr_off) { case mmr_offset(dbgstat): dv_w1c_4 (valuep, value, 0xc); break; case mmr_offset(dspid): /* Discard writes to these. */ break; default: dv_bfin_mmr_invalid (me, addr, nr_bytes, true); break; } return nr_bytes; }
static unsigned mn103int_io_read_buffer (struct hw *me, void *dest, int space, unsigned_word base, unsigned nr_bytes) { struct mn103int *controller = hw_data (me); unsigned8 *buf = dest; unsigned byte; /* HW_TRACE ((me, "read 0x%08lx %d", (long) base, (int) nr_bytes)); */ for (byte = 0; byte < nr_bytes; byte++) { unsigned_word address = base + byte; unsigned_word offset; switch (decode_addr (me, controller, address, &offset)) { case ICR_BLOCK: buf[byte] = read_icr (me, controller, offset); break; case IAGR_BLOCK: buf[byte] = read_iagr (me, controller, offset); break; case EXTMD_BLOCK: buf[byte] = read_extmd (me, controller, offset); break; default: hw_abort (me, "bad switch"); } } return nr_bytes; }
static unsigned bfin_ctimer_io_read_buffer (struct hw *me, void *dest, int space, address_word addr, unsigned nr_bytes) { struct bfin_ctimer *ctimer = hw_data (me); bu32 mmr_off; bu32 *valuep; mmr_off = addr - ctimer->base; valuep = (void *)((unsigned long)ctimer + mmr_base() + mmr_off); HW_TRACE_READ (); switch (mmr_off) { case mmr_offset(tcount): /* Since we're optimizing events here, we need to calculate the new tcount value. */ if (bfin_ctimer_enabled (ctimer)) bfin_ctimer_update_count (me, ctimer); break; } dv_store_4 (dest, *valuep); return nr_bytes; }
static void do_counter6_event (struct hw *me, void *data) { struct mn103tim *timers = hw_data(me); long timer_nr = (long) data; int next_timer; /* Check if counting is still enabled. */ if ( (timers->reg[timer_nr].mode & count_mask) != 0 ) { /* Generate an interrupt for the timer underflow (TIMERn_UFLOW). */ hw_port_event (me, timer_nr, 1); /* Schedule next timeout. */ timers->timer[timer_nr].start = hw_event_queue_time(me); /* FIX: Check if div_ratio has changed and if it's now 0. */ timers->timer[timer_nr].event = hw_event_queue_schedule (me, timers->timer[timer_nr].div_ratio, do_counter6_event, (void *)timer_nr); } else { timers->timer[timer_nr].event = NULL; } }
static void bfin_cec_port_event (struct hw *me, int my_port, struct hw *source, int source_port, int level) { struct bfin_cec *cec = hw_data (me); _cec_raise (cec->cpu, cec, my_port); }
static unsigned mn103int_io_write_buffer (struct hw *me, const void *source, int space, unsigned_word base, unsigned nr_bytes) { struct mn103int *controller = hw_data (me); const unsigned8 *buf = source; unsigned byte; /* HW_TRACE ((me, "write 0x%08lx %d", (long) base, (int) nr_bytes)); */ for (byte = 0; byte < nr_bytes; byte++) { unsigned_word address = base + byte; unsigned_word offset; switch (decode_addr (me, controller, address, &offset)) { case ICR_BLOCK: write_icr (me, controller, offset, buf[byte]); break; case IAGR_BLOCK: /* not allowed */ break; case EXTMD_BLOCK: write_extmd (me, controller, offset, buf[byte]); break; default: hw_abort (me, "bad switch"); } } return nr_bytes; }
static void m68hc11sio_info (struct hw *me) { SIM_DESC sd; uint16 base = 0; sim_cpu *cpu; struct m68hc11sio *controller; uint8 val; long clock_cycle; sd = hw_system (me); cpu = STATE_CPU (sd, 0); controller = hw_data (me); sim_io_printf (sd, "M68HC11 SIO:\n"); base = cpu_get_io_base (cpu); val = cpu->ios[M6811_BAUD]; print_io_byte (sd, "BAUD ", baud_desc, val, base + M6811_BAUD); sim_io_printf (sd, " (%ld baud)\n", (cpu->cpu_frequency / 4) / controller->baud_cycle); val = cpu->ios[M6811_SCCR1]; print_io_byte (sd, "SCCR1", sccr1_desc, val, base + M6811_SCCR1); sim_io_printf (sd, " (%d bits) (%dN1)\n", controller->data_length, controller->data_length - 2); val = cpu->ios[M6811_SCCR2]; print_io_byte (sd, "SCCR2", sccr2_desc, val, base + M6811_SCCR2); sim_io_printf (sd, "\n"); val = cpu->ios[M6811_SCSR]; print_io_byte (sd, "SCSR ", scsr_desc, val, base + M6811_SCSR); sim_io_printf (sd, "\n"); clock_cycle = controller->data_length * controller->baud_cycle; if (controller->tx_poll_event) { signed64 t; int n; t = hw_event_remain_time (me, controller->tx_poll_event); n = (clock_cycle - t) / controller->baud_cycle; n = controller->data_length - n; sim_io_printf (sd, " Transmit finished in %s (%d bit%s)\n", cycle_to_string (cpu, t, PRINT_TIME | PRINT_CYCLE), n, (n > 1 ? "s" : "")); } if (controller->rx_poll_event) { signed64 t; t = hw_event_remain_time (me, controller->rx_poll_event); sim_io_printf (sd, " Receive finished in %s\n", cycle_to_string (cpu, t, PRINT_TIME | PRINT_CYCLE)); } }
static void tx3904sio_port_event (struct hw *me, int my_port, struct hw *source, int source_port, int level) { struct tx3904sio *controller = hw_data (me); switch (my_port) { case RESET_PORT: { HW_TRACE ((me, "reset")); tx3904sio_fifo_reset(me, & controller->rx_fifo); tx3904sio_fifo_reset(me, & controller->tx_fifo); controller->slsr = controller->sdicr = controller->sdisr = controller->sfcr = controller->sbgr = 0; controller->slcr = 0x40000000; /* set TWUB */ controller->sbgr = 0x03ff0000; /* set BCLK=3, BRD=FF */ /* Don't interfere with I/O poller. */ break; } default: hw_abort (me, "Event on unknown port %d", my_port); break; } }
static unsigned bfin_ebiu_ddrc_io_read_buffer (struct hw *me, void *dest, int space, address_word addr, unsigned nr_bytes) { struct bfin_ebiu_ddrc *ddrc = hw_data (me); bu32 mmr_off; bu32 *value32p; bu16 *value16p; void *valuep; mmr_off = addr - ddrc->base; valuep = (void *)((unsigned long)ddrc + mmr_base() + mmr_off); value16p = valuep; value32p = valuep; HW_TRACE_READ (); switch (mmr_off) { case mmr_offset(errmst): case mmr_offset(rstctl): dv_bfin_mmr_require_16 (me, addr, nr_bytes, false); dv_store_2 (dest, *value16p); break; default: dv_bfin_mmr_require_32 (me, addr, nr_bytes, false); dv_store_4 (dest, *value32p); break; } return nr_bytes; }
unsigned bfin_uart_read_buffer (struct hw *me, unsigned char *buffer, unsigned nr_bytes) { SIM_DESC sd = hw_system (me); struct bfin_uart *uart = hw_data (me); int status = dv_sockser_status (sd); unsigned i = 0; if (status & DV_SOCKSER_DISCONNECTED) { int ret; while (uart->saved_count > 0 && i < nr_bytes) { buffer[i++] = uart->saved_byte; --uart->saved_count; } ret = sim_io_poll_read (sd, 0/*STDIN*/, (char *) buffer, nr_bytes - i); if (ret > 0) i += ret; } else buffer[i++] = dv_sockser_read (sd); return i; }
static unsigned bfin_cec_io_write_buffer (struct hw *me, const void *source, int space, address_word addr, unsigned nr_bytes) { struct bfin_cec *cec = hw_data (me); bu32 mmr_off; bu32 value; value = dv_load_4 (source); mmr_off = addr - cec->base; HW_TRACE_WRITE (); switch (mmr_off) { case mmr_offset(evt_override): cec->evt_override = value; break; case mmr_offset(imask): _cec_imask_write (cec, value); bfin_cec_check_pending (me, cec); break; case mmr_offset(ipend): /* Read-only register. */ break; case mmr_offset(ilat): dv_w1c_4 (&cec->ilat, value, 0xffee); break; case mmr_offset(iprio): cec->iprio = (value & IVG_UNMASKABLE_B); break; } return nr_bytes; }
static unsigned bfin_eppi_io_write_buffer (struct hw *me, const void *source, int space, address_word addr, unsigned nr_bytes) { struct bfin_eppi *eppi = hw_data (me); bu32 mmr_off; bu32 value; bu16 *value16p; bu32 *value32p; void *valuep; if (nr_bytes == 4) value = dv_load_4 (source); else value = dv_load_2 (source); mmr_off = addr - eppi->base; valuep = (void *)((unsigned long)eppi + mmr_base() + mmr_off); value16p = valuep; value32p = valuep; HW_TRACE_WRITE (); switch (mmr_off) { case mmr_offset(status): dv_bfin_mmr_require_16 (me, addr, nr_bytes, true); dv_w1c_2 (value16p, value, 0x1ff); break; case mmr_offset(hcount): case mmr_offset(hdelay): case mmr_offset(vcount): case mmr_offset(vdelay): case mmr_offset(frame): case mmr_offset(line): case mmr_offset(clkdiv): dv_bfin_mmr_require_16 (me, addr, nr_bytes, true); *value16p = value; break; case mmr_offset(control): *value32p = value; bfin_eppi_gui_setup (eppi); break; case mmr_offset(fs1w_hbl): case mmr_offset(fs1p_avpl): case mmr_offset(fsw2_lvb): case mmr_offset(fs2p_lavf): case mmr_offset(clip): case mmr_offset(err): dv_bfin_mmr_require_32 (me, addr, nr_bytes, true); *value32p = value; break; default: dv_bfin_mmr_invalid (me, addr, nr_bytes, true); break; } return nr_bytes; }
static unsigned bfin_uart_io_write_buffer (struct hw *me, const void *source, int space, address_word addr, unsigned nr_bytes) { struct bfin_uart *uart = hw_data (me); bu32 mmr_off; bu32 value; bu16 *valuep; /* Invalid access mode is higher priority than missing register. */ if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, true)) return 0; value = dv_load_2 (source); mmr_off = addr - uart->base; valuep = (void *)((unsigned long)uart + mmr_base() + mmr_off); HW_TRACE_WRITE (); /* XXX: All MMRs are "8bit" ... what happens to high 8bits ? */ switch (mmr_off) { case mmr_offset(thr): uart->thr = bfin_uart_write_byte (me, value, uart->mcr); if (uart->ier & ETBEI) hw_port_event (me, DV_PORT_TX, 1); break; case mmr_offset(ier_set): uart->ier |= value; break; case mmr_offset(ier_clear): dv_w1c_2 (&uart->ier, value, -1); break; case mmr_offset(lsr): dv_w1c_2 (valuep, value, TFI | BI | FE | PE | OE); break; case mmr_offset(rbr): /* XXX: Writes are ignored ? */ break; case mmr_offset(msr): dv_w1c_2 (valuep, value, SCTS); break; case mmr_offset(dll): case mmr_offset(dlh): case mmr_offset(gctl): case mmr_offset(lcr): case mmr_offset(mcr): case mmr_offset(scr): *valuep = value; break; default: dv_bfin_mmr_invalid (me, addr, nr_bytes, true); return 0; } return nr_bytes; }
void m68hc11sio_tx_poll (struct hw *me, void *data) { SIM_DESC sd; struct m68hc11sio *controller; sim_cpu *cpu; controller = hw_data (me); sd = hw_system (me); cpu = STATE_CPU (sd, 0); cpu->ios[M6811_SCSR] |= M6811_TDRE; cpu->ios[M6811_SCSR] |= M6811_TC; /* Transmitter is enabled and we have something to send. */ if ((cpu->ios[M6811_SCCR2] & M6811_TE) && controller->tx_has_char) { cpu->ios[M6811_SCSR] &= ~M6811_TDRE; cpu->ios[M6811_SCSR] &= ~M6811_TC; controller->tx_has_char = 0; switch (controller->backend) { case sio_tcp: dv_sockser_write (sd, controller->tx_char); break; case sio_stdio: sim_io_write_stdout (sd, &controller->tx_char, 1); sim_io_flush_stdout (sd); break; default: break; } } if (controller->tx_poll_event) { hw_event_queue_deschedule (me, controller->tx_poll_event); controller->tx_poll_event = 0; } if ((cpu->ios[M6811_SCCR2] & M6811_TE) && ((cpu->ios[M6811_SCSR] & M6811_TC) == 0)) { unsigned long clock_cycle; /* Compute CPU clock cycles to wait for the next character. */ clock_cycle = controller->data_length * controller->baud_cycle; controller->tx_poll_event = hw_event_queue_schedule (me, clock_cycle, m68hc11sio_tx_poll, NULL); } interrupts_update_pending (&cpu->cpu_interrupts); }
void tx3904sio_poll(struct hw* me, void* ignored) { struct tx3904sio* controller = hw_data (me); tx3904sio_tickle (me); hw_event_queue_deschedule (me, controller->poll_event); controller->poll_event = hw_event_queue_schedule (me, 1000, tx3904sio_poll, NULL); }
static unsigned bfin_uart_io_write_buffer (struct hw *me, const void *source, int space, address_word addr, unsigned nr_bytes) { struct bfin_uart *uart = hw_data (me); bu32 mmr_off; bu32 value; bu16 *valuep; value = dv_load_2 (source); mmr_off = addr - uart->base; valuep = (void *)((unsigned long)uart + mmr_base() + mmr_off); HW_TRACE_WRITE (); dv_bfin_mmr_require_16 (me, addr, nr_bytes, true); /* XXX: All MMRs are "8bit" ... what happens to high 8bits ? */ switch (mmr_off) { case mmr_offset(dll): if (uart->lcr & DLAB) uart->dll = value; else { uart->thr = bfin_uart_write_byte (me, value, uart->mcr); if (uart->ier & ETBEI) hw_port_event (me, DV_PORT_TX, 1); } break; case mmr_offset(dlh): if (uart->lcr & DLAB) uart->dlh = value; else { uart->ier = value; bfin_uart_reschedule (me); } break; case mmr_offset(iir): case mmr_offset(lsr): /* XXX: Writes are ignored ? */ break; case mmr_offset(lcr): case mmr_offset(mcr): case mmr_offset(scr): case mmr_offset(gctl): *valuep = value; break; default: dv_bfin_mmr_invalid (me, addr, nr_bytes, true); break; } return nr_bytes; }
static void write_hw_pal (struct hw *me, char val) { hw_pal_device *hw_pal = (hw_pal_device *) hw_data (me); sim_io_write_stdout (hw_system (me), &val, 1); hw_pal->output.buffer = val; hw_pal->output.status = 1; }
static unsigned hw_pal_io_write_buffer (struct hw *me, const void *source, int space, unsigned_word addr, unsigned nr_bytes) { hw_pal_device *hw_pal = (hw_pal_device*) hw_data (me); unsigned_1 *byte = (unsigned_1 *) source; switch (addr & hw_pal_address_mask) { case hw_pal_reset_register: hw_halt (me, sim_exited, byte[0]); break; case hw_pal_int_register: hw_port_event (me, INT_PORT + byte[0], /*port*/ (nr_bytes > 1 ? byte[1] : 0)); /* val */ break; case hw_pal_read_fifo: hw_pal->input.buffer = byte[0]; HW_TRACE ((me, "write - input-fifo %d\n", byte[0])); break; case hw_pal_read_status: hw_pal->input.status = byte[0]; HW_TRACE ((me, "write - input-status %d\n", byte[0])); break; case hw_pal_write_fifo: write_hw_pal (me, byte[0]); HW_TRACE ((me, "write - output-fifo %d\n", byte[0])); break; case hw_pal_write_status: hw_pal->output.status = byte[0]; HW_TRACE ((me, "write - output-status %d\n", byte[0])); break; case hw_pal_countdown: do_counter_write (me, hw_pal, "countdown", &hw_pal->countdown, source, nr_bytes); break; case hw_pal_timer: do_counter_write (me, hw_pal, "timer", &hw_pal->timer, source, nr_bytes); break; } return nr_bytes; }
static unsigned mn103iop_io_write_buffer (struct hw *me, const void *source, int space, unsigned_word base, unsigned nr_bytes) { struct mn103iop *io_port = hw_data (me); enum io_port_register_types io_port_reg; HW_TRACE ((me, "write 0x%08lx %d", (long) base, (int) nr_bytes)); io_port_reg = decode_addr (me, io_port, base); switch (io_port_reg) { /* Port output registers */ case P0OUT: case P1OUT: case P2OUT: case P3OUT: write_output_reg(me, io_port, io_port_reg-P0OUT, source, nr_bytes); break; /* Port output mode registers */ case P0MD: case P1MD: case P2MD: case P3MD: write_output_mode_reg(me, io_port, io_port_reg-P0MD, source, nr_bytes); break; /* Port control registers */ case P0DIR: case P1DIR: case P2DIR: case P3DIR: write_control_reg(me, io_port, io_port_reg-P0DIR, source, nr_bytes); break; /* Port pin registers */ case P0IN: case P1IN: case P2IN: hw_abort(me, "Cannot write to pin register."); break; case P2SS: case P4SS: write_dedicated_control_reg(me, io_port, io_port_reg, source, nr_bytes); break; default: hw_abort(me, "invalid address"); } return nr_bytes; }
/* Clean up any state when this device is removed (e.g. when shutting down, or when reloading via gdb). */ static void cfi_delete_callback (struct hw *me) { #ifdef HAVE_MMAP struct cfi *cfi = hw_data (me); if (cfi->mmap) munmap (cfi->mmap, cfi->dev_size); #endif }
static int mn103int_ioctl(struct hw *me, hw_ioctl_request request, va_list ap) { struct mn103int *controller = (struct mn103int *)hw_data(me); controller->group[0].request = EXTRACT_ID(4); mn103int_port_event(me, 2 /* nmi_port(syserr) */, NULL, 0, 0); return 0; }
static hw_instance * hw_pal_create_instance (struct hw *me, const char *path, const char *args) { return hw_create_instance_from (me, NULL, hw_data (me), path, args, &hw_pal_instance_callbacks); }
static unsigned bfin_wdog_io_write_buffer (struct hw *me, const void *source, int space, address_word addr, unsigned nr_bytes) { struct bfin_wdog *wdog = hw_data (me); bu32 mmr_off; bu32 value; bu16 *value16p; bu32 *value32p; void *valuep; /* Invalid access mode is higher priority than missing register. */ if (!dv_bfin_mmr_require_16_32 (me, addr, nr_bytes, true)) return 0; if (nr_bytes == 4) value = dv_load_4 (source); else value = dv_load_2 (source); mmr_off = addr - wdog->base; valuep = (void *)((unsigned long)wdog + mmr_base() + mmr_off); value16p = valuep; value32p = valuep; HW_TRACE_WRITE (); switch (mmr_off) { case mmr_offset(ctl): dv_w1c_2_partial (value16p, value, WDRO); /* XXX: Should enable an event here to handle timeouts. */ break; case mmr_offset(cnt): /* Writes are discarded when enabeld. */ if (!bfin_wdog_enabled (wdog)) { *value32p = value; /* Writes to CNT preloads the STAT. */ wdog->stat = wdog->cnt; } break; case mmr_offset(stat): /* When enabled, writes to STAT reload the counter. */ if (bfin_wdog_enabled (wdog)) wdog->stat = wdog->cnt; /* XXX: When disabled, are writes just ignored ? */ break; } return nr_bytes; }
static void hw_pal_attach_address (struct hw *me, int level, int space, address_word addr, address_word nr_bytes, struct hw *client) { hw_pal_device *pal = (hw_pal_device*) hw_data (me); pal->disk = client; }
static unsigned m68hc11eepr_io_read_buffer (struct hw *me, void *dest, int space, unsigned_word base, unsigned nr_bytes) { SIM_DESC sd; struct m68hc11eepr *controller; sim_cpu *cpu; HW_TRACE ((me, "read 0x%08lx %d", (long) base, (int) nr_bytes)); sd = hw_system (me); controller = hw_data (me); cpu = STATE_CPU (sd, 0); if (space == io_map) { unsigned cnt = 0; while (nr_bytes != 0) { switch (base) { case M6811_PPROG: case M6811_CONFIG: *((uint8*) dest) = cpu->ios[base]; break; default: hw_abort (me, "reading wrong register 0x%04x", base); } dest = (uint8*) (dest) + 1; base++; nr_bytes--; cnt++; } return cnt; } /* In theory, we can't read the EEPROM when it's being programmed. */ if ((cpu->ios[M6811_PPROG] & M6811_EELAT) != 0 && cpu_is_running (cpu)) { sim_memory_error (cpu, SIM_SIGBUS, base, "EEprom not configured for reading"); } base = base - controller->base_address; memcpy (dest, &controller->eeprom[base], nr_bytes); return nr_bytes; }