static void dormant_restore_addnl_reg(void)
{
int i;
u32 val1,val2;
/* Allow write access to the CCU registers */
writel(0xA5A501,
(KONA_PROC_CLK_VA + KPROC_CLK_MGR_REG_WR_ACCESS_OFFSET));
for ( i=0; i<ARRAY_SIZE(addnl_save_reg_list); i++ )
{
/* Restore the saved data */
writel( addnl_save_reg_list[i][1], addnl_save_reg_list[i][0]);
if (addnl_save_reg_list[i][0] == (KONA_PROC_CLK_VA + KPROC_CLK_MGR_REG_TGTMASK_DBG1_OFFSET))
{
/* Finished restoring all the A9 CCU registers
* lock the state machine so writing the GO bit would not cause
* issues with the state machine
*/
writel(readl(KONA_PROC_CLK_VA + KPROC_CLK_MGR_REG_LVM_EN_OFFSET) |
KPROC_CLK_MGR_REG_LVM_EN_POLICY_CONFIG_EN_MASK,
KONA_PROC_CLK_VA + KPROC_CLK_MGR_REG_LVM_EN_OFFSET);
/* Wait for HW confirmation of policy lock */
while ( readl(KONA_PROC_CLK_VA + KPROC_CLK_MGR_REG_LVM_EN_OFFSET) &
KPROC_CLK_MGR_REG_LVM_EN_POLICY_CONFIG_EN_MASK );
/* Write the go bit to trigger the frequency change
*/
writel(KPROC_CLK_MGR_REG_POLICY_CTL_GO_AC_MASK | KPROC_CLK_MGR_REG_POLICY_CTL_GO_MASK,
KONA_PROC_CLK_VA + KPROC_CLK_MGR_REG_POLICY_CTL_OFFSET);
}
}
/* Wait until the new frequency takes effect */
do
{
val1 = readl(KONA_PROC_CLK_VA + KPROC_CLK_MGR_REG_POLICY_CTL_OFFSET) &
KPROC_CLK_MGR_REG_POLICY_CTL_GO_MASK;
val2 = readl(KONA_PROC_CLK_VA + KPROC_CLK_MGR_REG_POLICY_CTL_OFFSET) &
KPROC_CLK_MGR_REG_POLICY_CTL_GO_MASK;
} while ( val1 | val2 ) ;
/* Finished restoring all the registers, enable the L2 CACHE now*/
/* HWRHEA-1199 - New frequency should now be in effect enable
* L2 cache now
*/
#ifdef CONFIG_ROM_SEC_DISPATCHER
hw_sec_pub_dispatcher(SEC_API_ENABLE_L2_CACHE,
SEC_FLAGS);
#endif
}
static void dormant_save_addnl_reg(void)
{
int i;
for ( i=0; i < ARRAY_SIZE(addnl_save_reg_list); i++ )
{
addnl_save_reg_list[i][1] = readl(addnl_save_reg_list[i][0]);
}
/* Finished saving all additional registers. Disable L2 before entering dormant */
/* HWRHEA-1199 - Disable L2 before entering dormant so that when
* we exit dormant, we have L2 disabled not causing an issue dur to
* running at 156 MHZ
*/
#ifdef CONFIG_ROM_SEC_DISPATCHER
hw_sec_pub_dispatcher(SEC_API_DISABLE_L2_CACHE,
SEC_FLAGS);
#endif
}
int rhea_l2x0_prefetch(bool enable)
{
int op, count;
op = enable ? SEC_API_ENABLE_L2_PREFETCH : SEC_API_DISABLE_L2_PREFETCH;
spin_lock(&l2x0_prefetch_enable_spinlock);
if (enable)
count = l2x0_prefetch_enable_count++;
else
count = --l2x0_prefetch_enable_count;
#ifdef CONFIG_ROM_SEC_DISPATCHER
if (!count)
hw_sec_pub_dispatcher(op, SEC_FLAGS);
#endif
spin_unlock(&l2x0_prefetch_enable_spinlock);
pr_info("l2x0 prefetch enable: %d %d\n", enable, count);
return 0;
}