static int ccu_div_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct ccu_div *cd = hw_to_ccu_div(hw); unsigned long flags; unsigned long val; u32 reg; parent_rate = ccu_mux_helper_apply_prediv(&cd->common, &cd->mux, -1, parent_rate); if (cd->common.features & CCU_FEATURE_FIXED_POSTDIV) rate *= cd->fixed_post_div; val = divider_get_val(rate, parent_rate, cd->div.table, cd->div.width, cd->div.flags); spin_lock_irqsave(cd->common.lock, flags); reg = readl(cd->common.base + cd->common.reg); reg &= ~GENMASK(cd->div.width + cd->div.shift - 1, cd->div.shift); writel(reg | (val << cd->div.shift), cd->common.base + cd->common.reg); spin_unlock_irqrestore(cd->common.lock, flags); return 0; }
static int ccu_div_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct ccu_div *cd = hw_to_ccu_div(hw); unsigned long flags; unsigned long val; u32 reg; ccu_mux_helper_adjust_parent_for_prediv(&cd->common, &cd->mux, -1, &parent_rate); val = divider_get_val(rate, parent_rate, cd->div.table, cd->div.width, cd->div.flags); spin_lock_irqsave(cd->common.lock, flags); reg = readl(cd->common.base + cd->common.reg); reg &= ~GENMASK(cd->div.width + cd->div.shift - 1, cd->div.shift); writel(reg | (val << cd->div.shift), cd->common.base + cd->common.reg); spin_unlock_irqrestore(cd->common.lock, flags); return 0; }
static int ccu_div_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) { struct ccu_div *cd = hw_to_ccu_div(hw); return ccu_mux_helper_determine_rate(&cd->common, &cd->mux, req, ccu_div_round_rate, cd); }
static unsigned long ccu_div_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct ccu_div *cd = hw_to_ccu_div(hw); unsigned long val; u32 reg; reg = readl(cd->common.base + cd->common.reg); val = reg >> cd->div.shift; val &= (1 << cd->div.width) - 1; ccu_mux_helper_adjust_parent_for_prediv(&cd->common, &cd->mux, -1, &parent_rate); return divider_recalc_rate(hw, parent_rate, val, cd->div.table, cd->div.flags); }
static unsigned long ccu_div_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct ccu_div *cd = hw_to_ccu_div(hw); unsigned long val; u32 reg; reg = readl(cd->common.base + cd->common.reg); val = reg >> cd->div.shift; val &= (1 << cd->div.width) - 1; parent_rate = ccu_mux_helper_apply_prediv(&cd->common, &cd->mux, -1, parent_rate); val = divider_recalc_rate(hw, parent_rate, val, cd->div.table, cd->div.flags, cd->div.width); if (cd->common.features & CCU_FEATURE_FIXED_POSTDIV) val /= cd->fixed_post_div; return val; }
static int ccu_div_is_enabled(struct clk_hw *hw) { struct ccu_div *cd = hw_to_ccu_div(hw); return ccu_gate_helper_is_enabled(&cd->common, cd->enable); }
static void ccu_div_disable(struct clk_hw *hw) { struct ccu_div *cd = hw_to_ccu_div(hw); return ccu_gate_helper_disable(&cd->common, cd->enable); }
static int ccu_div_set_parent(struct clk_hw *hw, u8 index) { struct ccu_div *cd = hw_to_ccu_div(hw); return ccu_mux_helper_set_parent(&cd->common, &cd->mux, index); }
static u8 ccu_div_get_parent(struct clk_hw *hw) { struct ccu_div *cd = hw_to_ccu_div(hw); return ccu_mux_helper_get_parent(&cd->common, &cd->mux); }