void hw_watchdog_init(void) { struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR; u16 val = readw(&wdog->wcr); u16 timeout; /* * The timer watchdog can be set between * 0.5 and 128 Seconds. If not defined * in configuration file, sets 128 Seconds */ #ifndef CONFIG_WATCHDOG_TIMEOUT_MSECS #define CONFIG_WATCHDOG_TIMEOUT_MSECS 128000 #endif timeout = (CONFIG_WATCHDOG_TIMEOUT_MSECS / 500) - 1; val |= WCR_WDZST; val &= ~(0xFF << 8); val &= ~WCR_WDE; val &= ~WCR_WDT; val |= SET_WCR_WT(timeout); writew(val, &wdog->wcr); val |= WCR_WDE; writew(val, &wdog->wcr); hw_watchdog_reset(); }
void hw_watchdog_init(void) { gpio_request(WATCHDOG_TRIGGER_GPIO, "watchdog_trigger"); gpio_direction_output(WATCHDOG_TRIGGER_GPIO, hw_watchdog_trigger_level); hw_watchdog_reset(); hw_watchdog_init_done = 1; }
void reset_cpu(ulong addr) { struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR; writew(WCR_WDE, &wdog->wcr); hw_watchdog_reset(); while (1) { /* * spin for .5 seconds before reset */ } }
void enet_timer_isr(void) { static long enet_ticks = 0; enet_ticks++; /* Toggle Watchdog every 100ms */ if ((enet_ticks % 100) == 0) hw_watchdog_reset(); /* Toggle Run LED every 500ms */ if ((enet_ticks % 500) == 0) enet_toggle_run_led(); }
void hw_watchdog_init(void) { struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR; u16 timeout; /* * The timer watchdog can be set between * 0.5 and 128 Seconds. If not defined * in configuration file, sets 128 Seconds */ #ifndef CONFIG_WATCHDOG_TIMEOUT_MSECS #define CONFIG_WATCHDOG_TIMEOUT_MSECS 128000 #endif timeout = (CONFIG_WATCHDOG_TIMEOUT_MSECS / 500) - 1; writew(WCR_WDZST | WCR_WDBG | WCR_WDE | WCR_WDT | WCR_SRS | SET_WCR_WT(timeout), &wdog->wcr); hw_watchdog_reset(); }
void hw_watchdog_enable(void) { unsigned int reg; unsigned int mr; /* Check if disabled */ mr = at91_sys_read(AT91_WDT_MR); if (mr & AT91_WDT_WDDIS) { printf("hw_watchdog_enable: sorry, wdt is disabled already\n"); return; } /* * All counting occurs at SLOW_CLOCK / 128 = 256 Hz * * Since WDV is a 12-bit counter, the maximum period is * 4096 / 256 = 16 seconds. */ reg = AT91_WDT_WDRSTEN /* causes watchdog reset */ //| AT91_WDT_WDRPROC /*causes processor reset only */ | AT91_WDT_WDDBGHLT /* disabled in debug mode */ | AT91_WDT_WDD /* restart at any time */ | (((WDT_HEARTBEAT * 256) -1) & AT91_WDT_WDV); /* timer value */ at91_sys_write(AT91_WDT_MR, reg); /* Check if watchdog could be programmed */ mr = at91_sys_read(AT91_WDT_MR); if (mr != reg) { printf("hw_watchdog_enable: Watchdog register already programmed.\n"); return; } hw_watchdog_reset(); printf("at91_wdt: enabled (heartbeat=%d sec)\n", WDT_HEARTBEAT); }
static void board_init_ddr(void) { struct emif_regs rut_ddr3_emif_reg_data = { .sdram_config = 0x61C04AB2, .sdram_tim1 = 0x0888A39B, .sdram_tim2 = 0x26337FDA, .sdram_tim3 = 0x501F830F, .emif_ddr_phy_ctlr_1 = 0x6, .zq_config = 0x50074BE4, .ref_ctrl = 0x93B, }; struct ddr_data rut_ddr3_data = { .datardsratio0 = 0x3b, .datawdsratio0 = 0x85, .datafwsratio0 = 0x100, .datawrsratio0 = 0xc1, }; struct cmd_control rut_ddr3_cmd_ctrl_data = { .cmd0csratio = 0x40, .cmd0iclkout = 1, .cmd1csratio = 0x40, .cmd1iclkout = 1, .cmd2csratio = 0x40, .cmd2iclkout = 1, }; config_ddr(DDR_PLL_FREQ, RUT_IOCTRL_VAL, &rut_ddr3_data, &rut_ddr3_cmd_ctrl_data, &rut_ddr3_emif_reg_data, 0); } static void spl_siemens_board_init(void) { return; } #endif /* if def CONFIG_SPL_BUILD */ #if defined(CONFIG_DRIVER_TI_CPSW) static void cpsw_control(int enabled) { /* VTP can be added here */ return; } static struct cpsw_slave_data cpsw_slaves[] = { { .slave_reg_ofs = 0x208, .sliver_reg_ofs = 0xd80, .phy_addr = 1, .phy_if = PHY_INTERFACE_MODE_RMII, }, { .slave_reg_ofs = 0x308, .sliver_reg_ofs = 0xdc0, .phy_addr = 0, .phy_if = PHY_INTERFACE_MODE_RMII, }, }; static struct cpsw_platform_data cpsw_data = { .mdio_base = CPSW_MDIO_BASE, .cpsw_base = CPSW_BASE, .mdio_div = 0xff, .channels = 8, .cpdma_reg_ofs = 0x800, .slaves = 1, .slave_data = cpsw_slaves, .ale_reg_ofs = 0xd00, .ale_entries = 1024, .host_port_reg_ofs = 0x108, .hw_stats_reg_ofs = 0x900, .bd_ram_ofs = 0x2000, .mac_control = (1 << 5), .control = cpsw_control, .host_port_num = 0, .version = CPSW_CTRL_VERSION_2, }; #if defined(CONFIG_DRIVER_TI_CPSW) || \ (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) int board_eth_init(bd_t *bis) { struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; int n = 0; int rv; #ifndef CONFIG_SPL_BUILD factoryset_setenv(); #endif /* Set rgmii mode and enable rmii clock to be sourced from chip */ writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel); rv = cpsw_register(&cpsw_data); if (rv < 0) printf("Error %d registering CPSW switch\n", rv); else n += rv; return n; } #endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */ #endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */ #if defined(CONFIG_HW_WATCHDOG) static bool hw_watchdog_init_done; static int hw_watchdog_trigger_level; void hw_watchdog_reset(void) { if (!hw_watchdog_init_done) return; hw_watchdog_trigger_level = hw_watchdog_trigger_level ? 0 : 1; gpio_set_value(WATCHDOG_TRIGGER_GPIO, hw_watchdog_trigger_level); } void hw_watchdog_init(void) { gpio_request(WATCHDOG_TRIGGER_GPIO, "watchdog_trigger"); gpio_direction_output(WATCHDOG_TRIGGER_GPIO, hw_watchdog_trigger_level); hw_watchdog_reset(); hw_watchdog_init_done = 1; } #endif /* defined(CONFIG_HW_WATCHDOG) */ #if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD) static struct da8xx_panel lcd_panels[] = { /* FORMIKE, 4.3", 480x800, KWH043MC17-F01 */ [0] = { .name = "KWH043MC17-F01", .width = 480, .height = 800, .hfp = 50, /* no spec, "don't care" values */ .hbp = 50, .hsw = 50, .vfp = 50, .vbp = 50, .vsw = 50, .pxl_clk = 35910000, /* tCYCD=20ns, max 50MHz, 60fps */ .invert_pxl_clk = 1, },
void hw_watchdog_init(void) { bfin_write_WDOG_CNT(5 * get_sclk()); /* 5 second timeout */ hw_watchdog_reset(); bfin_write_WDOG_CTL(0x0); }