static irqreturn_t i2s_irq_handler(int irq, void *dev_id) { struct dw_i2s_dev *dev = dev_id; bool irq_valid = false; u32 isr[4]; int i; for (i = 0; i < 4; i++) isr[i] = i2s_read_reg(dev->i2s_base, ISR(i)); i2s_clear_irqs(dev, SNDRV_PCM_STREAM_PLAYBACK); i2s_clear_irqs(dev, SNDRV_PCM_STREAM_CAPTURE); for (i = 0; i < 4; i++) { /* * Check if TX fifo is empty. If empty fill FIFO with samples * NOTE: Only two channels supported */ if ((isr[i] & ISR_TXFE) && (i == 0) && dev->use_pio) { dw_pcm_push_tx(dev); irq_valid = true; } /* * Data available. Retrieve samples from FIFO * NOTE: Only two channels supported */ if ((isr[i] & ISR_RXDA) && (i == 0) && dev->use_pio) { dw_pcm_pop_rx(dev); irq_valid = true; } /* Error Handling: TX */ if (isr[i] & ISR_TXFO) { dev_err(dev->dev, "TX overrun (ch_id=%d)\n", i); irq_valid = true; } /* Error Handling: TX */ if (isr[i] & ISR_RXFO) { dev_err(dev->dev, "RX overrun (ch_id=%d)\n", i); irq_valid = true; } } if (irq_valid) return IRQ_HANDLED; else return IRQ_NONE; }
static void i2s_stop(struct dw_i2s_dev *dev, struct snd_pcm_substream *substream) { u32 i = 0, irq; i2s_clear_irqs(dev, substream->stream); if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { i2s_write_reg(dev->i2s_base, ITER, 0); for (i = 0; i < 4; i++) { irq = i2s_read_reg(dev->i2s_base, IMR(i)); i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x30); } } else { i2s_write_reg(dev->i2s_base, IRER, 0); for (i = 0; i < 4; i++) { irq = i2s_read_reg(dev->i2s_base, IMR(i)); i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x03); } } if (!dev->active) { i2s_write_reg(dev->i2s_base, CER, 0); i2s_write_reg(dev->i2s_base, IER, 0); } }
static void i2s_stop(struct dw_i2s_dev *dev, struct snd_pcm_substream *substream) { i2s_clear_irqs(dev, substream->stream); if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) i2s_write_reg(dev->i2s_base, ITER, 0); else i2s_write_reg(dev->i2s_base, IRER, 0); i2s_disable_irqs(dev, substream->stream, 8); if (!dev->active) { i2s_write_reg(dev->i2s_base, CER, 0); i2s_write_reg(dev->i2s_base, IER, 0); } }