void genmult() { #ifdef INTERPRET_MULT gencallinterp((unsigned long)MULT, 0); #else int rs, rt; allocate_register_manually_w(EAX, (unsigned long *)&lo, 0); allocate_register_manually_w(EDX, (unsigned long *)&hi, 0); rs = allocate_register((unsigned long*)dst->f.r.rs); rt = allocate_register((unsigned long*)dst->f.r.rt); mov_reg32_reg32(EAX, rs); imul_reg32(rt); #endif }
void genmult(usf_state_t * state) { #ifdef INTERPRET_MULT gencallinterp(state, (unsigned int)state->current_instruction_table.MULT, 0); #else int rs, rt; allocate_register_manually_w(state, EAX, (unsigned int *)&state->lo, 0); allocate_register_manually_w(state, EDX, (unsigned int *)&state->hi, 0); rs = allocate_register(state, (unsigned int*)state->dst->f.r.rs); rt = allocate_register(state, (unsigned int*)state->dst->f.r.rt); mov_reg32_reg32(state, EAX, rs); imul_reg32(state, rt); #endif }
void genmult(void) { #ifdef INTERPRET_MULT gencallinterp((unsigned int)cached_interpreter_table.MULT, 0); #else int rs, rt; allocate_register_manually_w(EAX, (unsigned int *)r4300_mult_lo(), 0); allocate_register_manually_w(EDX, (unsigned int *)r4300_mult_hi(), 0); rs = allocate_register((unsigned int*)g_dev.r4300.recomp.dst->f.r.rs); rt = allocate_register((unsigned int*)g_dev.r4300.recomp.dst->f.r.rt); mov_reg32_reg32(EAX, rs); imul_reg32(rt); #endif }
void genmult(void) { #if defined(COUNT_INSTR) inc_m32abs(&instr_count[71]); #endif #ifdef INTERPRET_MULT gencallinterp((unsigned long long)MULT, 0); #else int rs, rt; allocate_register_32_manually_w(EAX, (unsigned int *)&lo); /* these must be done first so they are not assigned by allocate_register() */ allocate_register_32_manually_w(EDX, (unsigned int *)&hi); rs = allocate_register_32((unsigned int*)dst->f.r.rs); rt = allocate_register_32((unsigned int*)dst->f.r.rt); mov_reg32_reg32(EAX, rs); imul_reg32(rt); #endif }