static void imx6_add_video_clks(void __iomem *anab, void __iomem *cb)
{
clks[IMX6QDL_CLK_PLL5_POST_DIV] = imx_clk_divider_table("pll5_post_div", "pll5_video", anab + 0xa0, 19, 2, post_div_table);
clks[IMX6QDL_CLK_PLL5_VIDEO_DIV] = imx_clk_divider_table("pll5_video_div", "pll5_post_div", anab + 0x170, 30, 2, video_div_table);
clks[IMX6QDL_CLK_IPU1_SEL] = imx_clk_mux("ipu1_sel", cb + 0x3c, 9, 2, ipu_sels, ARRAY_SIZE(ipu_sels));
clks[IMX6QDL_CLK_IPU2_SEL] = imx_clk_mux("ipu2_sel", cb + 0x3c, 14, 2, ipu_sels, ARRAY_SIZE(ipu_sels));
clks[IMX6QDL_CLK_LDB_DI0_SEL] = imx_clk_mux_p("ldb_di0_sel", cb + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels));
clks[IMX6QDL_CLK_LDB_DI1_SEL] = imx_clk_mux_p("ldb_di1_sel", cb + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels));
clks[IMX6QDL_CLK_IPU1_DI0_PRE_SEL] = imx_clk_mux_p("ipu1_di0_pre_sel", cb + 0x34, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels));
clks[IMX6QDL_CLK_IPU1_DI1_PRE_SEL] = imx_clk_mux_p("ipu1_di1_pre_sel", cb + 0x34, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels));
clks[IMX6QDL_CLK_IPU2_DI0_PRE_SEL] = imx_clk_mux_p("ipu2_di0_pre_sel", cb + 0x38, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels));
clks[IMX6QDL_CLK_IPU2_DI1_PRE_SEL] = imx_clk_mux_p("ipu2_di1_pre_sel", cb + 0x38, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels));
clks[IMX6QDL_CLK_IPU1_DI0_SEL] = imx_clk_mux_p("ipu1_di0_sel", cb + 0x34, 0, 3, ipu1_di0_sels, ARRAY_SIZE(ipu1_di0_sels));
clks[IMX6QDL_CLK_IPU1_DI1_SEL] = imx_clk_mux_p("ipu1_di1_sel", cb + 0x34, 9, 3, ipu1_di1_sels, ARRAY_SIZE(ipu1_di1_sels));
clks[IMX6QDL_CLK_IPU2_DI0_SEL] = imx_clk_mux_p("ipu2_di0_sel", cb + 0x38, 0, 3, ipu2_di0_sels, ARRAY_SIZE(ipu2_di0_sels));
clks[IMX6QDL_CLK_IPU2_DI1_SEL] = imx_clk_mux_p("ipu2_di1_sel", cb + 0x38, 9, 3, ipu2_di1_sels, ARRAY_SIZE(ipu2_di1_sels));
clks[IMX6QDL_CLK_IPU1_PODF] = imx_clk_divider("ipu1_podf", "ipu1_sel", cb + 0x3c, 11, 3);
clks[IMX6QDL_CLK_IPU2_PODF] = imx_clk_divider("ipu2_podf", "ipu2_sel", cb + 0x3c, 16, 3);
clks[IMX6QDL_CLK_LDB_DI0_DIV_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
clks[IMX6QDL_CLK_LDB_DI0_PODF] = imx_clk_divider_np("ldb_di0_podf", "ldb_di0_div_3_5", cb + 0x20, 10, 1);
clks[IMX6QDL_CLK_LDB_DI1_DIV_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
clks[IMX6QDL_CLK_LDB_DI1_PODF] = imx_clk_divider_np("ldb_di1_podf", "ldb_di1_div_3_5", cb + 0x20, 11, 1);
clks[IMX6QDL_CLK_IPU1_DI0_PRE] = imx_clk_divider("ipu1_di0_pre", "ipu1_di0_pre_sel", cb + 0x34, 3, 3);
clks[IMX6QDL_CLK_IPU1_DI1_PRE] = imx_clk_divider("ipu1_di1_pre", "ipu1_di1_pre_sel", cb + 0x34, 12, 3);
clks[IMX6QDL_CLK_IPU2_DI0_PRE] = imx_clk_divider("ipu2_di0_pre", "ipu2_di0_pre_sel", cb + 0x38, 3, 3);
clks[IMX6QDL_CLK_IPU2_DI1_PRE] = imx_clk_divider("ipu2_di1_pre", "ipu2_di1_pre_sel", cb + 0x38, 12, 3);
clks[IMX6QDL_CLK_IPU1] = imx_clk_gate2("ipu1", "ipu1_podf", cb + 0x74, 0);
clks[IMX6QDL_CLK_IPU1_DI0] = imx_clk_gate2("ipu1_di0", "ipu1_di0_sel", cb + 0x74, 2);
clks[IMX6QDL_CLK_IPU1_DI1] = imx_clk_gate2("ipu1_di1", "ipu1_di1_sel", cb + 0x74, 4);
clks[IMX6QDL_CLK_IPU2] = imx_clk_gate2("ipu2", "ipu2_podf", cb + 0x74, 6);
clks[IMX6QDL_CLK_IPU2_DI0] = imx_clk_gate2("ipu2_di0", "ipu2_di0_sel", cb + 0x74, 8);
clks[IMX6QDL_CLK_LDB_DI0] = imx_clk_gate2("ldb_di0", "ldb_di0_podf", cb + 0x74, 12);
clks[IMX6QDL_CLK_LDB_DI1] = imx_clk_gate2("ldb_di1", "ldb_di1_podf", cb + 0x74, 14);
clks[IMX6QDL_CLK_IPU2_DI1] = imx_clk_gate2("ipu2_di1", "ipu2_di1_sel", cb + 0x74, 10);
clk_set_parent(clks[IMX6QDL_CLK_IPU1_DI0_SEL], clks[IMX6QDL_CLK_IPU1_DI0_PRE]);
clk_set_parent(clks[IMX6QDL_CLK_IPU1_DI1_SEL], clks[IMX6QDL_CLK_IPU1_DI1_PRE]);
clk_set_parent(clks[IMX6QDL_CLK_IPU2_DI0_SEL], clks[IMX6QDL_CLK_IPU2_DI0_PRE]);
clk_set_parent(clks[IMX6QDL_CLK_IPU2_DI1_SEL], clks[IMX6QDL_CLK_IPU2_DI1_PRE]);
clk_set_parent(clks[IMX6QDL_CLK_IPU1_DI0_PRE_SEL], clks[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
clk_set_parent(clks[IMX6QDL_CLK_IPU1_DI1_PRE_SEL], clks[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
clk_set_parent(clks[IMX6QDL_CLK_IPU2_DI0_PRE_SEL], clks[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
clk_set_parent(clks[IMX6QDL_CLK_IPU2_DI1_PRE_SEL], clks[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
if ((imx_silicon_revision() != IMX_CHIP_REV_1_0) ||
cpu_is_mx6dl()) {
clk_set_parent(clks[IMX6QDL_CLK_LDB_DI0_SEL], clks[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
clk_set_parent(clks[IMX6QDL_CLK_LDB_DI1_SEL], clks[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
}
}
static int f3s_devices_init(void)
{
uint32_t reg;
/* CS0: Nor Flash */
imx35_setup_weimcs(0, 0x0000cf03, 0x10000d03, 0x00720900);
reg = readl(MX35_CCM_BASE_ADDR + MX35_CCM_RCSR);
/* some fuses provide us vital information about connected hardware */
if (reg & 0x20000000)
nand_info.width = 2; /* 16 bit */
else
nand_info.width = 1; /* 8 bit */
/*
* This platform supports NOR and NAND
*/
imx35_add_nand(&nand_info);
add_cfi_flash_device(DEVICE_ID_DYNAMIC, MX35_CS0_BASE_ADDR, 64 * 1024 * 1024, 0);
switch ((reg >> 25) & 0x3) {
case 0x01: /* NAND is the source */
devfs_add_partition("nand0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self_raw");
dev_add_bb_dev("self_raw", "self0");
devfs_add_partition("nand0", 0x40000, 0x80000, DEVFS_PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
break;
case 0x00: /* NOR is the source */
devfs_add_partition("nor0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self0");
devfs_add_partition("nor0", 0x40000, 0x80000, DEVFS_PARTITION_FIXED, "env0");
protect_file("/dev/env0", 1);
break;
}
set_silicon_rev(imx_silicon_revision());
i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices));
imx35_add_i2c0(NULL);
imx35_add_fec(&fec_info);
add_generic_device("smc911x", DEVICE_ID_DYNAMIC, NULL, MX35_CS5_BASE_ADDR, MX35_CS5_SIZE,
IORESOURCE_MEM, NULL);
imx35_add_mmc0(NULL);
imx35_add_fb(&ipu_fb_data);
armlinux_set_bootparams((void *)0x80000100);
armlinux_set_architecture(MACH_TYPE_MX35_3DS);
return 0;
}
static int loco_devices_init(void)
{
imx53_iim_register_fec_ethaddr();
loco_fec_reset();
imx53_add_fec(&fec_info);
imx53_add_mmc0(&loco_sd1_data);
imx53_add_mmc2(&loco_sd3_data);
i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices));
imx53_add_i2c0(NULL);
if (IS_ENABLED(CONFIG_USB_EHCI))
loco_ehci_init();
set_silicon_rev(imx_silicon_revision());
armlinux_set_bootparams((void *)0x70000100);
armlinux_set_architecture(MACH_TYPE_MX53_LOCO);
imx53_bbu_internal_mmc_register_handler("mmc", "/dev/disk0",
BBU_HANDLER_FLAG_DEFAULT, dcd_entry, sizeof(dcd_entry), 0);
return 0;
}
static int efikamx_late_init(void)
{
int i;
if (!of_machine_is_compatible("genesi,imx51-sb"))
return 0;
defaultenv_append_directory(defaultenv_efikasb);
for (i = 0; i < ARRAY_SIZE(leds); i++)
led_gpio_register(&leds[i]);
led_set_trigger(LED_TRIGGER_HEARTBEAT, &leds[0].led);
writew(0x0, MX51_WDOG_BASE_ADDR + 0x8);
imx51_bbu_internal_mmc_register_handler("mmc", "/dev/mmc1",
BBU_HANDLER_FLAG_DEFAULT);
armlinux_set_architecture(2370);
armlinux_set_revision(0x5100 | imx_silicon_revision());
return 0;
}
static int loco_late_init(void)
{
struct mc13xxx *mc34708;
int rev;
if (!of_machine_is_compatible("fsl,imx53-qsb") &&
!of_machine_is_compatible("fsl,imx53-qsrb"))
return 0;
mc34708 = mc13xxx_get();
if (mc34708) {
unsigned int val;
int ret;
/* get the board revision from fuse */
rev = readl(MX53_IIM_BASE_ADDR + 0x878);
set_board_rev(rev);
printf("MCIMX53-START-R board 1.0 rev %c\n", (rev == 1) ? 'A' : 'B' );
barebox_set_hostname("loco-r");
armlinux_set_revision(loco_system_rev);
/* Set VDDGP to 1.25V for 1GHz on SW1 */
mc13xxx_reg_read(mc34708, MC13892_REG_SW_0, &val);
val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_250V_MC34708;
ret = mc13xxx_reg_write(mc34708, MC13892_REG_SW_0, val);
if (ret) {
printf("Writing to REG_SW_0 failed: %d\n", ret);
return ret;
}
/* Set VCC as 1.30V on SW2 */
mc13xxx_reg_read(mc34708, MC13892_REG_SW_1, &val);
val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_300V_MC34708;
ret = mc13xxx_reg_write(mc34708, MC13892_REG_SW_1, val);
if (ret) {
printf("Writing to REG_SW_1 failed: %d\n", ret);
return ret;
}
/* Set global reset timer to 4s */
mc13xxx_reg_read(mc34708, MC13892_REG_POWER_CTL2, &val);
val = (val & ~TIMER_MASK_MC34708) | TIMER_4S_MC34708;
ret = mc13xxx_reg_write(mc34708, MC13892_REG_POWER_CTL2, val);
if (ret) {
printf("Writing to REG_POWER_CTL2 failed: %d\n", ret);
return ret;
}
/* Set VUSBSEL and VUSBEN for USB PHY supply*/
mc13xxx_reg_read(mc34708, MC13892_REG_MODE_0, &val);
val |= (VUSBSEL_MC34708 | VUSBEN_MC34708);
ret = mc13xxx_reg_write(mc34708, MC13892_REG_MODE_0, val);
if (ret) {
printf("Writing to REG_MODE_0 failed: %d\n", ret);
return ret;
}
/* Set SWBST to 5V in auto mode */
val = SWBST_AUTO;
ret = mc13xxx_reg_write(mc34708, SWBST_CTRL, val);
if (ret) {
printf("Writing to SWBST_CTRL failed: %d\n", ret);
return ret;
}
} else {
/* so we have a DA9053 based board */
printf("MCIMX53-START board 1.0\n");
barebox_set_hostname("loco");
armlinux_set_revision(loco_system_rev);
}
/* USB PWR enable */
gpio_direction_output(MX53_LOCO_USB_PWREN, 0);
gpio_set_value(MX53_LOCO_USB_PWREN, 1);
loco_fec_reset();
set_silicon_rev(imx_silicon_revision());
armlinux_set_architecture(MACH_TYPE_MX53_LOCO);
imx53_bbu_internal_mmc_register_handler("mmc", "/dev/mmc0",
BBU_HANDLER_FLAG_DEFAULT);
return 0;
}
static int imx27_ccm_probe(struct device_d *dev)
{
void __iomem *base;
base = dev_request_mem_region(dev, 0);
writel(PCCR0_SDHC3_EN | PCCR0_SDHC2_EN | PCCR0_SDHC1_EN |
PCCR0_PWM_EN | PCCR0_KPP_EN | PCCR0_IIM_EN |
PCCR0_I2C2_EN | PCCR0_I2C1_EN | PCCR0_GPT6_EN | PCCR0_GPT5_EN |
PCCR0_GPT4_EN | PCCR0_GPT3_EN | PCCR0_GPT2_EN | PCCR0_GPT1_EN |
PCCR0_GPIO_EN | PCCR0_FEC_EN | PCCR0_CSPI3_EN | PCCR0_CSPI2_EN |
PCCR0_CSPI1_EN,
base + CCM_PCCR0);
writel(PCCR1_NFC_BAUDEN | PCCR1_PERCLK4_EN | PCCR1_PERCLK2_EN | PCCR1_PERCLK1_EN |
PCCR1_HCLK_USB | PCCR1_HCLK_FEC | PCCR1_HCLK_EMI | PCCR1_WDT_EN |
PCCR1_USB_EN | PCCR1_UART6_EN | PCCR1_UART5_EN | PCCR1_UART4_EN |
PCCR1_UART3_EN | PCCR1_UART2_EN | PCCR1_UART1_EN,
base + CCM_PCCR1);
clks[dummy] = clk_fixed("dummy", 0);
clks[ckih] = clk_fixed("ckih", 26000000);
clks[ckil] = clk_fixed("ckil", 32768);
clks[fpm] = imx_clk_fixed_factor("fpm", "ckil", 1024, 1);
clks[ckih_div1p5] = imx_clk_fixed_factor("ckih_div1p5", "ckih", 2, 3);
clks[mpll_osc_sel] = imx_clk_mux("mpll_osc_sel", base + CCM_CSCR, 4, 1,
mpll_osc_sel_clks,
ARRAY_SIZE(mpll_osc_sel_clks));
clks[mpll_sel] = imx_clk_mux("mpll_sel", base + CCM_CSCR, 16, 1, mpll_sel_clks,
ARRAY_SIZE(mpll_sel_clks));
clks[mpll] = imx_clk_pllv1("mpll", "mpll_sel", base + CCM_MPCTL0);
clks[spll] = imx_clk_pllv1("spll", "ckih", base + CCM_SPCTL0);
clks[mpll_main2] = imx_clk_fixed_factor("mpll_main2", "mpll", 2, 3);
if (imx_silicon_revision() >= IMX_CHIP_REV_2_0) {
clks[ahb] = imx_clk_divider("ahb", "mpll_main2", base + CCM_CSCR, 8, 2);
clks[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2);
} else {
clks[ahb] = imx_clk_divider("ahb", "mpll_main2", base + CCM_CSCR, 9, 4);
clks[ipg] = imx_clk_divider("ipg", "ahb", base + CCM_CSCR, 8, 1);
}
clks[nfc_div] = imx_clk_divider("nfc_div", "ahb", base + CCM_PCDR0, 6, 4);
clks[per1_div] = imx_clk_divider("per1_div", "mpll_main2", base + CCM_PCDR1, 0, 6);
clks[per2_div] = imx_clk_divider("per2_div", "mpll_main2", base + CCM_PCDR1, 8, 6);
clks[per3_div] = imx_clk_divider("per3_div", "mpll_main2", base + CCM_PCDR1, 16, 6);
clks[per4_div] = imx_clk_divider("per4_div", "mpll_main2", base + CCM_PCDR1, 24, 6);
clks[usb_div] = imx_clk_divider("usb_div", "spll", base + CCM_CSCR, 28, 3);
clks[cpu_sel] = imx_clk_mux("cpu_sel", base + CCM_CSCR, 15, 1, cpu_sel_clks,
ARRAY_SIZE(cpu_sel_clks));
clks[clko_sel] = imx_clk_mux("clko_sel", base + CCM_CCSR, 0, 5, clko_sel_clks,
ARRAY_SIZE(clko_sel_clks));
if (imx_silicon_revision() >= IMX_CHIP_REV_2_0)
clks[cpu_div] = imx_clk_divider("cpu_div", "cpu_sel", base + CCM_CSCR, 12, 2);
else
clks[cpu_div] = imx_clk_divider("cpu_div", "cpu_sel", base + CCM_CSCR, 13, 3);
clks[clko_div] = imx_clk_divider("clko_div", "clko_sel", base + CCM_PCDR0, 22, 3);
clks[per3_gate] = imx_clk_gate("per3_gate", "per3_div", base + CCM_PCCR1, 8);
clks[lcdc_ahb_gate] = imx_clk_gate("lcdc_ahb_gate", "ahb", base + CCM_PCCR1, 15);
clks[lcdc_ipg_gate] = imx_clk_gate("lcdc_ipg_gate", "ipg", base + CCM_PCCR0, 14);
clkdev_add_physbase(clks[per1_div], MX27_GPT1_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per1_div], MX27_GPT2_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per1_div], MX27_GPT3_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per1_div], MX27_GPT4_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per1_div], MX27_GPT5_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per1_div], MX27_GPT6_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per1_div], MX27_UART1_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per1_div], MX27_UART2_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per1_div], MX27_UART3_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per1_div], MX27_UART4_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per1_div], MX27_UART5_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per1_div], MX27_UART6_BASE_ADDR, NULL);
clkdev_add_physbase(clks[ipg], MX27_CSPI1_BASE_ADDR, NULL);
clkdev_add_physbase(clks[ipg], MX27_CSPI2_BASE_ADDR, NULL);
clkdev_add_physbase(clks[ipg], MX27_CSPI3_BASE_ADDR, NULL);
clkdev_add_physbase(clks[ipg], MX27_I2C1_BASE_ADDR, NULL);
clkdev_add_physbase(clks[ipg], MX27_I2C2_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per2_div], MX27_SDHC1_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per2_div], MX27_SDHC2_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per2_div], MX27_SDHC3_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per3_gate], MX27_LCDC_BASE_ADDR, "per");
clkdev_add_physbase(clks[lcdc_ahb_gate], MX27_LCDC_BASE_ADDR, "ahb");
clkdev_add_physbase(clks[lcdc_ipg_gate], MX27_LCDC_BASE_ADDR, "ipg");
clkdev_add_physbase(clks[ipg], MX27_FEC_BASE_ADDR, NULL);
return 0;
}
static void babbage_power_init(void)
{
struct mc13xxx *mc13xxx;
u32 val;
mc13xxx = mc13xxx_get();
if (!mc13xxx) {
printf("could not get PMIC\n");
return;
}
/* Write needed to Power Gate 2 register */
mc13xxx_reg_read(mc13xxx, MC13892_REG_POWER_MISC, &val);
val &= ~0x10000;
mc13xxx_reg_write(mc13xxx, MC13892_REG_POWER_MISC, val);
/* Write needed to update Charger 0 */
mc13xxx_reg_write(mc13xxx, MC13892_REG_CHARGE, 0x0023807F);
/* power up the system first */
mc13xxx_reg_write(mc13xxx, MC13892_REG_POWER_MISC, 0x00200000);
if (imx_silicon_revision() < IMX_CHIP_REV_3_0) {
/* Set core voltage to 1.1V */
mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_0, &val);
val &= ~0x1f;
val |= 0x14;
mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_0, val);
/* Setup VCC (SW2) to 1.25 */
mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_1, &val);
val &= ~0x1f;
val |= 0x1a;
mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_1, val);
/* Setup 1V2_DIG1 (SW3) to 1.25 */
mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_2, &val);
val &= ~0x1f;
val |= 0x1a;
mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_2, val);
} else {
/* Setup VCC (SW2) to 1.225 */
mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_1, &val);
val &= ~0x1f;
val |= 0x19;
mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_1, val);
/* Setup 1V2_DIG1 (SW3) to 1.2 */
mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_2, &val);
val &= ~0x1f;
val |= 0x18;
mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_2, val);
}
if (mc13xxx_revision(mc13xxx) < MC13892_REVISION_2_0) {
/* Set switchers in PWM mode for Atlas 2.0 and lower */
/* Setup the switcher mode for SW1 & SW2*/
mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_4, &val);
val &= ~0x3c0f;
val |= 0x1405;
mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_4, val);
/* Setup the switcher mode for SW3 & SW4 */
mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_5, &val);
val &= ~0xf0f;
val |= 0x505;
mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_5, val);
} else {
/* Set switchers in Auto in NORMAL mode & STANDBY mode for Atlas 2.0a */
/* Setup the switcher mode for SW1 & SW2*/
mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_4, &val);
val &= ~0x3c0f;
val |= 0x2008;
mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_4, val);
/* Setup the switcher mode for SW3 & SW4 */
mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_5, &val);
val &= ~0xf0f;
val |= 0x808;
mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_5, val);
}
/* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.5V */
mc13xxx_reg_read(mc13xxx, MC13892_REG_SETTING_0, &val);
val &= ~0x34030;
val |= 0x10020;
mc13xxx_reg_write(mc13xxx, MC13892_REG_SETTING_0, val);
/* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
mc13xxx_reg_read(mc13xxx, MC13892_REG_SETTING_1, &val);
val &= ~0x1FC;
val |= 0x1F4;
mc13xxx_reg_write(mc13xxx, MC13892_REG_SETTING_1, val);
/* Configure VGEN3 and VCAM regulators to use external PNP */
val = 0x208;
mc13xxx_reg_write(mc13xxx, MC13892_REG_MODE_1, val);
udelay(200);
#define GPIO_LAN8700_RESET (1 * 32 + 14)
/* Reset the ethernet controller over GPIO */
gpio_direction_output(GPIO_LAN8700_RESET, 0);
/* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
val = 0x49249;
mc13xxx_reg_write(mc13xxx, MC13892_REG_MODE_1, val);
udelay(200);
gpio_set_value(GPIO_LAN8700_RESET, 1);
mdelay(50);
}
static void babbage_power_init(void)
{
struct mc13892 *mc13892;
u32 val;
mc13892 = mc13892_get();
if (!mc13892) {
printf("could not get mc13892\n");
return;
}
/* Write needed to Power Gate 2 register */
mc13892_reg_read(mc13892, 34, &val);
val &= ~0x10000;
mc13892_reg_write(mc13892, 34, val);
/* Write needed to update Charger 0 */
mc13892_reg_write(mc13892, 48, 0x0023807F);
/* power up the system first */
mc13892_reg_write(mc13892, 34, 0x00200000);
if (imx_silicon_revision() < MX51_CHIP_REV_3_0) {
/* Set core voltage to 1.1V */
mc13892_reg_read(mc13892, 24, &val);
val &= ~0x1f;
val |= 0x14;
mc13892_reg_write(mc13892, 24, val);
/* Setup VCC (SW2) to 1.25 */
mc13892_reg_read(mc13892, 25, &val);
val &= ~0x1f;
val |= 0x1a;
mc13892_reg_write(mc13892, 25, val);
/* Setup 1V2_DIG1 (SW3) to 1.25 */
mc13892_reg_read(mc13892, 26, &val);
val &= ~0x1f;
val |= 0x1a;
mc13892_reg_write(mc13892, 26, val);
udelay(50);
/* Raise the core frequency to 800MHz */
writel(0x0, MX51_CCM_BASE_ADDR + MX51_CCM_CACRR);
} else {
/* Setup VCC (SW2) to 1.225 */
mc13892_reg_read(mc13892, 25, &val);
val &= ~0x1f;
val |= 0x19;
mc13892_reg_write(mc13892, 25, val);
/* Setup 1V2_DIG1 (SW3) to 1.2 */
mc13892_reg_read(mc13892, 26, &val);
val &= ~0x1f;
val |= 0x18;
mc13892_reg_write(mc13892, 26, val);
}
if (mc13892_get_revision(mc13892) < MC13892_REVISION_2_0) {
/* Set switchers in PWM mode for Atlas 2.0 and lower */
/* Setup the switcher mode for SW1 & SW2*/
mc13892_reg_read(mc13892, 28, &val);
val &= ~0x3c0f;
val |= 0x1405;
mc13892_reg_write(mc13892, 28, val);
/* Setup the switcher mode for SW3 & SW4 */
mc13892_reg_read(mc13892, 29, &val);
val &= ~0xf0f;
val |= 0x505;
mc13892_reg_write(mc13892, 29, val);
} else {
/* Set switchers in Auto in NORMAL mode & STANDBY mode for Atlas 2.0a */
/* Setup the switcher mode for SW1 & SW2*/
mc13892_reg_read(mc13892, 28, &val);
val &= ~0x3c0f;
val |= 0x2008;
mc13892_reg_write(mc13892, 28, val);
/* Setup the switcher mode for SW3 & SW4 */
mc13892_reg_read(mc13892, 29, &val);
val &= ~0xf0f;
val |= 0x808;
mc13892_reg_write(mc13892, 29, val);
}
/* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.5V */
mc13892_reg_read(mc13892, 30, &val);
val &= ~0x34030;
val |= 0x10020;
mc13892_reg_write(mc13892, 30, val);
/* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
mc13892_reg_read(mc13892, 31, &val);
val &= ~0x1FC;
val |= 0x1F4;
mc13892_reg_write(mc13892, 31, val);
/* Configure VGEN3 and VCAM regulators to use external PNP */
val = 0x208;
mc13892_reg_write(mc13892, 33, val);
udelay(200);
#define GPIO_LAN8700_RESET (1 * 32 + 14)
/* Reset the ethernet controller over GPIO */
gpio_direction_output(GPIO_LAN8700_RESET, 0);
/* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
val = 0x49249;
mc13892_reg_write(mc13892, 33, val);
udelay(500);
gpio_set_value(GPIO_LAN8700_RESET, 1);
}
static void babbage_power_init(struct mc13xxx *mc13xxx)
{
u32 val;
/* Write needed to Power Gate 2 register */
mc13xxx_reg_read(mc13xxx, MC13892_REG_POWER_MISC, &val);
val &= ~0x10000;
mc13xxx_reg_write(mc13xxx, MC13892_REG_POWER_MISC, val);
/* Write needed to update Charger 0 */
mc13xxx_reg_write(mc13xxx, MC13892_REG_CHARGE, 0x0023807F);
/* power up the system first */
mc13xxx_reg_write(mc13xxx, MC13892_REG_POWER_MISC, 0x00200000);
if (imx_silicon_revision() < IMX_CHIP_REV_3_0) {
/* Set core voltage to 1.1V */
mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_0, &val);
val &= ~0x1f;
val |= 0x14;
mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_0, val);
/* Setup VCC (SW2) to 1.25 */
mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_1, &val);
val &= ~0x1f;
val |= 0x1a;
mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_1, val);
/* Setup 1V2_DIG1 (SW3) to 1.25 */
mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_2, &val);
val &= ~0x1f;
val |= 0x1a;
mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_2, val);
} else {
/* Setup VCC (SW2) to 1.225 */
mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_1, &val);
val &= ~0x1f;
val |= 0x19;
mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_1, val);
/* Setup 1V2_DIG1 (SW3) to 1.2 */
mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_2, &val);
val &= ~0x1f;
val |= 0x18;
mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_2, val);
}
if (mc13xxx_revision(mc13xxx) < MC13892_REVISION_2_0) {
/* Set switchers in PWM mode for Atlas 2.0 and lower */
/* Setup the switcher mode for SW1 & SW2*/
mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_4, &val);
val &= ~0x3c0f;
val |= 0x1405;
mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_4, val);
/* Setup the switcher mode for SW3 & SW4 */
mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_5, &val);
val &= ~0xf0f;
val |= 0x505;
mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_5, val);
} else {
/* Set switchers in Auto in NORMAL mode & STANDBY mode for Atlas 2.0a */
/* Setup the switcher mode for SW1 & SW2*/
mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_4, &val);
val &= ~0x3c0f;
val |= 0x2008;
mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_4, val);
/* Setup the switcher mode for SW3 & SW4 */
mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_5, &val);
val &= ~0xf0f;
val |= 0x808;
mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_5, val);
}
/* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.5V */
mc13xxx_reg_read(mc13xxx, MC13892_REG_SETTING_0, &val);
val &= ~0x34030;
val |= 0x10020;
mc13xxx_reg_write(mc13xxx, MC13892_REG_SETTING_0, val);
/* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
mc13xxx_reg_read(mc13xxx, MC13892_REG_SETTING_1, &val);
val &= ~0x1FC;
val |= 0x1F4;
mc13xxx_reg_write(mc13xxx, MC13892_REG_SETTING_1, val);
/* Configure VGEN3 and VCAM regulators to use external PNP */
val = 0x208;
mc13xxx_reg_write(mc13xxx, MC13892_REG_MODE_1, val);
udelay(200);
/* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
val = 0x49249;
mc13xxx_reg_write(mc13xxx, MC13892_REG_MODE_1, val);
udelay(200);
pr_info("initialized PMIC\n");
console_flush();
imx51_init_lowlevel(800);
clock_notifier_call_chain();
}
