static void
grackle_write_config(device_t dev, u_int bus, u_int slot, u_int func,
u_int reg, u_int32_t val, int width)
{
struct grackle_softc *sc;
vm_offset_t caoff;
sc = device_get_softc(dev);
caoff = sc->sc_data + (reg & 0x03);
if (grackle_enable_config(sc, bus, slot, func, reg)) {
switch (width) {
case 1:
out8rb(caoff, val);
(void)in8rb(caoff);
break;
case 2:
out16rb(caoff, val);
(void)in16rb(caoff);
break;
case 4:
out32rb(caoff, val);
(void)in32rb(caoff);
break;
}
}
grackle_disable_config(sc);
}
static status_t
grackle_read_pci_config(void *cookie, uint8 bus, uint8 device, uint8 function,
uint8 offset, uint8 size, uint32 *value)
{
grackle_host_bridge *bridge = (grackle_host_bridge*)cookie;
TRACE("grackle_read_pci_config(bus=%u, dev=%u, func=%u, offset=%u, "
"size=%u)\n", (int)bus, (int)device, (int)function, (int)offset,
(int)size);
out32rb(bridge->address_registers, (1 << 31)
| (bus << 16) | ((device & 0x1f) << 11) | ((function & 0x7) << 8)
| (offset & 0xfc));
addr_t dataAddress = bridge->data_registers + (offset & 0x3);
switch (size) {
case 1:
*value = in8rb(dataAddress);
break;
case 2:
*value = in16rb(dataAddress);
break;
case 4:
*value = in32rb(dataAddress);
break;
default:
*value = 0xffffffff;
break;
}
out32rb(bridge->address_registers, 0);
return B_OK;
}
static u_int32_t
uninorth_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
int width)
{
struct uninorth_softc *sc;
vm_offset_t caoff;
sc = device_get_softc(dev);
caoff = sc->sc_data + (reg & 0x07);
if (uninorth_enable_config(sc, bus, slot, func, reg) != 0) {
switch (width) {
case 1:
return (in8rb(caoff));
break;
case 2:
return (in16rb(caoff));
break;
case 4:
return (in32rb(caoff));
break;
}
}
return (0xffffffff);
}
static u_int32_t
grackle_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
int width)
{
struct grackle_softc *sc;
vm_offset_t caoff;
u_int32_t retval = 0xffffffff;
sc = device_get_softc(dev);
caoff = sc->sc_data + (reg & 0x03);
if (grackle_enable_config(sc, bus, slot, func, reg) != 0) {
/*
* Config probes to non-existent devices on the
* secondary bus generates machine checks. Be sure
* to catch these.
*/
if (bus > 0) {
if (badaddr((void *)sc->sc_data, 4)) {
return (retval);
}
}
switch (width) {
case 1:
retval = (in8rb(caoff));
break;
case 2:
retval = (in16rb(caoff));
break;
case 4:
retval = (in32rb(caoff));
break;
}
}
grackle_disable_config(sc);
return (retval);
}
/*
* Interrupt handler for the MACE DMA completion interrupts
*/
int
mc_dmaintr(void *arg)
{
struct mc_softc *sc = arg;
int status, offset, statoff;
int datalen, resid;
int i, n;
dbdma_command_t *cmd;
/* We've received some packets from the MACE */
/* Loop through, processing each of the packets */
i = sc->sc_tail;
for (n = 0; n < MC_RXDMABUFS; n++, i++) {
if (i == MC_RXDMABUFS)
i = 0;
cmd = &sc->sc_rxdmacmd[i];
/* flushcache(cmd, sizeof(dbdma_command_t)); */
status = in16rb(&cmd->d_status);
resid = in16rb(&cmd->d_resid);
/*if ((status & D_ACTIVE) == 0)*/
if ((status & 0x40) == 0)
continue;
#if 1
if (in16rb(&cmd->d_count) != ETHERMTU + 22)
printf("bad d_count\n");
#endif
datalen = in16rb(&cmd->d_count) - resid;
datalen -= 4; /* 4 == status bytes */
if (datalen < 4 + sizeof(struct ether_header)) {
printf("short packet len=%d\n", datalen);
/* continue; */
goto next;
}
offset = i * MC_BUFSIZE;
statoff = offset + datalen;
DBDMA_BUILD_CMD(cmd, DBDMA_CMD_STOP, 0, 0, 0, 0);
__asm volatile("eieio");
/* flushcache(sc->sc_rxbuf + offset, datalen + 4); */
sc->sc_rxframe.rx_rcvcnt = sc->sc_rxbuf[statoff + 0];
sc->sc_rxframe.rx_rcvsts = sc->sc_rxbuf[statoff + 1];
sc->sc_rxframe.rx_rntpc = sc->sc_rxbuf[statoff + 2];
sc->sc_rxframe.rx_rcvcc = sc->sc_rxbuf[statoff + 3];
sc->sc_rxframe.rx_frame = sc->sc_rxbuf + offset;
mc_rint(sc);
next:
DBDMA_BUILD_CMD(cmd, DBDMA_CMD_IN_LAST, 0, DBDMA_INT_ALWAYS,
DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER);
__asm volatile("eieio");
cmd->d_status = 0;
cmd->d_resid = 0;
sc->sc_tail = i + 1;
}
dbdma_continue(sc->sc_rxdma);
return 1;
}
int
bmac_read_reg(struct bmac_softc *sc, int off)
{
return in16rb(sc->sc_regs + off);
}