void cpu_init_f(void) { /* Pointer is writable since we allocated a register for it */ gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); /* Clear initial global data */ memset ((void *) gd, 0, sizeof (gd_t)); #ifdef CONFIG_FSL_LAW init_laws(); #endif setup_bats(); init_early_memctl_regs(); #if defined(CONFIG_FSL_DMA) dma_init(); #endif /* enable the timebase bit in HID0 */ set_hid0(get_hid0() | 0x4000000); /* enable EMCP, SYNCBE | ABE bits in HID1 */ set_hid1(get_hid1() | 0x80000C00); }
void cpu_init_f(void) { volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile ccsr_lbc_t *memctl = &immap->im_lbc; /* Pointer is writable since we allocated a register for it */ gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); /* Clear initial global data */ memset ((void *) gd, 0, sizeof (gd_t)); #ifdef CONFIG_FSL_LAW init_laws(); #endif setup_bats(); /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary * addresses - these have to be modified later when FLASH size * has been determined */ #if defined(CONFIG_SYS_OR0_REMAP) memctl->or0 = CONFIG_SYS_OR0_REMAP; #endif #if defined(CONFIG_SYS_OR1_REMAP) memctl->or1 = CONFIG_SYS_OR1_REMAP; #endif /* now restrict to preliminary range */ #if defined(CONFIG_SYS_BR0_PRELIM) && defined(CONFIG_SYS_OR0_PRELIM) memctl->br0 = CONFIG_SYS_BR0_PRELIM; memctl->or0 = CONFIG_SYS_OR0_PRELIM; #endif #if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM) memctl->or1 = CONFIG_SYS_OR1_PRELIM; memctl->br1 = CONFIG_SYS_BR1_PRELIM; #endif #if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM) memctl->or2 = CONFIG_SYS_OR2_PRELIM; memctl->br2 = CONFIG_SYS_BR2_PRELIM; #endif #if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM) memctl->or3 = CONFIG_SYS_OR3_PRELIM; memctl->br3 = CONFIG_SYS_BR3_PRELIM; #endif #if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM) memctl->or4 = CONFIG_SYS_OR4_PRELIM; memctl->br4 = CONFIG_SYS_BR4_PRELIM; #endif #if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM) memctl->or5 = CONFIG_SYS_OR5_PRELIM; memctl->br5 = CONFIG_SYS_BR5_PRELIM; #endif #if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM) memctl->or6 = CONFIG_SYS_OR6_PRELIM; memctl->br6 = CONFIG_SYS_BR6_PRELIM; #endif #if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM) memctl->or7 = CONFIG_SYS_OR7_PRELIM; memctl->br7 = CONFIG_SYS_BR7_PRELIM; #endif #if defined(CONFIG_FSL_DMA) dma_init(); #endif /* enable the timebase bit in HID0 */ set_hid0(get_hid0() | 0x4000000); /* enable EMCP, SYNCBE | ABE bits in HID1 */ set_hid1(get_hid1() | 0x80000C00); }
/* We run cpu_init_early_f in AS = 1 */ void cpu_init_early_f(void) { u32 mas0, mas1, mas2, mas3, mas7; int i; #ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #endif #if defined(CONFIG_SYS_FSL_ERRATUM_IFC_A003399) && !defined(CONFIG_SYS_RAMBOOT) ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; u32 *l2srbar, *dst, *src; void (*setup_ifc_sram)(void); #endif /* Pointer is writable since we allocated a register for it */ gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); /* * Clear initial global data * we don't use memset so we can share this code with NAND_SPL */ for (i = 0; i < sizeof(gd_t); i++) ((char *)gd)[i] = 0; mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(13); mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_1M); mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G); mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS, 0, MAS3_SW|MAS3_SR); mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_CCSRBAR_PHYS); write_tlb(mas0, mas1, mas2, mas3, mas7); /* * Work Around for IFC Erratum A-003549. This issue is P1010 * specific. LCLK(a free running clk signal) is muxed with IFC_CS3 on P1010 SOC * Hence specifically selecting CS3. */ #ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_LCLK_IFC_CS3); #endif init_laws(); /* * Work Around for IFC Erratum A003399, issue will hit only when execution * from NOR Flash */ #if defined(CONFIG_SYS_FSL_ERRATUM_IFC_A003399) && !defined(CONFIG_SYS_RAMBOOT) #define SRAM_BASE_ADDR (0x00000000) /* TLB for SRAM */ mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(9); mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_1M); mas2 = FSL_BOOKE_MAS2(SRAM_BASE_ADDR, MAS2_I); mas3 = FSL_BOOKE_MAS3(SRAM_BASE_ADDR, 0, MAS3_SX|MAS3_SW|MAS3_SR); mas7 = FSL_BOOKE_MAS7(0); write_tlb(mas0, mas1, mas2, mas3, mas7); out_be32(&l2cache->l2srbar0, SRAM_BASE_ADDR); out_be32(&l2cache->l2errdis, (MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC)); out_be32(&l2cache->l2ctl, (MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE)); /* * Copy the code in setup_ifc to L2SRAM. Do a word copy * because NOR Flash on P1010 does not support byte * access (Erratum IFC-A002769) */ setup_ifc_sram = (void *)SRAM_BASE_ADDR; dst = (u32 *) SRAM_BASE_ADDR; src = (u32 *) setup_ifc; for (i = 0; i < 1024; i++) *l2srbar++ = *src++; setup_ifc_sram(); /* CLEANUP */ clrbits_be32(&l2cache->l2ctl, (MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE)); out_be32(&l2cache->l2srbar0, 0x0); #endif invalidate_tlb(1); #if defined(CONFIG_SECURE_BOOT) /* Disable the TLBs created by ISBC */ for (i = CONFIG_SYS_ISBC_START_TLB; i < CONFIG_SYS_ISBC_START_TLB + CONFIG_SYS_ISBC_NUM_TLBS; i++) disable_tlb(i); #endif init_tlbs(); }
/* We run cpu_init_early_f in AS = 1 */ void cpu_init_early_f(void *fdt) { u32 mas0, mas1, mas2, mas3, mas7; int i; #ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #endif #ifdef CONFIG_A003399_NOR_WORKAROUND ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; u32 *dst, *src; void (*setup_ifc_sram)(void); #endif /* Pointer is writable since we allocated a register for it */ gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); /* * Clear initial global data * we don't use memset so we can share this code with NAND_SPL */ for (i = 0; i < sizeof(gd_t); i++) ((char *)gd)[i] = 0; #ifdef CONFIG_QEMU_E500 /* * CONFIG_SYS_CCSRBAR_PHYS below may use gd->fdt_blob on ePAPR systems, * so we need to populate it before it accesses it. */ gd->fdt_blob = fdt; #endif mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(13); mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_1M); mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G); mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS, 0, MAS3_SW|MAS3_SR); mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_CCSRBAR_PHYS); write_tlb(mas0, mas1, mas2, mas3, mas7); /* * Work Around for IFC Erratum A-003549. This issue is P1010 * specific. LCLK(a free running clk signal) is muxed with IFC_CS3 on P1010 SOC * Hence specifically selecting CS3. */ #ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_LCLK_IFC_CS3); #endif init_laws(); /* * Work Around for IFC Erratum A003399, issue will hit only when execution * from NOR Flash */ #ifdef CONFIG_A003399_NOR_WORKAROUND #define SRAM_BASE_ADDR (0x00000000) /* TLB for SRAM */ mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(9); mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_1M); mas2 = FSL_BOOKE_MAS2(SRAM_BASE_ADDR, MAS2_I); mas3 = FSL_BOOKE_MAS3(SRAM_BASE_ADDR, 0, MAS3_SX|MAS3_SW|MAS3_SR); mas7 = FSL_BOOKE_MAS7(0); write_tlb(mas0, mas1, mas2, mas3, mas7); out_be32(&l2cache->l2srbar0, SRAM_BASE_ADDR); out_be32(&l2cache->l2errdis, (MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC)); out_be32(&l2cache->l2ctl, (MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE)); /* * Copy the code in setup_ifc to L2SRAM. Do a word copy * because NOR Flash on P1010 does not support byte * access (Erratum IFC-A002769) */ setup_ifc_sram = (void *)SRAM_BASE_ADDR; dst = (u32 *) SRAM_BASE_ADDR; src = (u32 *) setup_ifc; for (i = 0; i < 1024; i++) { /* cppcheck-suppress nullPointer */ *dst++ = *src++; } /* cppcheck-suppress nullPointer */ setup_ifc_sram(); /* CLEANUP */ clrbits_be32(&l2cache->l2ctl, (MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE)); out_be32(&l2cache->l2srbar0, 0x0); #endif invalidate_tlb(1); #if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && \ !(defined(CONFIG_SPL_INIT_MINIMAL) && defined(CONFIG_SPL_BUILD)) && \ !defined(CONFIG_NAND_SPL) disable_tlb(CONFIG_SYS_PPC_E500_DEBUG_TLB); #endif init_tlbs(); }