int main()
{
int a[8]={1,2,3,4,5,6,7,8};
pLink L1,L2;
init_link(&L1);
init_link(&L2);
creat_link(a,L1,8);
print_link(L1);
// reverse_link(L1,L2);
L1=reverse2(L1);
print_link(L1);
return 0;
}
static void load_links(char *directory, char *urlprefix)
{
DIR *linkdir;
struct dirent *d;
char fn[PATH_MAX];
dbgprintf("load_links(%s, %s)\n", textornull(directory), textornull(urlprefix));
linkdir = opendir(directory);
if (!linkdir) {
errprintf("Cannot read links in directory %s\n", directory);
return;
}
MEMDEFINE(fn);
while ((d = readdir(linkdir))) {
link_t *newlink;
if (*(d->d_name) == '.') continue;
strcpy(fn, d->d_name);
newlink = init_link(fn, urlprefix);
rbtInsert(linkstree, newlink->key, newlink);
}
closedir(linkdir);
MEMUNDEFINE(fn);
}
int llopen(unsigned int port, unsigned int flag) {
if (init_link(port))
return -1;
linklayer.flag = flag;
int fd = open_port_file(port);
if (flag == RECEIVER) {
if (rec_set(fd))
return -1;
if (send_ua(fd, flag))
return -1;
} else if (flag == SENDER) {
if (send_set(fd))
return -1;
if (rec_ua(fd, flag))
return -1;
} else {
printf("ENTER A VALID STATUS!\n");
close_port_file(fd);
return -1;
}
initialized = -1;
return fd;
}
int main(void)
{
link_t head;
init_link(&head);
student_t *d;
char loop = 1;
while(loop)
{
system("cls");
printf_menu();
switch(getchar())
{
case '1':
new_std(&d);
add_to_link_tail(&head,d);
printf("添加成功 请按任意键返回");
getchar();
getchar();
break;
case '3':
travel_link(&head,show_student);
printf("请按任意键返回");
getchar();
getchar();
break;
case 'q':
loop = 0;
break;
}
}
return 0;
}
static void countline(int dir, struct field *line)
{
int i;
int max;
int counter = -1;
struct count count;
if (hori(dir))
max = XMAX;
else
max = YMAX;
count.zero = count.one = count.num = 0;
count.empty = -1;
for (i=0; i<max; i++) {
init_link(&(line[i]));
make_count(counter, &(line[i]), &count);
if (line[i].value == -1)
count.empty = i;
}
fill_remain(max, line, count);
make_link(max, line, count);
check_link(max, line);
counter = 0;
count.zero = count.one = count.num = 0;
count.empty = -1;
for (i=0; i<max; i++) {
counter = make_count(counter, &(line[i]), &count);
if ((line[i].value == -1) && (line[i].link.x == -1))
count.empty = i;
}
fill_remain(max, line, count);
}
static inline u32
init_nvreg(struct nvbios_init *init, u32 reg)
{
/* C51 (at least) sometimes has the lower bits set which the VBIOS
* interprets to mean that access needs to go through certain IO
* ports instead. The NVIDIA binary driver has been seen to access
* these through the NV register address, so lets assume we can
* do the same
*/
reg &= ~0x00000003;
/* GF8+ display scripts need register addresses mangled a bit to
* select a specific CRTC/OR
*/
if (nv_device(init->bios)->card_type >= NV_50) {
if (reg & 0x80000000) {
reg += init_crtc(init) * 0x800;
reg &= ~0x80000000;
}
if (reg & 0x40000000) {
reg += init_or(init) * 0x800;
reg &= ~0x40000000;
if (reg & 0x20000000) {
reg += init_link(init) * 0x80;
reg &= ~0x20000000;
}
}
}
if (reg & ~0x00fffffc)
warn("unknown bits in register 0x%08x\n", reg);
return reg;
}
link *init_graph_base( int size)
{
int i;
link *l = malloc( sizeof( link) * (size + 1));
for (i = 1; i <= size; i++)
l[i] = init_link();
return l;
}
static void init_link(struct bus *link)
{
struct device *dev;
struct bus *c_link;
for (dev = link->children; dev; dev = dev->sibling)
init_dev(dev);
for (dev = link->children; dev; dev = dev->sibling) {
for (c_link = dev->link_list; c_link; c_link = c_link->next)
init_link(c_link);
}
}
link *rezise_graph_base( link *graph_base, int graph_base_size, int new_size)
{
link *gb = malloc( sizeof( link) * (new_size + 1));
int i;
for( i = 1; i <= graph_base_size; i++)
{
gb[i] = graph_base[i];
graph_base[i] = NULL;
}
/* i := the first index that doesn't belong to the previous graph base. */
while( i <= new_size)
gb[i++] = init_link();
free( graph_base);
return gb;
}
/* TCPIP マネージャの初期化
*/
ER
init_tcpip ()
{
if (!initialized)
{
init_timer ();
init_link ();
init_ip ();
init_udp ();
init_tcp ();
init_arp ();
initialized = 1;
}
return (E_OK);
}
t_state *set_state(t_sys *sys, t_state *state, t_link *link, int *win_tab)
{
t_state *news;
if (!(news = (t_state *)malloc(sizeof(t_state))))
exit(1);
news->size = state->size;
news->id = sys->id;
sys->id++;
news->father = state->id;
news->tab = set_tab(state, link);
init_link(news, state);
news->move_cost = state->move_cost + 1;
news->heur_cost = sys->heuristic_func(news, win_tab);
news->total_cost = news->move_cost + news->heur_cost;
return (news);
}
int pomme_rpcs_init(pomme_rpcs_t *rpcs,
int max_thread,
int max_waiting,
int cur_num)
{
int ret = 0;
assert( rpcs != NULL);
memset( rpcs, 0, sizeof(pomme_rpcs_t));
init_link(&rpcs->func);
rpcs->func_register = &fregister;
rpcs->func_print = &func_print;
ret = pomme_tp_init(&rpcs->thread_pool,
max_thread,max_waiting,cur_num);
return ret;
}
static void make_line(int i, int dir, struct field *line)
{
int j;
int max;
if (hori(dir))
max = XMAX;
else
max = YMAX;
for (j=0; j<max; j++) {
init_link(&(line[i]));
if (hori(dir)) {
line[j].value = field[j][i].value;
line[j].link.x = field[j][i].link.x;
} else {
line[j].value = field[i][j].value;
line[j].link.x = field[i][j].link.y;
}
}
}
t_state *parse_tab(char *file)
{
int fd;
t_state *state;
int size;
char *str;
size = 0;
if ((fd = open(file, O_RDONLY)) == -1 ||
!(state = (t_state *)malloc(sizeof(t_state))))
{
print_usage();
exit(-1);
}
parse_func(fd, &str, size, state);
state->id = 0;
state->father = -1;
init_link(state, NULL);
return (state);
}
/**
* Initialize all devices in the global device tree.
*
* Starting at the root device, call the device's init() method to do
* device-specific setup, then call each child's init() method.
*/
void dev_initialize(void)
{
struct bus *link;
printk(BIOS_INFO, "Initializing devices...\n");
#if CONFIG_ARCH_X86
/* Ensure EBDA is prepared before Option ROMs. */
setup_default_ebda();
#endif
/* First call the mainboard init. */
init_dev(&dev_root);
/* Now initialize everything. */
for (link = dev_root.link_list; link; link = link->next)
init_link(link);
printk(BIOS_INFO, "Devices initialized\n");
show_all_devs(BIOS_SPEW, "After init.");
}
void prim(item vertex[],int numV,int s)
{
int i;
edge_link* link;
link=(edge_link*)malloc(sizeof(edge_link));
edge_adj* curr_node;
edge* curr_edge;
for(i=0;i<numV;i++)
{
vertex[i].color=WHITE;
vertex[i].par=0;
}
vertex[s].color=BLACK;
init_link(link);
curr_edge=vertex[s].adj;
while(curr_edge!=NULL)
{
if(vertex[curr_edge->dest].color==WHITE)
{
insert_link(link,curr_edge->dest,s,curr_edge->weight);
}
curr_edge=curr_edge->next;
}
while(!is_empty(link))
{
curr_node=del_min_link(link);
vertex[curr_node->dest].color=BLACK;
printf("%c %c %d\n",vertex[curr_node->par].data,vertex[curr_node->dest].data,curr_node->weight);
curr_edge=vertex[curr_node->dest].adj;
while(curr_edge!=NULL)
{
if(vertex[curr_edge->dest].color==WHITE)
{
insert_link(link,curr_edge->dest,curr_node->dest,curr_edge->weight);
}
curr_edge=curr_edge->next;
}
free(curr_node);
}
}
static int smdks5p_wm8580_init_paiftx(struct snd_soc_codec *codec)
{
/* Add smdk specific Capture widgets */
snd_soc_dapm_new_controls(codec, wm8580_dapm_widgets_cpt,
ARRAY_SIZE(wm8580_dapm_widgets_cpt));
/* Set up PAIFTX audio path */
snd_soc_dapm_add_routes(codec, audio_map_tx, ARRAY_SIZE(audio_map_tx));
/* LineIn enabled by default */
snd_soc_dapm_enable_pin(codec, "MicIn");
snd_soc_dapm_enable_pin(codec, "LineIn");
/* signal a DAPM event */
snd_soc_dapm_sync(codec);
if (init_link(DAI_I2S_REC)) {
printk("Unable to init dai_link-%d\n", DAI_I2S_REC);
return -EINVAL;
}
return 0;
}
int main(int argc , char **argv)
{
int ret;
NODE *head;
pthread_t id1,id2;
//创建信号量 并初始化其值为 1
if ((ret=sem_init(&mutex, 0, 1)) != 0){
perror("sem_init error");
return -1;
}
head = init_link();
ret = pthread_create(&id1, NULL, (void *)writeDataToFile, head);
ret = pthread_create(&id2, NULL, (void *)readDataFromFile, head);
pthread_join(id1, NULL);
pthread_join(id2, NULL);
return 0;
}
static int smdks5p_wm8580_init_paifrx(struct snd_soc_codec *codec)
{
/* Add smdk specific Playback widgets */
snd_soc_dapm_new_controls(codec, wm8580_dapm_widgets_pbk,
ARRAY_SIZE(wm8580_dapm_widgets_pbk));
/* Set up PAIFRX audio path */
snd_soc_dapm_add_routes(codec, audio_map_rx, ARRAY_SIZE(audio_map_rx));
/* Stereo enabled by default */
snd_soc_dapm_enable_pin(codec, "Front-L/R");
snd_soc_dapm_enable_pin(codec, "Center/Sub");
snd_soc_dapm_enable_pin(codec, "Rear-L/R");
/* signal a DAPM event */
snd_soc_dapm_sync(codec);
if (init_link(DAI_I2S_PBK)) {
printk("Unable to init dai_link-%d\n", DAI_I2S_PBK);
return -EINVAL;
}
return 0;
}
int pomme_rpcs_init(pomme_rpcs_t *rpcs,
void *extra,
int max_thread,
int max_waiting,
int cur_num,
short port)
{
int ret = 0;
assert( rpcs != NULL);
memset( rpcs, 0, sizeof(pomme_rpcs_t));
rpcs->extra = extra;
init_link(&rpcs->func);
rpcs->func_register = &fregister;
rpcs->func_print = &func_print;
rpcs->start = &start;
rpcs->call = &call;
rpcs->port = port;
ret = pomme_tp_init(&rpcs->thread_pool,
max_thread,max_waiting,cur_num);
return ret;
}
board::board() {
memset(m_head, 0, sizeof(m_head));
init();
init_link();
}
/****************************************************
* Function: init_mac
* Description: Initialise the MAC.
*
* NOTE: Will be left on BANK0.
*
* Input:
* NONE
*
* Return:
* SUCCESS If completed
* FAILURE If there was a problem
***************************************************/
RETURN_STATUS init_mac()
{
//
// Initialise some stuff.
//
init_link();
frame_buffer_pos = 0;
mac_header_pos = 0;
// Set callback so that all received data comes back here.
set_recv_data_callback(&recv_frame_bytes);
// NOW MAC CHIP SETUP
//
// Start with bank0 registers.
//
// Set receive buffer;
write_control_register(ERXSTL, (RX_START & 0xFF));
write_control_register(ERXSTH, (RX_START >> 8));
// Rx pointer
write_control_register(ERXRDPTL, (RX_START & 0xFF));
write_control_register(ERXRDPTH, (RX_START >> 8));
//
// Bank 1 looks complicated.
//
// KISS. No filters needed.
// Everything else looks OK as defaults.
//
// Now onto bank 2.
//
write_control_register(ECON1, ECON1_BSEL1);
write_control_register(MACON1, MACON1_TXPAUS | MACON1_RXPAUS | MACON1_MARXEN);
write_control_register(MACON3, MACON3_PADCFG2 | MACON3_PADCFG1 | MACON3_PADCFG0 | MACON3_FRMLNEN | MACON3_TXCRCEN);
write_control_register(MACON4, MACON4_DEFER);
write_control_register(MABBIPG, MABBIPG_BBIPG4 | MABBIPG_BBIPG1);
write_control_register(MAMXFLL, (FRAMELEN_MAX & 0xFF));
write_control_register(MAMXFLH, (FRAMELEN_MAX >> 8));
write_control_register(MAIPGL, (MACIPG_VAL & 0xFF));
write_control_register(MAIPGH, (MACIPG_VAL >> 8));
//
// Bank 3
//
write_control_register(ECON1, ECON1_BSEL0 | ECON1_BSEL1);
/* Get our address and write to device */
uint8_t mac_addr[6];
get_ether_addr(&mac_addr);
write_control_register(MAADR1, mac_addr[0]);
write_control_register(MAADR2, mac_addr[1]);
write_control_register(MAADR3, mac_addr[2]);
write_control_register(MAADR4, mac_addr[3]);
write_control_register(MAADR5, mac_addr[4]);
write_control_register(MAADR6, mac_addr[5]);
// Now init the PHY layer.
// Alter via bank 2
write_control_register(ECON1, ECON1_BSEL1);
// PHY is indirect through MIREGADR, MIWRL, MIWRH
write_control_register(MIREGADR, PHCON2);
write_control_register(MIWRL, (PHCON2_HDLDIS & 0xFF));
write_control_register(MIWRH, (PHCON2_HDLDIS >> 8));
// Now set up ECON1 properly (and leave on bank0)
write_control_register(ECON1, ECON1_RXEN | ECON1_CSUMEN);
// BUSY status now set. Write should take 10uS.
// Easier during init just to wait a tiny while
uint16_t waiting = add_timer(1, NULL);
if(waiting != 0)
{
while(is_running(waiting) == TRUE);
}
return SUCCESS;
}
board::board():m_feasible(board_size*board_size) {
memset(m_head, 0, sizeof(m_head));
init();
init_link();
}