Esempio n. 1
0
void
main (void)
{
  init_usrp ();

  // CPUCS = 0;		// 12 MHz
  // CPUCS = bmCLKSPD0;	// 24 MHz
  CPUCS = bmCLKSPD1;	// 48 MHz
  
  while (1){
    USRP_LED_REG ^= bmLED0;
    udelay (250);
  }
}
Esempio n. 2
0
void init_sys() {
	//Buffer initialize	
	printf("New receiving signal buffer\n");
	s_cnt = (size_t)(1e8/SAMPLE_P * r_sec);
	pkt = new gr_complex[s_cnt];
	if(pkt!= NULL) {
		memset(pkt, 0, sizeof(gr_complex)*s_cnt);
	}

	rate = 1e8/inter;
	freq = 1e9*freq;

	init_usrp();
	//sync_clock();
	init_stream();
}
Esempio n. 3
0
void
main (void)
{
  init_usrp ();
  
  EA = 0;		// disable all interrupts

  setup_autovectors ();
  usb_install_handlers ();

  EIEX4 = 0;
  EA = 1;		// global interrupt enable

  fx2_renumerate ();	// simulates disconnect / reconnect

  main_loop ();
}
Esempio n. 4
0
void
main (void)
{
#if 0
  g_rx_enable = 0;	// FIXME (work around initialization bug)
  g_tx_enable = 0;
  g_rx_overrun = 0;
  g_tx_underrun = 0;
#endif

  PORTECFG = 0x00;
  OEE = 0x0f;
  IOE = 0x0c;

  memset (hash1, 0, USRP_HASH_SIZE);	// zero fpga bitstream hash.  This forces reload

  patch_usb_descriptors();
  init_usrp ();
  init_gpif ();

  // if (UC_START_WITH_GSTATE_OUTPUT_ENABLED)
  // IFCONFIG |= bmGSTATE;			// no conflict, start with it on

  set_led_0 (0);
  set_led_1 (0);

  EA = 0;		// disable all interrupts

  setup_autovectors ();
  usb_install_handlers ();
  hook_timer_tick ((unsigned short) isr_tick);

  EIEX4 = 1;		// disable INT4 FIXME
  EA = 1;		// global interrupt enable

  IOE = 0x04;
  fx2_renumerate ();	// simulates disconnect / reconnect
  IOE = 0x08;

  main_loop ();
}
Esempio n. 5
0
void main(void) {
  
  init_usrp(); 
  init_gpif();
   
 // init_se4110();  	// MIS -  this is no longer required for EK3, 4110 or 4120 varient
  init_se4120();	//  MIS - initialise SE4120 - default is to Hardware programming mode
 
 
  
// ***********Should first read the port (PA3) to see if S/W programming is allowed. **************


//------------------------------------------- Hardware programming start - just keep separate for now 
// Use portA for Hardware programming, 
// as can't split PortB at bit level when functionality of PortB is set to GPIF mode / FIFO mode
  hard_program_se4120(0x01); 	//    0x1 : F0 = 0, F1 = 1, F2=0  : select the chosen Sampling  /Serial format  
//---------------------------------------------Hardware programming end


//-------------------------------------------Software  programming start - just keep separate for now 
// Just re-program it once, then leave in S/W mode
  soft_program_se4120(0xbc, 0x18); //    Change to required S/W Prog mode - MSByte first
//--------------------------------------------Software programming end

 
/*
 //------------------------------------------------debug code start
 while (1) //DEBUG
 {
	 unsigned short i = 0;
	 unsigned short j = 0;
	
	 for (i = 0x0; i <= 0xff; i += 0x4)
		{
			soft_program_se4120((0xFD & i), 0x18); //    Change to required S/W Prog mode - MSByte first 
			toggle_portD();  
			
			for (j = 0x0; j < 0x08; j++)
				{
				mdelay(0xff); // 4 ms x delay = 0.5 secs	((clock is still at 12MHz not 48MHz)
				} 
		}
	
	  //  hold it here ! MIS - else init_usrp will reset FIFO / portb settings.
 } 
 //---------------------------------------------debug code end 
*/


  EA = 0;	// disable all interrupts

  setup_autovectors();
  usb_install_handlers();
    
  EIEX4 = 1;   	      	// disable INT4 FIXME
  EA = 1;           	// global interrupt enable

  fx2_renumerate();	// simulates disconnect / reconnect

 // enable_se4110();         // MIS -  this is no longer required for EK3, 4110 or 4120 varient - leave for EK2 compatibility ?

  main_loop();
}