/******************************
Routine:
Description:
Read a received character if one is
available. Return -1 otherwise.
******************************/
int serial_getc(int channel)
{
if (inreg(channel, LSR) & LSR_DR) {
return inreg(channel, RBR);
}
return -1;
}
void serial_loopback(int flag)
{
if (flag)
outreg(MCR, inreg(MCR) | MCR_LOOP); /* enable loop back mode */
else
outreg(MCR, inreg(MCR) & ~MCR_LOOP); /* disable loop back mode */
}
/* Read a received character if one is available. Return -1 otherwise. */
int serial_getc(void)
{
if (inreg(LSR) & LSR_DR)
return inreg(DataIn);
return -1;
}
/* Read a received character if one is available. Return -1 otherwise. */
int serial_getc()
{
if (inreg(LSR) & LSR_DR)
{
return inreg(DataIn);
}
return -1;
}
static int bus_test ()
{
unsigned char out, in;
int bitpos;
volatile int junk;
junk = (int) &junk; /* Don't let compiler optimize or "registerize" */
outreg(SCR,0); /* Clear scratchpad register */
for (bitpos = 0; bitpos < 8; bitpos++)
{
out = 1 << bitpos;
outreg(SCR,out); /* Write data to scratchpad reg. */
junk = ~0; /* Force data lines high */
in = inreg(SCR); /* Read data */
printf ("%02X ", in);
/* make sure it's what we wrote */
if (in != out)
return (0);
}
outreg(SCR,0); /* Clear scratchpad register */
printf ("\n");
return (1);
}
/*
* Set the baud rate.
*/
void serial_set(unsigned long baud)
{
unsigned char sav_lcr;
if(baud == 0)
baud = 9600L;
/*
* Enable access to the divisor latches by setting DLAB in LCR.
*
*/
sav_lcr = inreg(LCR);
outreg(LCR, LCR_DLAB | sav_lcr);
/*
* Set divisor latches.
*/
outreg(BaudLsb, XTAL/(16*baud));
outreg(BaudMsb, (XTAL/(16*baud)) >> 8);
/*
* Restore line control register
*/
outreg(LCR, sav_lcr);
}
/*
* Initialize the device driver.
*/
void serial_init(void)
{
/* If the serial port has been init'd before, there may be data in it */
/* Wait for the transmit FIFO to empty out before resetting anything */
if (duart_already_init == TRUE)
{
while (!(inreg(LSR) & LSR_TSRE));
}
/*
* Configure active port, (uart_unit already set.)
*
* Set 8 bits, 1 stop bit, no parity.
*
* LCR<7> 0 divisor latch access bit
* LCR<6> 0 break control (1=send break)
* LCR<5> 0 stick parity (0=space, 1=mark)
* LCR<4> 0 parity even (0=odd, 1=even)
* LCR<3> 0 parity enable (1=enabled)
* LCR<2> 0 # stop bits (0=1, 1=1.5)
* LCR<1:0> 11 bits per character(00=5, 01=6, 10=7, 11=8)
*/
outreg(LCR, 0x3);
/* Assert DTR and RTS to prevent hardware handshake problems with
serial terminals, etc. which can be connected to the serial port */
outreg(MCR, MCR_DTR | MCR_RTS);
outreg(FCR, FIFO_ENABLE); /* Enable the FIFO */
outreg(IER, INT_ENABLE); /* Enable appropriate interrupts */
}
/******************************
Routine:
Description:
Set the baud rate.
******************************/
void serial_set(int channel, unsigned long baud)
{
unsigned char sav_lcr;
/*
* Enable access to the divisor latches by setting DLAB in LCR.
*
*/
sav_lcr = inreg(channel, LCR);
#if 0
/*
* Set baud rate
*/
outreg(channel, LCR, LCR_DLAB | sav_lcr);
// outreg(DLL,(XTAL/(16*2*(baud))-2));
outreg(channel, DLL, XTAL / (16 * baud));
// outreg(DLM,(XTAL/(16*2*(baud))-2)>>8);
outreg(channel, DLM, (XTAL / (16 * baud)) >> 8);
#else
/*
* Note: Set baud rate, hardcoded here for rate of 115200
* since became unsure of above "buad rate" algorithm (??).
*/
outreg(channel, LCR, 0x83);
outreg(channel, DLM, 0x00); // See note above
outreg(channel, DLL, 0x02); // See note above.
outreg(channel, LCR, 0x03);
#endif
/*
* Restore line control register
*/
outreg(channel, LCR, sav_lcr);
}
static int mb862xx_i2c_read_byte(struct i2c_adapter *adap, u8 *byte, int last)
{
struct mb862xxfb_par *par = adap->algo_data;
outreg(i2c, GC_I2C_BCR, I2C_START | (last ? 0 : I2C_ACK));
if (!mb862xx_i2c_wait_event(adap))
return 0;
*byte = inreg(i2c, GC_I2C_DAR);
return 1;
}
static int mb862xx_i2c_write_byte(struct i2c_adapter *adap, u8 byte)
{
struct mb862xxfb_par *par = adap->algo_data;
outreg(i2c, GC_I2C_DAR, byte);
outreg(i2c, GC_I2C_BCR, I2C_START);
if (!mb862xx_i2c_wait_event(adap))
return -EIO;
return !(inreg(i2c, GC_I2C_BSR) & I2C_LRB);
}
static void uart_isr (int unused)
{
unsigned char iir;
disable_uart_ints ();
uart_int = 1;
/* read the IIR to clear the interrupt */
iir = inreg(IIR);
return ;
}
static int mb862xx_i2c_do_address(struct i2c_adapter *adap, int addr)
{
struct mb862xxfb_par *par = adap->algo_data;
outreg(i2c, GC_I2C_DAR, addr);
outreg(i2c, GC_I2C_CCR, I2C_CLOCK_AND_ENABLE);
outreg(i2c, GC_I2C_BCR, par->i2c_rs ? I2C_REPEATED_START : I2C_START);
if (!mb862xx_i2c_wait_event(adap))
return -EIO;
par->i2c_rs = !(inreg(i2c, GC_I2C_BSR) & I2C_LRB);
return par->i2c_rs;
}
static int mb862xx_i2c_wait_event(struct i2c_adapter *adap)
{
struct mb862xxfb_par *par = adap->algo_data;
u32 reg;
do {
udelay(1);
reg = inreg(i2c, GC_I2C_BCR);
if (reg & (I2C_INT | I2C_BER))
break;
} while (1);
return (reg & I2C_BER) ? 0 : 1;
}
/* Transmit a character. */
void serial_putc(int c)
{
while ((inreg(LSR) & LSR_THRE) == 0)
;
outreg(DataOut, c);
}
/******************************
Routine:
Description:
Transmit a character.
******************************/
void serial_putc(int channel, int c)
{
while ((inreg(channel, LSR) & LSR_THRE) == 0);
outreg(channel, THR, c);
}
