static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank)
{
unsigned long tmp;
tmp = intc_bank_read_reg(bank, INTC_REVISION) & 0xff;
printk(KERN_INFO "IRQ: Found an INTC at 0x%p "
"(revision %ld.%ld) with %d interrupts\n",
bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs);
tmp = intc_bank_read_reg(bank, INTC_SYSCONFIG);
tmp |= 1 << 1; /* soft reset */
intc_bank_write_reg(tmp, bank, INTC_SYSCONFIG);
while (!(intc_bank_read_reg(bank, INTC_SYSSTATUS) & 0x1))
/* Wait for reset to complete */;
/* Enable autoidle */
intc_bank_write_reg(1 << 0, bank, INTC_SYSCONFIG);
/* Enable protection mode */
__raw_writel(1 << 0, bank->base_reg + INTC_PROTECTION);
/* Disable all interrupts by masking them off. They will be re-enabled when
a handler is registered for them. */
for (tmp = 0; tmp < bank->nr_irqs; tmp += IRQ_BITS_PER_REG)
{
intc_bank_write_reg(0xffffffff, bank, INTC_MIR_SET0 + tmp);
}
/* Set the global enable */
omap_global_enable();
}
static void omap_ack_irq(unsigned int irq)
{
unsigned long tmp;
tmp = intc_bank_read_reg(&irq_banks[0], (INTC_ILR_REG0 + (irq * 0x04)));
if(tmp & 0x01)
{
/* FIQ ACK*/
intc_bank_write_reg(0x02, &irq_banks[0], INTC_CONTROL);
}
else
{
/*IRQ ACK*/
intc_bank_write_reg(0x01, &irq_banks[0], INTC_CONTROL);
}
}
static void omap_global_enable(void)
{
unsigned long tmp;
tmp = intc_bank_read_reg(&irq_banks[0], INTC_SICR);
tmp &= ~(1 << 6);
intc_bank_write_reg(tmp, &irq_banks[0], INTC_SICR);
}
static void omap_irq_set_cfg(int irq, int fiq, int priority)
{
unsigned long val, offset;
val = (fiq & 0x01) | ((priority & 0x3f) << 2) ;
offset = INTC_ILR_REG0 + (irq * 0x04);
intc_bank_write_reg(val, &irq_banks[0], offset);
}
static void omap_unmask_irq(unsigned int irq)
{
int offset = irq & (~(IRQ_BITS_PER_REG - 1));
irq &= (IRQ_BITS_PER_REG - 1);
intc_bank_write_reg(1 << irq, &irq_banks[0], INTC_MIR_CLEAR0 + offset);
}
void omap3_intc_restore_context(void)
{
int ind = 0, i = 0;
for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) {
struct omap_irq_bank *bank = irq_banks + ind;
intc_bank_write_reg(intc_context[ind].sysconfig,
bank, INTC_SYSCONFIG);
intc_bank_write_reg(intc_context[ind].sysconfig,
bank, INTC_SYSCONFIG);
intc_bank_write_reg(intc_context[ind].protection,
bank, INTC_PROTECTION);
intc_bank_write_reg(intc_context[ind].idle,
bank, INTC_IDLE);
intc_bank_write_reg(intc_context[ind].threshold,
bank, INTC_THRESHOLD);
for (i = 0; i < INTCPS_NR_IRQS; i++)
intc_bank_write_reg(intc_context[ind].ilr[i],
bank, (0x100 + 0x4*i));
for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
intc_bank_write_reg(intc_context[ind].mir[i],
&irq_banks[0], INTC_MIR0 + (0x20 * i));
}
/* MIRs are saved and restore with other PRCM registers */
}
static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank)
{
unsigned long tmp;
tmp = intc_bank_read_reg(bank, INTC_REVISION) & 0xff;
printk(KERN_INFO "IRQ: Found an INTC at 0x%p "
"(revision %ld.%ld) with %d interrupts\n",
bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs);
tmp = intc_bank_read_reg(bank, INTC_SYSCONFIG);
tmp |= 1 << 1; /* soft reset */
intc_bank_write_reg(tmp, bank, INTC_SYSCONFIG);
while (!(intc_bank_read_reg(bank, INTC_SYSSTATUS) & 0x1))
/* Wait for reset to complete */;
/* Enable autoidle */
intc_bank_write_reg(1 << 0, bank, INTC_SYSCONFIG);
}
void omap3_intc_autoidle(int enable)
{
u32 read_val;
read_val = intc_bank_read_reg(&irq_banks[0], INTC_SYSCONFIG);
if (!enable)
read_val &= ~0x1;
else
read_val |= 0x1;
intc_bank_write_reg(read_val, &irq_banks[0], INTC_SYSCONFIG);
}
static void omap_mask_irq(unsigned int irq)
{
int offset = irq & (~(IRQ_BITS_PER_REG - 1));
if (cpu_is_omap34xx()) {
int spurious = 0;
/*
* INT_34XX_GPT12_IRQ is also the spurious irq. Maybe because
* it is the highest irq number?
*/
if (irq == INT_34XX_GPT12_IRQ)
spurious = omap_check_spurious(irq);
if (!spurious)
previous_irq = irq;
}
irq &= (IRQ_BITS_PER_REG - 1);
intc_bank_write_reg(1 << irq, &irq_banks[0], INTC_MIR_SET0 + offset);
}
/* XXX: FIQ and additional INTC support (only MPU at the moment) */
static void omap_ack_irq(unsigned int irq)
{
intc_bank_write_reg(0x1, &irq_banks[0], INTC_CONTROL);
}
