int arm_get_next_irq(int last_irq) { uint32_t pending; int32_t irq = last_irq + 1; /* Sanity check */ if (irq < 0) irq = 0; /* TODO: should we mask last_irq? */ pending = intc_read_4(INTC_PENDING_BASIC); while (irq < BANK1_START) { if (pending & (1 << irq)) return irq; irq++; } pending = intc_read_4(INTC_PENDING_BANK1); while (irq < BANK2_START) { if (pending & (1 << IRQ_BANK1(irq))) return irq; irq++; } pending = intc_read_4(INTC_PENDING_BANK2); while (irq <= BANK2_END) { if (pending & (1 << IRQ_BANK2(irq))) return irq; irq++; } return (-1); }
int arm_get_next_irq(int last) { uint32_t value; int i; /* IRQs 0-31 are mapped to LPC_INTC_MIC_SR */ value = intc_read_4(LPC_INTC_MIC_SR); for (i = 0; i < 32; i++) { if (value & (1 << i)) return (i); } /* IRQs 32-63 are mapped to LPC_INTC_SIC1_SR */ value = intc_read_4(LPC_INTC_SIC1_SR); for (i = 0; i < 32; i++) { if (value & (1 << i)) return (i + 32); } /* IRQs 64-95 are mapped to LPC_INTC_SIC2_SR */ value = intc_read_4(LPC_INTC_SIC2_SR); for (i = 0; i < 32; i++) { if (value & (1 << i)) return (i + 64); } return (-1); }
static inline int bcm2835_intc_active_intr(struct bcm_intc_softc *sc) { uint32_t pending, pending_gpu; pending = intc_read_4(sc, INTC_PENDING_BASIC) & INTC_PENDING_BASIC_MASK; if (pending == 0) return (-1); if (pending & INTC_PENDING_BASIC_ARM) return (ffs(pending) - 1); if (pending & INTC_PENDING_BASIC_GPU1_MASK) { if (pending & INTC_PENDING_BASIC_GPU1_7) return (BANK1_START + 7); if (pending & INTC_PENDING_BASIC_GPU1_9) return (BANK1_START + 9); if (pending & INTC_PENDING_BASIC_GPU1_10) return (BANK1_START + 10); if (pending & INTC_PENDING_BASIC_GPU1_18) return (BANK1_START + 18); if (pending & INTC_PENDING_BASIC_GPU1_19) return (BANK1_START + 19); } if (pending & INTC_PENDING_BASIC_GPU2_MASK) { if (pending & INTC_PENDING_BASIC_GPU2_21) return (BANK2_START + 21); if (pending & INTC_PENDING_BASIC_GPU2_22) return (BANK2_START + 22); if (pending & INTC_PENDING_BASIC_GPU2_23) return (BANK2_START + 23); if (pending & INTC_PENDING_BASIC_GPU2_24) return (BANK2_START + 24); if (pending & INTC_PENDING_BASIC_GPU2_25) return (BANK2_START + 25); if (pending & INTC_PENDING_BASIC_GPU2_30) return (BANK2_START + 30); } if (pending & INTC_PENDING_BASIC_GPU1_PEND) { pending_gpu = intc_read_4(sc, INTC_PENDING_BANK1); pending_gpu &= INTC_PENDING_BANK1_MASK; if (pending_gpu != 0) return (BANK1_START + ffs(pending_gpu) - 1); } if (pending & INTC_PENDING_BASIC_GPU2_PEND) { pending_gpu = intc_read_4(sc, INTC_PENDING_BANK2); pending_gpu &= INTC_PENDING_BANK2_MASK; if (pending_gpu != 0) return (BANK2_START + ffs(pending_gpu) - 1); } return (-1); /* It shouldn't end here, but it's hardware. */ }
void arm_unmask_irq(uintptr_t nb) { struct rt1310_intc_softc *sc = intc_softc; uint32_t value; value = intc_read_4(sc, RT_INTC_IECR); value |= (1 << nb); intc_write_4(sc, RT_INTC_IMR, value); intc_write_4(sc, RT_INTC_IECR, value); }
int arm_get_next_irq(int last) { struct rt1310_intc_softc *sc = intc_softc; uint32_t value; int i; value = intc_read_4(sc, RT_INTC_IPR); for (i = 0; i < 32; i++) { if (value & (1 << i)) return (i); } return (-1); }
static void rt1310_intc_eoi(void *data) { struct rt1310_intc_softc *sc = intc_softc; int nb = (int)data; intc_write_4(sc, RT_INTC_ICCR, 1 << nb); if (nb == 0) { uint32_t value; value = intc_read_4(sc, RT_INTC_IECR); value &= ~(1 << nb); intc_write_4(sc, RT_INTC_IECR, value); intc_write_4(sc, RT_INTC_IMR, value); } }
static void rt1310_enable_intr(device_t dev, struct intr_irqsrc *isrc) { u_int irq; unsigned int value; struct rt1310_intc_softc *sc; sc = intc_softc; irq = ((struct rt1310_irqsrc *)isrc)->ri_irq; value = intc_read_4(sc, RT_INTC_IECR); value |= (1 << irq); intc_write_4(sc, RT_INTC_IMR, value); intc_write_4(sc, RT_INTC_IECR, value); }
void arm_mask_irq(uintptr_t nb) { struct rt1310_intc_softc *sc = intc_softc; uint32_t value; /* Make sure that interrupt isn't active already */ rt1310_intc_eoi((void *)nb); /* Clear bit in ER register */ value = intc_read_4(sc, RT_INTC_IECR); value &= ~(1 << nb); intc_write_4(sc, RT_INTC_IECR, value); intc_write_4(sc, RT_INTC_IMR, value); intc_write_4(sc, RT_INTC_ICCR, 1 << nb); }
static int rt1310_intr(void *arg) { uint32_t irq; struct rt1310_intc_softc *sc = arg; irq = ffs(intc_read_4(sc, RT_INTC_IPR)) - 1; if (intr_isrc_dispatch(&sc->ri_isrcs[irq].ri_isrc, curthread->td_intr_frame) != 0) { intc_write_4(sc, RT_INTC_ICCR, 1 << irq); device_printf(sc->dev, "Stray irq %u disabled\n", irq); } arm_irq_memory_barrier(0); return (FILTER_HANDLED); }
static void rt1310_disable_intr(device_t dev, struct intr_irqsrc *isrc) { u_int irq; unsigned int value; struct rt1310_intc_softc *sc; sc = intc_softc; irq = ((struct rt1310_irqsrc *)isrc)->ri_irq; /* Clear bit in ER register */ value = intc_read_4(sc, RT_INTC_IECR); value &= ~(1 << irq); intc_write_4(sc, RT_INTC_IECR, value); intc_write_4(sc, RT_INTC_IMR, value); intc_write_4(sc, RT_INTC_ICCR, 1 << irq); }
void arm_unmask_irq(uintptr_t nb) { int reg; uint32_t value; if (nb > 63) { nb -= 64; reg = LPC_INTC_SIC2_ER; } else if (nb > 31) { nb -= 32; reg = LPC_INTC_SIC1_ER; } else reg = LPC_INTC_MIC_ER; /* Set bit in ER register */ value = intc_read_4(reg); value |= (1 << nb); intc_write_4(reg, value); }
static void lpc_intc_eoi(void *data) { int reg; int nb = (int)data; uint32_t value; if (nb > 63) { nb -= 64; reg = LPC_INTC_SIC2_RSR; } else if (nb > 31) { nb -= 32; reg = LPC_INTC_SIC1_RSR; } else reg = LPC_INTC_MIC_RSR; /* Set bit in RSR register */ value = intc_read_4(reg); value |= (1 << nb); intc_write_4(reg, value); }
void arm_mask_irq(uintptr_t nb) { int reg; uint32_t value; /* Make sure that interrupt isn't active already */ lpc_intc_eoi((void *)nb); if (nb > 63) { nb -= 64; reg = LPC_INTC_SIC2_ER; } else if (nb > 31) { nb -= 32; reg = LPC_INTC_SIC1_ER; } else reg = LPC_INTC_MIC_ER; /* Clear bit in ER register */ value = intc_read_4(reg); value &= ~(1 << nb); intc_write_4(reg, value); }