static void brw_emit_prim( struct brw_context *brw, const struct _mesa_prim *prim ) { struct brw_3d_primitive prim_packet; if (INTEL_DEBUG & DEBUG_PRIMS) _mesa_printf("PRIM: %s %d %d\n", _mesa_lookup_enum_by_nr(prim->mode), prim->start, prim->count); prim_packet.header.opcode = CMD_3D_PRIM; prim_packet.header.length = sizeof(prim_packet)/4 - 2; prim_packet.header.pad = 0; prim_packet.header.topology = brw_set_prim(brw, prim->mode); prim_packet.header.indexed = prim->indexed; prim_packet.verts_per_instance = trim(prim->mode, prim->count); prim_packet.start_vert_location = prim->start; prim_packet.instance_count = 1; prim_packet.start_instance_location = 0; prim_packet.base_vert_location = 0; if (prim_packet.verts_per_instance) { intel_batchbuffer_data( brw->intel.batch, &prim_packet, sizeof(prim_packet), INTEL_BATCH_NO_CLIPRECTS); } }
/* A facility similar to the data caching code above, which aims to * prevent identical commands being issued repeatedly. */ GLboolean brw_cached_batch_struct( struct brw_context *brw, const void *data, GLuint sz ) { struct brw_cached_batch_item *item = brw->cached_batch_items; struct header *newheader = (struct header *)data; if (brw->emit_state_always) { intel_batchbuffer_data(brw->intel.batch, data, sz, false); return GL_TRUE; } while (item) { if (item->header->opcode == newheader->opcode) { if (item->sz == sz && memcmp(item->header, newheader, sz) == 0) return GL_FALSE; if (item->sz != sz) { free(item->header); item->header = malloc(sz); item->sz = sz; } goto emit; } item = item->next; } assert(!item); item = CALLOC_STRUCT(brw_cached_batch_item); item->header = malloc(sz); item->sz = sz; item->next = brw->cached_batch_items; brw->cached_batch_items = item; emit: memcpy(item->header, newheader, sz); intel_batchbuffer_data(brw->intel.batch, data, sz, false); return GL_TRUE; }
static void brw_emit_cliprect( struct brw_context *brw, const drm_clip_rect_t *rect ) { struct brw_drawrect bdr; bdr.header.opcode = CMD_DRAW_RECT; bdr.header.length = sizeof(bdr)/4 - 2; bdr.xmin = rect->x1; bdr.xmax = rect->x2 - 1; bdr.ymin = rect->y1; bdr.ymax = rect->y2 - 1; bdr.xorg = brw->intel.drawX; bdr.yorg = brw->intel.drawY; intel_batchbuffer_data( brw->intel.batch, &bdr, sizeof(bdr), INTEL_BATCH_NO_CLIPRECTS); }
bool gen75_send_avc_picid_state( struct intel_batchbuffer *batch, GenFrameStore frame_store[MAX_GEN_REFERENCE_FRAMES] ) { uint16_t pic_ids[16]; if (!gen75_fill_avc_picid_list(pic_ids, frame_store)) return false; BEGIN_BCS_BATCH(batch, 10); OUT_BCS_BATCH(batch, MFD_AVC_PICID_STATE | (10 - 2)); OUT_BCS_BATCH(batch, 0); // enable Picture ID Remapping intel_batchbuffer_data(batch, pic_ids, sizeof(pic_ids)); ADVANCE_BCS_BATCH(batch); return true; }
static void brw_emit_prim(struct brw_context *brw, const struct _mesa_prim *prim, uint32_t hw_prim) { struct brw_3d_primitive prim_packet; struct intel_context *intel = &brw->intel; if (INTEL_DEBUG & DEBUG_PRIMS) printf("PRIM: %s %d %d\n", _mesa_lookup_enum_by_nr(prim->mode), prim->start, prim->count); prim_packet.header.opcode = CMD_3D_PRIM; prim_packet.header.length = sizeof(prim_packet)/4 - 2; prim_packet.header.pad = 0; prim_packet.header.topology = hw_prim; prim_packet.header.indexed = prim->indexed; prim_packet.verts_per_instance = trim(prim->mode, prim->count); prim_packet.start_vert_location = prim->start; if (prim->indexed) prim_packet.start_vert_location += brw->ib.start_vertex_offset; prim_packet.instance_count = 1; prim_packet.start_instance_location = 0; prim_packet.base_vert_location = prim->basevertex; /* If we're set to always flush, do it before and after the primitive emit. * We want to catch both missed flushes that hurt instruction/state cache * and missed flushes of the render cache as it heads to other parts of * the besides the draw code. */ if (intel->always_flush_cache) { intel_batchbuffer_emit_mi_flush(intel->batch); } if (prim_packet.verts_per_instance) { intel_batchbuffer_data( brw->intel.batch, &prim_packet, sizeof(prim_packet)); } if (intel->always_flush_cache) { intel_batchbuffer_emit_mi_flush(intel->batch); } }
/* Emit Reference List Entries (Gen6+: SNB, IVB) */ static void gen6_send_avc_ref_idx_state_1( struct intel_batchbuffer *batch, unsigned int list, const VAPictureH264 *ref_list, unsigned int ref_list_count, const GenFrameStore frame_store[MAX_GEN_REFERENCE_FRAMES] ) { uint8_t ref_idx_state[32]; BEGIN_BCS_BATCH(batch, 10); OUT_BCS_BATCH(batch, MFX_AVC_REF_IDX_STATE | (10 - 2)); OUT_BCS_BATCH(batch, list); gen5_fill_avc_ref_idx_state( ref_idx_state, ref_list, ref_list_count, frame_store ); intel_batchbuffer_data(batch, ref_idx_state, sizeof(ref_idx_state)); ADVANCE_BCS_BATCH(batch); }
bool intelEmitImmediateColorExpandBlit(struct intel_context *intel, GLuint cpp, GLubyte *src_bits, GLuint src_size, GLuint fg_color, GLshort dst_pitch, drm_intel_bo *dst_buffer, GLuint dst_offset, uint32_t dst_tiling, GLshort x, GLshort y, GLshort w, GLshort h, GLenum logic_op) { int dwords = ALIGN(src_size, 8) / 4; uint32_t opcode, br13, blit_cmd; if (dst_tiling != I915_TILING_NONE) { if (dst_offset & 4095) return false; if (dst_tiling == I915_TILING_Y) return false; } assert((logic_op >= GL_CLEAR) && (logic_op <= (GL_CLEAR + 0x0f))); assert(dst_pitch > 0); if (w < 0 || h < 0) return true; DBG("%s dst:buf(%p)/%d+%d %d,%d sz:%dx%d, %d bytes %d dwords\n", __FUNCTION__, dst_buffer, dst_pitch, dst_offset, x, y, w, h, src_size, dwords); intel_batchbuffer_require_space(intel, (8 * 4) + (3 * 4) + dwords * 4); opcode = XY_SETUP_BLT_CMD; if (cpp == 4) opcode |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB; br13 = dst_pitch | (translate_raster_op(logic_op) << 16) | (1 << 29); br13 |= br13_for_cpp(cpp); blit_cmd = XY_TEXT_IMMEDIATE_BLIT_CMD | XY_TEXT_BYTE_PACKED; /* packing? */ if (dst_tiling != I915_TILING_NONE) blit_cmd |= XY_DST_TILED; BEGIN_BATCH(8 + 3); OUT_BATCH(opcode | (8 - 2)); OUT_BATCH(br13); OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */ OUT_BATCH((100 << 16) | 100); /* clip x2, y2 */ OUT_RELOC_FENCED(dst_buffer, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, dst_offset); OUT_BATCH(0); /* bg */ OUT_BATCH(fg_color); /* fg */ OUT_BATCH(0); /* pattern base addr */ OUT_BATCH(blit_cmd | ((3 - 2) + dwords)); OUT_BATCH((y << 16) | x); OUT_BATCH(((y + h) << 16) | (x + w)); ADVANCE_BATCH(); intel_batchbuffer_data(intel, src_bits, dwords * 4); intel_batchbuffer_emit_mi_flush(intel); return true; }
void intelEmitImmediateColorExpandBlit(struct intel_context *intel, GLuint cpp, GLubyte *src_bits, GLuint src_size, GLuint fg_color, GLshort dst_pitch, dri_bo *dst_buffer, GLuint dst_offset, GLboolean dst_tiled, GLshort x, GLshort y, GLshort w, GLshort h, GLenum logic_op) { int dwords = ALIGN(src_size, 8) / 4; uint32_t opcode, br13, blit_cmd; assert( logic_op - GL_CLEAR >= 0 ); assert( logic_op - GL_CLEAR < 0x10 ); if (w < 0 || h < 0) return; dst_pitch *= cpp; DBG("%s dst:buf(%p)/%d+%d %d,%d sz:%dx%d, %d bytes %d dwords\n", __FUNCTION__, dst_buffer, dst_pitch, dst_offset, x, y, w, h, src_size, dwords); intel_batchbuffer_require_space( intel->batch, (8 * 4) + (3 * 4) + dwords, NO_LOOP_CLIPRECTS ); opcode = XY_SETUP_BLT_CMD; if (cpp == 4) opcode |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB; #ifndef I915 if (dst_tiled) { opcode |= XY_DST_TILED; dst_pitch /= 4; } #endif br13 = dst_pitch | (translate_raster_op(logic_op) << 16) | (1 << 29); if (cpp == 2) br13 |= BR13_565; else br13 |= BR13_8888; blit_cmd = XY_TEXT_IMMEDIATE_BLIT_CMD | XY_TEXT_BYTE_PACKED; /* packing? */ if (dst_tiled) blit_cmd |= XY_DST_TILED; BEGIN_BATCH(8 + 3, NO_LOOP_CLIPRECTS); OUT_BATCH(opcode); OUT_BATCH(br13); OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */ OUT_BATCH((100 << 16) | 100); /* clip x2, y2 */ OUT_RELOC(dst_buffer, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_WRITE, dst_offset); OUT_BATCH(0); /* bg */ OUT_BATCH(fg_color); /* fg */ OUT_BATCH(0); /* pattern base addr */ OUT_BATCH(blit_cmd | ((3 - 2) + dwords)); OUT_BATCH((y << 16) | x); OUT_BATCH(((y + h) << 16) | (x + w)); ADVANCE_BATCH(); intel_batchbuffer_data( intel->batch, src_bits, dwords * 4, NO_LOOP_CLIPRECTS ); }
bool intelEmitImmediateColorExpandBlit(struct brw_context *brw, GLuint cpp, GLubyte *src_bits, GLuint src_size, GLuint fg_color, GLshort dst_pitch, struct brw_bo *dst_buffer, GLuint dst_offset, enum isl_tiling dst_tiling, GLshort x, GLshort y, GLshort w, GLshort h, enum gl_logicop_mode logic_op) { const struct gen_device_info *devinfo = &brw->screen->devinfo; int dwords = ALIGN(src_size, 8) / 4; uint32_t opcode, br13, blit_cmd; if (dst_tiling != ISL_TILING_LINEAR) { if (dst_offset & 4095) return false; if (dst_tiling == ISL_TILING_Y0) return false; } assert((unsigned) logic_op <= 0x0f); assert(dst_pitch > 0); if (w < 0 || h < 0) return true; DBG("%s dst:buf(%p)/%d+%d %d,%d sz:%dx%d, %d bytes %d dwords\n", __func__, dst_buffer, dst_pitch, dst_offset, x, y, w, h, src_size, dwords); unsigned xy_setup_blt_length = devinfo->gen >= 8 ? 10 : 8; intel_batchbuffer_require_space(brw, (xy_setup_blt_length * 4) + (3 * 4) + dwords * 4); opcode = XY_SETUP_BLT_CMD; if (cpp == 4) opcode |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB; if (dst_tiling != ISL_TILING_LINEAR) { opcode |= XY_DST_TILED; dst_pitch /= 4; } br13 = dst_pitch | (translate_raster_op(logic_op) << 16) | (1 << 29); br13 |= br13_for_cpp(cpp); blit_cmd = XY_TEXT_IMMEDIATE_BLIT_CMD | XY_TEXT_BYTE_PACKED; /* packing? */ if (dst_tiling != ISL_TILING_LINEAR) blit_cmd |= XY_DST_TILED; BEGIN_BATCH_BLT(xy_setup_blt_length + 3); OUT_BATCH(opcode | (xy_setup_blt_length - 2)); OUT_BATCH(br13); OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */ OUT_BATCH((100 << 16) | 100); /* clip x2, y2 */ if (devinfo->gen >= 8) { OUT_RELOC64(dst_buffer, RELOC_WRITE, dst_offset); } else { OUT_RELOC(dst_buffer, RELOC_WRITE, dst_offset); } OUT_BATCH(0); /* bg */ OUT_BATCH(fg_color); /* fg */ OUT_BATCH(0); /* pattern base addr */ if (devinfo->gen >= 8) OUT_BATCH(0); OUT_BATCH(blit_cmd | ((3 - 2) + dwords)); OUT_BATCH(SET_FIELD(y, BLT_Y) | SET_FIELD(x, BLT_X)); OUT_BATCH(SET_FIELD(y + h, BLT_Y) | SET_FIELD(x + w, BLT_X)); ADVANCE_BATCH(); intel_batchbuffer_data(brw, src_bits, dwords * 4); brw_emit_mi_flush(brw); return true; }
void intelEmitImmediateColorExpandBlit(struct intel_context *intel, GLuint cpp, GLubyte *src_bits, GLuint src_size, GLuint fg_color, GLshort dst_pitch, struct buffer *dst_buffer, GLuint dst_offset, GLboolean dst_tiled, GLshort x, GLshort y, GLshort w, GLshort h, GLenum logic_op) { struct xy_setup_blit setup; struct xy_text_immediate_blit text; int dwords = ((src_size + 7) & ~7) / 4; assert( logic_op - GL_CLEAR >= 0 ); assert( logic_op - GL_CLEAR < 0x10 ); if (w < 0 || h < 0) return; dst_pitch *= cpp; if (dst_tiled) dst_pitch /= 4; DBG("%s dst:buf(%p)/%d+%d %d,%d sz:%dx%d, %d bytes %d dwords\n", __FUNCTION__, dst_buffer, dst_pitch, dst_offset, x, y, w, h, src_size, dwords); memset(&setup, 0, sizeof(setup)); setup.br0.client = CLIENT_2D; setup.br0.opcode = OPCODE_XY_SETUP_BLT; setup.br0.write_alpha = (cpp == 4); setup.br0.write_rgb = (cpp == 4); setup.br0.dst_tiled = dst_tiled; setup.br0.length = (sizeof(setup) / sizeof(int)) - 2; setup.br13.dest_pitch = dst_pitch; setup.br13.rop = translate_raster_op(logic_op); setup.br13.color_depth = (cpp == 4) ? BR13_8888 : BR13_565; setup.br13.clipping_enable = 0; setup.br13.mono_source_transparency = 1; setup.dw2.clip_y1 = 0; setup.dw2.clip_x1 = 0; setup.dw3.clip_y2 = 100; setup.dw3.clip_x2 = 100; setup.dest_base_addr = bmBufferOffset(intel, dst_buffer) + dst_offset; setup.background_color = 0; setup.foreground_color = fg_color; setup.pattern_base_addr = 0; memset(&text, 0, sizeof(text)); text.dw0.client = CLIENT_2D; text.dw0.opcode = OPCODE_XY_TEXT_IMMEDIATE_BLT; text.dw0.pad0 = 0; text.dw0.byte_packed = 1; /* ?maybe? */ text.dw0.pad1 = 0; text.dw0.dst_tiled = dst_tiled; text.dw0.pad2 = 0; text.dw0.length = (sizeof(text)/sizeof(int)) - 2 + dwords; text.dw1.dest_y1 = y; /* duplicates info in setup blit */ text.dw1.dest_x1 = x; text.dw2.dest_y2 = y + h; text.dw2.dest_x2 = x + w; intel_batchbuffer_require_space( intel->batch, sizeof(setup) + sizeof(text) + dwords, INTEL_BATCH_NO_CLIPRECTS ); intel_batchbuffer_data( intel->batch, &setup, sizeof(setup), INTEL_BATCH_NO_CLIPRECTS ); intel_batchbuffer_data( intel->batch, &text, sizeof(text), INTEL_BATCH_NO_CLIPRECTS ); intel_batchbuffer_data( intel->batch, src_bits, dwords * 4, INTEL_BATCH_NO_CLIPRECTS ); }