Esempio n. 1
0
static const struct firmware *
load_firmware(struct device *dev)
{
	const struct firmware *fw;
	int rc;
	char *fw_path = IS_ISP2400 ? ISP2400B0_FW_PATH : MFLD_FW_PATH;

	if (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_VALLEYVIEW2)
		fw_path = ISP2400B0_FW_PATH;

	if (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_TANGIER)
		fw_path = ISP2400A0_FW_PATH;

	rc = request_firmware(&fw, fw_path, dev);
	if (rc) {
		if (rc == -ENOENT)
			v4l2_err(&atomisp_dev,
				    "Error ISP firmware %s not found.\n",
				    fw_path);
		else
			v4l2_err(&atomisp_dev,
				    "atomisp: Error %d while requesting"
				    " firmware %s\n", rc, fw_path);
		return NULL;
	}

	if (fw->data == NULL) {
		v4l2_err(&atomisp_dev,
			    "ISP firmware data is NULL.\n");
		return NULL;
	}

	return fw;
}
static u32 get_flis_offset_by_gpio(int gpio)
{
	int i;
	int start;
	u32 offset = -EINVAL, size;
	struct gpio_flis_pair *gpio_flis_map;

	if (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_TANGIER) {
		size = ARRAY_SIZE(gpio_flis_tng_mapping_table);
		gpio_flis_map = gpio_flis_tng_mapping_table;
	} else if (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_ANNIEDALE) {
		size = ARRAY_SIZE(gpio_flis_ann_mapping_table);
		gpio_flis_map = gpio_flis_ann_mapping_table;
	} else
		return -EINVAL;

	for (i = 0; i < size - 1; i++) {
		if (gpio >= gpio_flis_map[i].gpio
			&& gpio < gpio_flis_map[i + 1].gpio)
			break;
	}

	start = gpio_flis_map[i].gpio;

	if (gpio_flis_map[i].offset != -EINVAL)
		offset = gpio_flis_map[i].offset + (gpio - start) * 4;

	return offset;
}
Esempio n. 3
0
static int __init mip_module_init(void)
{
	if ((intel_mid_identify_cpu() != INTEL_MID_CPU_CHIP_PENWELL)
		&& (intel_mid_identify_cpu() != INTEL_MID_CPU_CHIP_CLOVERVIEW))
		return -EINVAL;

	return ipc_driver_register(&mip_driver);
}
void mrst_early_console_init(void)
{
	u32 ctrlr0 = 0;
	u32 spi0_cdiv;
	u32 freq; /* Freqency info only need be searched once */

	/* Base clk is 100 MHz, the actual clk = 100M / (clk_divider + 1) */
	pclk_spi0 = (void *)set_fixmap_offset_nocache(FIX_EARLYCON_MEM_BASE,
							MRST_CLK_SPI0_REG);
	spi0_cdiv = ((*pclk_spi0) & 0xe00) >> 9;
	freq = 100000000 / (spi0_cdiv + 1);

	if (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_PENWELL)
		mrst_spi_paddr = MRST_REGBASE_SPI1;
	else if (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_CLOVERVIEW)
		mrst_spi_paddr = CLV_REGBASE_SPI1;

	pspi = (void *)set_fixmap_offset_nocache(FIX_EARLYCON_MEM_BASE,
						mrst_spi_paddr);

	/* Disable SPI controller */
	dw_writel(pspi, ssienr, 0);

	/* Set control param, 8 bits, transmit only mode */
	ctrlr0 = dw_readl(pspi, ctrl0);

	ctrlr0 &= 0xfcc0;
	ctrlr0 |= 0xf | (SPI_FRF_SPI << SPI_FRF_OFFSET)
		      | (SPI_TMOD_TO << SPI_TMOD_OFFSET);
	dw_writel(pspi, ctrl0, ctrlr0);

	/*
	 * Change the spi0 clk to comply with 115200 bps, use 100000 to
	 * calculate the clk dividor to make the clock a little slower
	 * than real baud rate.
	 */
	dw_writel(pspi, baudr, freq/100000);

	/* Disable all INT for early phase */
	dw_writel(pspi, imr, 0x0);

	/* Set the cs to spi-uart */
	dw_writel(pspi, ser, 0x2);

	/* Enable the HW, the last step for HW init */
	dw_writel(pspi, ssienr, 0x1);

	/* Set the default configuration */
	max3110_spi_write_config();

	/* Register the kmsg dumper */
	if (!dumper_registered) {
		dw_dumper.dump = dw_kmsg_dump;
		kmsg_dump_register(&dw_dumper);
		dumper_registered = 1;
	}
}
Esempio n. 5
0
/*
 * Checking the SOC type is temporary workaround to enable OV8830
 * on Bodegabay (tangier) platform. Once standard regulator devices
 * (e.g. vprog1, vprog2) and control functions (pmic_avp) are added
 * for the platforms with tangier, then we can revert this change.
 * ([email protected])
 */
static int ov8830_power_ctrl(struct v4l2_subdev *sd, int flag)
{
	int ret = 0;

	/* The camera powering is different on RedHookBay and VictoriaBay
	 * On RHB, vprog1 is at 2.8V and supplies both cameras
	 * On VB, vprog1 supplies the 2nd camera and must not rise over 1.2V
	 * Check if the RHB SW has accidentally been flashed to VB
	 * If yes, don't turn on the regulator. The VB secondary camera will
	 * be permanently damaged by the too high voltage
	 */
	if (INTEL_MID_BOARD(2, PHONE, CLVTP, VB, PRO) ||
	    INTEL_MID_BOARD(2, PHONE, CLVTP, VB, ENG)) {
		printk(KERN_ALERT \
		"Aborted vprog1 enable to protect VictoriaBay 2nd camera HW\n");
		return -ENODEV;
	}

	if (flag) {
		if (!camera_vprog1_on) {
			if (intel_mid_identify_cpu() ==
			   INTEL_MID_CPU_CHIP_TANGIER)
				ret = intel_scu_ipc_msic_vprog1(1);
			else
				ret = regulator_enable(vprog1_reg);
			if (!ret)
				camera_vprog1_on = 1;
			else
				printk(KERN_ALERT "Failed to enable regulator vprog1\n");
			return ret;
		}
	} else {
		if (camera_vprog1_on) {
			if (intel_mid_identify_cpu() ==
			   INTEL_MID_CPU_CHIP_TANGIER)
				ret = intel_scu_ipc_msic_vprog1(0);
			else
				ret = regulator_disable(vprog1_reg);

			if (!ret)
				camera_vprog1_on = 0;
			else
				printk(KERN_ALERT "Failed to disable regulator vprog1\n");
			return ret;
		}
	}
	return ret;
}
Esempio n. 6
0
/*
 * Checking the SOC type is temporary workaround to enable OV8830 on Bodegabay
 * (tangier) platform once standard regulator devices (e.g. vprog1, vprog2) and
 * control functions (pmic_avp) are added for the platforms with tangier, then
 * we can revert this change.([email protected]
 */
static int ov8830_platform_deinit(void)
{
	if (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_TANGIER)
		return 0;

	regulator_put(vprog1_reg);
}
Esempio n. 7
0
static int atomisp_resume(struct device *dev)
{
	struct atomisp_device *isp = (struct atomisp_device *)
		dev_get_drvdata(dev);
	int ret;

	if (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_VALLEYVIEW2) {
		ret = pmu_nc_set_power_state(TNG_ISP_ISLAND, OSPM_ISLAND_UP,
					MRFLD_ISPSSPM0);
		if (ret)
			return ret;
	}

	pm_qos_update_request(&isp->pm_qos, isp->max_isr_latency);

	/*Turn on ISP d-phy */
	ret = atomisp_ospm_dphy_up(isp);
	if (ret) {
		v4l2_err(&atomisp_dev,
			    "Failed to power up ISP!.\n");
		return -EINVAL;
	}

	/*restore register values for iUnit and iUnitPHY registers*/
	if (isp->saved_regs.pcicmdsts)
		atomisp_restore_iunit_reg(isp);

	if (IS_ISP2400)
		atomisp_freq_scaling(isp, ATOMISP_DFS_MODE_LOW);

	return 0;
}
int intel_mid_hsu_func_to_port(unsigned int func)
{
	int i;
	struct hsu_func2port *tbl = NULL;

	switch (intel_mid_identify_cpu()) {
	case INTEL_MID_CPU_CHIP_CLOVERVIEW:
		tbl = &hsu_port_func_id_tlb[hsu_clv][0];
		break;
	case INTEL_MID_CPU_CHIP_TANGIER:
	case INTEL_MID_CPU_CHIP_ANNIEDALE:
		tbl = &hsu_port_func_id_tlb[hsu_tng][0];
		break;
	case INTEL_MID_CPU_CHIP_PENWELL:
		tbl = &hsu_port_func_id_tlb[hsu_pnw][0];
		break;
	default:
		/* FIXME: VALLEYVIEW2? */
		/* 1e.3 and 1e.4 */
		tbl = &hsu_port_func_id_tlb[hsu_vlv2][0];
		break;
	}

	for (i = 0; i < hsu_port_func_max; i++) {
		if (tbl->func == func)
			return tbl->port;
		tbl++;
	}

	return -1;
}
static int stm_xfer_start(void)
{
	struct stm_dev *stm = _dev_stm;
	struct stm_ctrl *stm_ctrl;
	u32 reg_word;

	if (!stm)
		return -ENODEV;

	/* REVERTME : filter PUNIT and SCU MasterID when switching to USB */
	if (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_ANNIEDALE) {
		pr_info("%s\n REVERTME : filter PUNIT and SCU MasterID\n", __func__);
		reg_word = stm_readl(stm->stm_ioaddr, (u32)STM_MASMSK1);
		reg_word |= 0x28;
		stm_writel(stm->stm_ioaddr, (u32)STM_MASMSK1, reg_word);

		pr_info("%s\n REVERTME : USBTO\n", __func__);
		reg_word = stm_readl(stm->stm_ioaddr, (u32)STM_USBTO);
		reg_word |= 0x01;
		stm_writel(stm->stm_ioaddr, (u32)STM_USBTO, reg_word);
	}

	stm_ctrl = &stm->stm_ctrl_hwreg;
	stm_ctrl->reg_word = stm_readl(stm->stm_ioaddr, (u32)STM_CTRL);

	stm_ctrl->usb_debug_en = true;
	stm_ctrl->pti_out_en = false;

	stm_writel(stm->stm_ioaddr, (u32)STM_CTRL, stm_ctrl->reg_word);
	pr_info("%s\n switch STM output to DvC.Trace ", __func__);

	return 0;
}
Esempio n. 10
0
static __init int add_rtc_cmos(void)
{
#ifdef CONFIG_PNP
	static const char *ids[] __initconst =
	    { "PNP0b00", "PNP0b01", "PNP0b02", };
	struct pnp_dev *dev;
	struct pnp_id *id;
	int i;

	pnp_for_each_dev(dev) {
		for (id = dev->id; id; id = id->next) {
			for (i = 0; i < ARRAY_SIZE(ids); i++) {
				if (compare_pnp_id(id, ids[i]) != 0)
					return 0;
			}
		}
	}
#endif
	if (of_have_populated_dt())
		return 0;

	/* Intel MID platforms don't have ioport rtc */
	if (intel_mid_identify_cpu())
		return -ENODEV;

	platform_device_register(&rtc_device);
	dev_info(&rtc_device.dev,
		 "registered platform RTC device (no PNP device found)\n");

	return 0;
}
static int __init regulator_init(void)
{
	if (intel_mid_identify_cpu() != INTEL_MID_CPU_CHIP_CLOVERVIEW)
		return 0;

	if (INTEL_MID_BOARD(2, PHONE, CLVTP, VB, PRO)
	    || INTEL_MID_BOARD(2, PHONE, CLVTP, VB, ENG)
	    || INTEL_MID_BOARD(3, PHONE, CLVTP, RHB, PRO, VVLITE)
	    || INTEL_MID_BOARD(3, PHONE, CLVTP, RHB, ENG, VVLITE)
	    || ((INTEL_MID_BOARD(2, PHONE, CLVTP, RHB, PRO)
		 || INTEL_MID_BOARD(2, PHONE, CLVTP, RHB, ENG))
		&& (SPID_HARDWARE_ID(CLVTP, PHONE, VB, PR1A)
		    || SPID_HARDWARE_ID(CLVTP, PHONE, VB, PR1B)
		    || SPID_HARDWARE_ID(CLVTP, PHONE, VB, PR20))))
		atom_regulator_victoriabay_init();
	else if (INTEL_MID_BOARD(2, PHONE, CLVTP, RHB, PRO)
		 || INTEL_MID_BOARD(2, PHONE, CLVTP, RHB, ENG))
		atom_regulator_redhookbay_init();

	platform_device_register(&vprog2_device);
	platform_device_register(&vemmc1_device); //ASUS_BSP+++
	platform_device_register(&vemmc2_device);
	platform_device_register(&vccsdio_device);

	return 0;
}
static int camera_set_vprog3(bool flag, enum camera_vprog_voltage voltage)
{
	/*
	 * Currently it is not possible to control the voltage outside of
	 * intel_scu_ipcut so have to do it manually here
	 */
#define MSIC_VPROG3_MRFLD_CTRL		0xae
#define MSIC_VPROG3_MRFLD_ON_1_05	0x01	/* 1.05V and Auto mode */
#define MSIC_VPROG3_MRFLD_ON_1_83	0x41	/* 1.83V and Auto mode */
#define MSIC_VPROG_MRFLD_OFF		0	/* OFF */

	if (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_ANNIEDALE) {
		if (voltage == CAMERA_1_05_VOLT) {
			return intel_scu_ipc_iowrite8(MSIC_VPROG3_MRFLD_CTRL,
			       flag ? MSIC_VPROG3_MRFLD_ON_1_05 :
			       MSIC_VPROG_MRFLD_OFF);
		} else if (voltage == CAMERA_1_83_VOLT) {
			return intel_scu_ipc_iowrite8(MSIC_VPROG3_MRFLD_CTRL,
			       flag ? MSIC_VPROG3_MRFLD_ON_1_83 :
			       MSIC_VPROG_MRFLD_OFF);
		} else {
			pr_err("Error: Unsupported vprog3 voltage\n");
			return -ENODEV;
		}
	} else {
		pr_err("Error: vprog3 not supported\n");
		return -ENODEV;
	}
}
static __init int hsu_dev_platform_data(void)
{
	switch (intel_mid_identify_cpu()) {
	case INTEL_MID_CPU_CHIP_CLOVERVIEW:
		platform_hsu_info = &hsu_port_cfgs[hsu_clv][0];
		if (INTEL_MID_BOARD(2, PHONE, CLVTP, VB, PRO))
			hsu_port_gpio_mux =
				&hsu_port_pin_cfgs[hsu_clv][hsu_pid_vtb_pro][0];
		else if (INTEL_MID_BOARD(2, PHONE, CLVTP, VB, ENG))
			hsu_port_gpio_mux =
				&hsu_port_pin_cfgs[hsu_clv][hsu_pid_vtb_eng][0];
		else
			hsu_port_gpio_mux =
				&hsu_port_pin_cfgs[hsu_clv][hsu_pid_rhb][0];
		break;
	case INTEL_MID_CPU_CHIP_VALLEYVIEW2:
		platform_hsu_info = &hsu_port_cfgs[hsu_vlv2][0];
		hsu_port_gpio_mux =
			&hsu_port_pin_cfgs[hsu_vlv2][hsu_pid_def][0];
		break;

	case INTEL_MID_CPU_CHIP_TANGIER:
	case INTEL_MID_CPU_CHIP_ANNIEDALE:
		platform_hsu_info = &hsu_port_cfgs[hsu_tng][0];
		hsu_port_gpio_mux = &hsu_port_pin_cfgs[hsu_tng][hsu_pid_def][0];
		break;

	case INTEL_MID_CPU_CHIP_LINCROFT:
	case INTEL_MID_CPU_CHIP_PENWELL:
	default:
		platform_hsu_info = &hsu_port_cfgs[hsu_pnw][0];
		hsu_port_gpio_mux = &hsu_port_pin_cfgs[hsu_pnw][hsu_pid_def][0];
		break;
	}

	if (platform_hsu_info == NULL)
		return -ENODEV;

	if (hsu_port_gpio_mux == NULL)
		return -ENODEV;

	hsu_register_board_info(platform_hsu_info);
	hsu_platform_clk(intel_mid_identify_cpu());

	return 0;
}
static int imx175_power_ctrl(struct v4l2_subdev *sd, int flag)
{
	int ret = 0;

	if (flag) {
		if (!camera_vprog1_on) {
			if (intel_mid_identify_cpu() !=
			    INTEL_MID_CPU_CHIP_VALLEYVIEW2)
				ret = intel_scu_ipc_msic_vprog1(1);
#ifdef CONFIG_CRYSTAL_COVE
			/*
			 * This should call VRF APIs.
			 *
			 * VRF not implemented for BTY, so call this
			 * as WAs
			 */
			ret = camera_set_pmic_power(CAMERA_2P8V, true);
			if (ret)
				return ret;
			ret = camera_set_pmic_power(CAMERA_1P8V, true);
#endif
			if (!ret) {
				/* imx1x5 VDIG rise to XCLR release */
				usleep_range(1000, 1200);
				camera_vprog1_on = 1;
			}
			return ret;
		}
	} else {
		if (camera_vprog1_on) {
			if (intel_mid_identify_cpu() !=
			    INTEL_MID_CPU_CHIP_VALLEYVIEW2)
				ret = intel_scu_ipc_msic_vprog1(0);
#ifdef CONFIG_CRYSTAL_COVE
			ret = camera_set_pmic_power(CAMERA_2P8V, false);
			if (ret)
				return ret;
			ret = camera_set_pmic_power(CAMERA_1P8V, false);
#endif
			if (!ret)
				camera_vprog1_on = 0;
			return ret;
		}
	}
	return ret;
}
Esempio n. 15
0
int intel_scu_ipc_write_umip(u8 *data, int len, int offset)
{
	int ret, offset_align;
	int len_align = 0;
	u32 dptr, sptr, cmd;
	u8 *buf = NULL;

	/* Cloverview don't need UMIP access through IPC */
	if (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_CLOVERVIEW)
		return -EINVAL;

	if (!intel_mip_base)
		return -ENODEV;

	if (offset + len > IPC_MIP_MAX_ADDR)
		return -EINVAL;

	intel_scu_ipc_lock();

	offset_align = offset & (~0x3);
	len_align = (len + (offset - offset_align) + 3) & (~0x3);

	if (len != len_align) {
		buf = kzalloc(len_align, GFP_KERNEL);
		if (!buf) {
			pr_err("Alloc memory failed\n");
			ret = -ENOMEM;
			goto fail;
		}
		ret = read_mip(buf, len_align, offset_align, 0);
		if (ret)
			goto fail;
		memcpy(buf + offset - offset_align, data, len);
	} else {
		buf = data;
	}

	dptr = offset_align;
	sptr = len_align / 4;
	cmd = IPC_CMD_UMIP_WR << 12 | IPCMSG_MIP_ACCESS;

	memcpy(intel_mip_base, buf, len_align);

	do {
		ret = intel_scu_ipc_raw_cmd(cmd, 0, NULL, 0, NULL, 0,
				dptr, sptr);
		if (ret == -EIO)
			msleep(20);
	} while (ret == -EIO);

fail:
	if (buf && len_align != len)
		kfree(buf);

	intel_scu_ipc_unlock();

	return ret;
}
static int scu_mip_probe(struct platform_device *pdev)
{
	if (intel_mid_identify_cpu() != INTEL_MID_CPU_CHIP_PENWELL) {
		if (!pdev->dev.platform_data)
			return -EINVAL;
		pdata =
		(struct scu_mip_platform_data *)pdev->dev.platform_data;
	}
	return 0;
}
Esempio n. 17
0
static __init int add_rtc_cmos(void)
{
	int ret;

#ifdef CONFIG_PNP
	static const char * const  const ids[] __initconst =
	    { "PNP0b00", "PNP0b01", "PNP0b02", };
	struct pnp_dev *dev;
	struct pnp_id *id;
	int i;

	pnp_for_each_dev(dev) {
		for (id = dev->id; id; id = id->next) {
			for (i = 0; i < ARRAY_SIZE(ids); i++) {
				if (compare_pnp_id(id, ids[i]) != 0)
					return 0;
			}
		}
	}
#endif
	if (of_have_populated_dt())
		return 0;

	/* Intel MID platforms don't have ioport rtc
	 * except Tangier platform, which doesn't have vRTC
	 */
	if (intel_mid_identify_cpu() &&
	    intel_mid_identify_cpu() != INTEL_MID_CPU_CHIP_TANGIER)
		return -ENODEV;

	ret = handle_mrfl_dev_ioapic(RTC_IRQ);
	if (ret)
		return ret;

	platform_device_register(&rtc_device);
	dev_info(&rtc_device.dev,
		 "registered platform RTC device (no PNP device found)\n");

	return 0;
}
static int serial_hsu_pci_dma_probe(struct pci_dev *pdev,
				const struct pci_device_id *ent)
{
	struct hsu_dma_chan *dchan;
	int ret, share_irq = 0;
	resource_size_t start, len;

	start = pci_resource_start(pdev, 0);
	len = pci_resource_len(pdev, 0);

	dev_info(&pdev->dev,
		"FUNC: %d driver: %ld addr:%lx len:%lx\n",
		PCI_FUNC(pdev->devfn), ent->driver_data,
		(unsigned long) pci_resource_start(pdev, 0),
		(unsigned long) pci_resource_len(pdev, 0));

	ret = pci_enable_device(pdev);
	if (ret)
		return ret;

	ret = pci_request_region(pdev, 0, "hsu dma");
	if (ret)
		goto err;

	/* share irq with port? ANN all and TNG chip from B0 stepping */
	if ((intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_TANGIER &&
		pdev->revision >= 0x1) ||
		intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_ANNIEDALE)
		share_irq = 1;

	ret = serial_hsu_dma_setup(&pdev->dev, start, len, pdev->irq, share_irq);
	if (ret)
		goto err;

	return 0;
err:
	pci_disable_device(pdev);
	return ret;
}
static int imx175_gpio_ctrl(struct v4l2_subdev *sd, int flag)
{
	int ret;

	if (intel_mid_identify_cpu() != INTEL_MID_CPU_CHIP_VALLEYVIEW2) {
		if (camera_reset < 0) {
			ret = camera_sensor_gpio(-1, GP_CAMERA_0_RESET,
					GPIOF_DIR_OUT, 1);
			if (ret < 0)
				return ret;
			camera_reset = ret;
		}
	} else {
		/*
		 * FIXME: WA using hardcoded GPIO value here.
		 * The GPIO value would be provided by ACPI table, which is
		 * not implemented currently
		 */
		if (camera_reset < 0) {
			ret = gpio_request(CAMERA_0_RESET, "camera_0_reset");
			if (ret) {
				pr_err("%s: failed to request gpio(pin %d)\n",
				__func__, CAMERA_0_RESET);
				return -EINVAL;
			}
		}
		camera_reset = CAMERA_0_RESET;
		ret = gpio_direction_output(camera_reset, 1);
		if (ret) {
			pr_err("%s: failed to set gpio(pin %d) direction\n",
				__func__, camera_reset);
			gpio_free(camera_reset);
		}
	}
	if (flag) {
		gpio_set_value(camera_reset, 1);
		/* imx175 core silicon initializing time - t1+t2+t3
		 * 400us(t1) - Time to VDDL is supplied after REGEN high
		 * 600us(t2) - imx175 core Waking up time
		 * 459us(t3, 8825clocks) -Initializing time of silicon
		 */
		usleep_range(1500, 1600);

	} else {
		gpio_set_value(camera_reset, 0);
		/* 1us - Falling time of REGEN after XCLR H -> L */
		udelay(1);
	}

	return 0;
}
Esempio n. 20
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static int __init register_mid_wdt(void)
{
	if (intel_mid_identify_cpu() != INTEL_MID_CPU_CHIP_TANGIER)
		return -ENODEV;

	wdt_dev.dev.platform_data = &tangier_pdata;

	/*
	 * We need to be sure that the SCU IPC is ready before watchdog device
	 * can be registered:
	 */
	intel_scu_notifier_add(&wdt_scu_notifier);

	return 0;
}
Esempio n. 21
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static void atomisp_pci_shutdown(struct pci_dev *dev)
{
	struct atomisp_device *isp = (struct atomisp_device *)
		pci_get_drvdata(dev);

	if (IS_ISP2400 && atomisp_mrfld_pre_power_down(isp))
		return;

	/*Turn off the ISP d-phy*/
	if (atomisp_ospm_dphy_down(isp))
		return;

	pm_qos_update_request(&isp->pm_qos, PM_QOS_DEFAULT_VALUE);
	if (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_VALLEYVIEW2)
		pmu_nc_set_power_state(TNG_ISP_ISLAND, OSPM_ISLAND_DOWN,
					MRFLD_ISPSSPM0);
};
ssize_t Factory_UMIP_store(struct device *dev,
					struct device_attribute *attr,
					const char *buffer, size_t count)
{
	int ret = 0;
	u8 data_write;
	u8 yes;
	u8 no;
	bool bv;

	if (strlen(buffer) != 2) {
		pr_err("The length must be 1\n");
		ret = -EINVAL;
		goto error;
	}

	ret = strtobool(buffer, &bv);
	if (ret) {
		pr_err("Not expected value [Y|y|1|N|n|0]\n");
		goto error;
	}

	if (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_PENWELL) {
		ret = intel_scu_ipc_read_mip(&data_write,
						1,
						FACTORY_UMIP_OFFSET,
						0);
		data_write &= ~(1 << FACTORY_BIT_OFFSET);
		data_write |= bv;

		ret = intel_scu_ipc_write_umip(&data_write,
						1,
						FACTORY_UMIP_OFFSET);

		if (ret) {
			pr_err("Could not write to UMIP for Factory\n");
			goto error;
		}
	}

	return count;

error:
	return ret;
}
Esempio n. 23
0
/*
 * Checking the SOC type is temporary workaround to enable OV8830
 * on Bodegabay (tangier) platform. Once standard regulator devices
 * (e.g. vprog1, vprog2) and control functions (pmic_avp) are added
 * for the platforms with tangier, then we can revert this change.
 * ([email protected])
 */
static int ov8830_platform_init(struct i2c_client *client)
{
	int ret;
	if (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_TANGIER)
		return 0;

	vprog1_reg = regulator_get(&client->dev, "vprog1");
	if (IS_ERR(vprog1_reg)) {
		dev_err(&client->dev, "regulator_get failed\n");
		return PTR_ERR(vprog1_reg);
	}
	ret = regulator_set_voltage(vprog1_reg, VPROG1_VAL, VPROG1_VAL);
	if (ret) {
		dev_err(&client->dev, "regulator voltage set failed\n");
		regulator_put(vprog1_reg);
	}
	return ret;
}
static int imx175_flisclk_ctrl(struct v4l2_subdev *sd, int flag)
{
	static const unsigned int clock_khz = 19200;
#ifdef CONFIG_VLV2_PLAT_CLK
	if (flag) {
		int ret;
		ret = vlv2_plat_set_clock_freq(OSC_CAM0_CLK, CLK_19P2MHz);
		if (ret)
			return ret;
	}
	return vlv2_plat_configure_clock(OSC_CAM0_CLK, flag);
#endif
	if (intel_mid_identify_cpu() != INTEL_MID_CPU_CHIP_VALLEYVIEW2)
		return intel_scu_ipc_osc_clk(OSC_CLK_CAM0,
			flag ? clock_khz : 0);
	else
		return 0;
}
int mcd_get_cpu_ver(void)
{
	enum intel_mid_cpu_type mid_cpu = intel_mid_identify_cpu();

	switch (mid_cpu) {
	case INTEL_MID_CPU_CHIP_PENWELL:
		return CPU_PWELL;
	case INTEL_MID_CPU_CHIP_CLOVERVIEW:
		return CPU_CLVIEW;
	case INTEL_MID_CPU_CHIP_TANGIER:
		return CPU_TANGIER;
	case INTEL_MID_CPU_CHIP_ANNIEDALE:
		return CPU_ANNIEDALE;
	default:
		return CPU_UNSUP;
	}
	return CPU_UNSUP;
}
Esempio n. 26
0
static int atomisp_suspend(struct device *dev)
{
	struct atomisp_device *isp = (struct atomisp_device *)
		dev_get_drvdata(dev);
	unsigned long flags;
	int ret;
	/* FIXME: currently only use subdev[0] in single stream mode */
	struct atomisp_sub_device *isp_subdev = &isp->isp_subdev[0];

	/*
	 * FIXME: Suspend is not supported by sensors. Abort if any video
	 * node was opened.
	 */
	if (atomisp_dev_users(isp))
		return -EBUSY;

	spin_lock_irqsave(&isp->lock, flags);
	if (isp_subdev->streaming != ATOMISP_DEVICE_STREAMING_DISABLED) {
		spin_unlock_irqrestore(&isp->lock, flags);
		v4l2_err(&atomisp_dev,
			    "atomisp cannot suspend at this time.\n");
		return -EINVAL;
	}
	spin_unlock_irqrestore(&isp->lock, flags);

	/* Prepare for MRFLD IUNIT power down */
	if (IS_ISP2400) {
		ret = atomisp_mrfld_pre_power_down(isp);
		if (ret)
			return ret;
	}

	/*Turn off the ISP d-phy */
	ret = atomisp_ospm_dphy_down(isp);
	if (ret) {
		dev_err(isp->dev, "fail to power off ISP\n");
		return ret;
	}
	pm_qos_update_request(&isp->pm_qos, PM_QOS_DEFAULT_VALUE);
	if (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_VALLEYVIEW2)
		ret = pmu_nc_set_power_state(TNG_ISP_ISLAND, OSPM_ISLAND_DOWN,
					MRFLD_ISPSSPM0);
	return ret;
}
static int ov5670_flisclk_ctrl(struct v4l2_subdev *sd, int flag)
{
	static const unsigned int clock_khz = 19200;

#ifdef CONFIG_INTEL_SOC_PMC
	if (flag) {
		int ret;
		ret = pmc_pc_set_freq(OSC_CAM0_CLK, CLK_19P2MHz);
		if (ret)
			return ret;
	}
	return pmc_pc_configure(OSC_CAM0_CLK, flag);
#endif
	if (intel_mid_identify_cpu() != INTEL_MID_CPU_CHIP_VALLEYVIEW2)
		return intel_scu_ipc_osc_clk(OSC_CLK_CAM0,
			flag ? clock_khz : 0);
	else
		return 0;
}
static ssize_t factory_umip_show(struct device *dev,
				struct device_attribute *attr, char *buffer)
{
	int ret;
	u8 data_read;

	if (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_PENWELL) {
		ret = intel_scu_ipc_read_mip(&data_read,
						1,
						FACTORY_UMIP_OFFSET,
						0);
		if (ret) {
			pr_err("Could not read to UMIP for Factory\n");
			return -EBUSY;
		}

		return sprintf(buffer, "%d\n",
				(data_read >> FACTORY_BIT_OFFSET) & 0x01);
	} else {
/* Register the RTC device if appropriate */
static int __init intel_mid_device_create(void)
{
	/* No Moorestown, no device */
	if (!intel_mid_identify_cpu())
		return -ENODEV;
	/* No timer, no device */
	if (!sfi_mrtc_num)
		return -ENODEV;

	/* iomem resource */
	vrtc_resources[0].start = sfi_mrtc_array[0].phys_addr;
	vrtc_resources[0].end = sfi_mrtc_array[0].phys_addr +
				MRST_VRTC_MAP_SZ;
	/* irq resource */
	vrtc_resources[1].start = sfi_mrtc_array[0].irq;
	vrtc_resources[1].end = sfi_mrtc_array[0].irq;

	return platform_device_register(&vrtc_device);
}
Esempio n. 30
0
File: rtc.c Progetto: 020gzh/linux
static __init int add_rtc_cmos(void)
{
#ifdef CONFIG_PNP
	static const char * const ids[] __initconst =
	    { "PNP0b00", "PNP0b01", "PNP0b02", };
	struct pnp_dev *dev;
	struct pnp_id *id;
	int i;

	pnp_for_each_dev(dev) {
		for (id = dev->id; id; id = id->next) {
			for (i = 0; i < ARRAY_SIZE(ids); i++) {
				if (compare_pnp_id(id, ids[i]) != 0)
					return 0;
			}
		}
	}
#endif
	if (of_have_populated_dt())
		return 0;

	/* Intel MID platforms don't have ioport rtc */
	if (intel_mid_identify_cpu())
		return -ENODEV;

#ifdef CONFIG_ACPI
	if (acpi_gbl_FADT.boot_flags & ACPI_FADT_NO_CMOS_RTC) {
		/* This warning can likely go away again in a year or two. */
		pr_info("ACPI: not registering RTC platform device\n");
		return -ENODEV;
	}
#endif

	if (paravirt_enabled() && !paravirt_has(RTC))
		return -ENODEV;

	platform_device_register(&rtc_device);
	dev_info(&rtc_device.dev,
		 "registered platform RTC device (no PNP device found)\n");

	return 0;
}