void task_signal(Task *task, Signal signal)
{
/* Set destionation signal. Unblock the task if the target
signal is in mask. */
interrupts_disable();
task_line("");
log_hex(signal);
log_string(" --> ");
log_string(task->name);
log_string(" {mask=");
log_hex(task->sig_mask);
log_string(", rec=");
log_hex(task->sig_rec);
log_string("} ==> rec=");
task->sig_rec |= signal;
log_hex(task->sig_rec);
if (task->sig_mask & signal) {
log_string(", unblock, prio:");
list_remove_node((Node *) task);
list_enqueue(&ready_tasks, (Node *) task);
if (running_task->node.ln_pri < task->node.ln_pri) {
log_string("hi");
port_reschedule();
} else {
/* An unneeded context switch is optimized away. */
log_string("lo");
interrupts_enable();
}
} else {
log_string(", no unblock.");
interrupts_enable();
}
}
void _kmain(struct multiboot_info *mboot) {
clrscr();
// This will make sure there's about 4K of space for malloc to use until physical
// memory management is available for proper virtual memory.
kprintf("Initialising malloc()...\n");
dlmalloc_sbrk(0);
kprintf("Initialising physical memory manager...\n");
pmem_init(mboot);
kprintf("Completing virtual memory initialisation...\n");
vmem_init();
kprintf("Configuring software and hardware interrupts...\n");
interrupts_init();
kprintf("Initialising machine devices...\n");
init_devices();
kprintf("Enabling interrupts...\n");
interrupts_enable();
kprintf("Startup complete!\n");
while(1) __asm__ volatile("hlt");
}
int main(void)
{
// Enable peripherals
system_init();
pins_init();
us1_init();
us0_init();
twi_init();
// Initialize state machines
qcfp_init();
eq_init();
// Once everything is initialized, enable interrupts globally
interrupts_enable();
// Enable Expansion module 3 and 4 (sensors plugged into these temporarily)
AT91C_BASE_PIOA->PIO_CODR = AT91C_PIO_PA20;
AT91C_BASE_PIOA->PIO_CODR = AT91C_PIO_PA23;
sensors_init();
eq_post_timer(gpio_led_dance, 250, eq_timer_periodic);
while(1)
{
eq_dispatch();
eq_dispatch_timers();
}
return 0;
}
int
uart_put_byte(U32 u, U8 b)
{
int ret_val;
int i_state;
struct soft_uart *p;
volatile struct _AT91S_USART *up;
if (u >= N_UARTS)
return -1;
p = &uart[u];
up = p->uart;
i_state = interrupts_get_and_disable();
#ifndef UART_POLLED
ret_val = byte_fifo_put(&p->tx, 0, b);
/* Enable transmitting and the transmit interrupt.
* This will allow the UART tx chain to wake up and
* pick up the next byte for tx, if it was stopped.
*/
p->transmitting = 1;
up->US_IER = 0x02;
#else
# warning Polled UART not supported!
#endif
if (i_state)
interrupts_enable();
return ret_val;
}
void
nxt_spi_init(void)
{
int i_state = interrupts_get_and_disable();
#define SPI_BITRATE 2000000
*AT91C_PMC_PCER = (1L << AT91C_ID_SPI); /* Enable MCK clock */
*AT91C_PIOA_PER = AT91C_PIO_PA12;/*EnableA0onPA12*/
*AT91C_PIOA_OER = AT91C_PIO_PA12;
*AT91C_PIOA_CODR = AT91C_PIO_PA12;
*AT91C_PIOA_PDR = AT91C_PA14_SPCK;/*EnableSPCKonPA14*/
*AT91C_PIOA_ASR = AT91C_PA14_SPCK;
*AT91C_PIOA_ODR = AT91C_PA14_SPCK;
*AT91C_PIOA_OWER = AT91C_PA14_SPCK;
*AT91C_PIOA_MDDR = AT91C_PA14_SPCK;
*AT91C_PIOA_PPUDR = AT91C_PA14_SPCK;
*AT91C_PIOA_IFDR = AT91C_PA14_SPCK;
*AT91C_PIOA_CODR = AT91C_PA14_SPCK;
*AT91C_PIOA_IDR = AT91C_PA14_SPCK;
*AT91C_PIOA_PDR = AT91C_PA13_MOSI;/*EnablemosionPA13*/
*AT91C_PIOA_ASR = AT91C_PA13_MOSI;
*AT91C_PIOA_ODR = AT91C_PA13_MOSI;
*AT91C_PIOA_OWER = AT91C_PA13_MOSI;
*AT91C_PIOA_MDDR = AT91C_PA13_MOSI;
*AT91C_PIOA_PPUDR = AT91C_PA13_MOSI;
*AT91C_PIOA_IFDR = AT91C_PA13_MOSI;
*AT91C_PIOA_CODR = AT91C_PA13_MOSI;
*AT91C_PIOA_IDR = AT91C_PA13_MOSI;
*AT91C_PIOA_PDR = AT91C_PA10_NPCS2;/*Enablenpcs0onPA10*/
*AT91C_PIOA_BSR = AT91C_PA10_NPCS2;
*AT91C_PIOA_ODR = AT91C_PA10_NPCS2;
*AT91C_PIOA_OWER = AT91C_PA10_NPCS2;
*AT91C_PIOA_MDDR = AT91C_PA10_NPCS2;
*AT91C_PIOA_PPUDR = AT91C_PA10_NPCS2;
*AT91C_PIOA_IFDR = AT91C_PA10_NPCS2;
*AT91C_PIOA_CODR = AT91C_PA10_NPCS2;
*AT91C_PIOA_IDR = AT91C_PA10_NPCS2;
*AT91C_SPI_CR = AT91C_SPI_SWRST;/*Softreset*/
*AT91C_SPI_CR = AT91C_SPI_SPIEN;/*Enablespi*/
*AT91C_SPI_MR = AT91C_SPI_MSTR|AT91C_SPI_MODFDIS | (0xB<<16);
AT91C_SPI_CSR[2] = ((CLOCK_FREQUENCY/SPI_BITRATE)<<8) | AT91C_SPI_CPOL;
/* Set mode to unknown */
mode = 0xff;
/* Set up safe dma refresh state */
data = display = (U8 *) 0;
dirty = 0;
page = 0;
/* Install the interrupt handler */
aic_mask_off(AT91C_ID_SPI);
aic_set_vector(AT91C_ID_SPI, AIC_INT_LEVEL_NORMAL, spi_isr_entry);
aic_mask_on(AT91C_ID_SPI);
*AT91C_SPI_PTCR = AT91C_PDC_TXTEN;
if (i_state)
interrupts_enable();
}
int
uart_get_byte(U32 u, U8 *b)
{
int ret_val;
int i_state;
struct soft_uart *p;
volatile struct _AT91S_USART *up;
if (u >= N_UARTS)
return -1;
p = &uart[u];
up = p->uart;
i_state = interrupts_get_and_disable();
#ifndef UART_POLLED
ret_val = byte_fifo_get(&p->rx, b);
#else
#endif
if (i_state)
interrupts_enable();
return ret_val;
}
void
systick_init(void)
{
int i_state = interrupts_get_and_disable();
aic_mask_off(LOW_PRIORITY_IRQ);
aic_set_vector(LOW_PRIORITY_IRQ, (1 << 5) /* positive internal edge */ |
AIC_INT_LEVEL_LOW, (U32) tpl_primary_irq_handler);// (U32) systick_low_priority_entry);
aic_mask_on(LOW_PRIORITY_IRQ);
aic_mask_off(AT91C_PERIPHERAL_ID_SYSIRQ);
aic_set_vector(AT91C_PERIPHERAL_ID_SYSIRQ, (1 << 5) /* positive internal edge */ |
AIC_INT_LEVEL_NORMAL, (U32) tpl_primary_irq_handler);//(U32) systick_isr_entry);
aic_mask_on(AT91C_PERIPHERAL_ID_SYSIRQ);
*AT91C_PITC_PIMR = ((CLOCK_FREQUENCY / 16 / PIT_FREQ) - 1) | 0x03000000; /* Enable, enable interrupts */
if (i_state)
interrupts_enable();
}
// Initialise the module
void
i2c_init(void)
{
int i;
int istate;
U32 dummy;
for (i = 0; i < I2C_N_PORTS; i++) {
i2c_ports[i] = NULL;
}
istate = interrupts_get_and_disable();
/* Set up Timer Counter 0 */
*AT91C_PMC_PCER = (1 << AT91C_ID_TC0); /* Power enable */
*AT91C_TC0_CCR = AT91C_TC_CLKDIS; /* Disable */
*AT91C_TC0_IDR = ~0;
dummy = *AT91C_TC0_SR;
*AT91C_TC0_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK|AT91C_TC_CPCTRG; /* MCLK/2, RC compare trigger */
*AT91C_TC0_RC = (CLOCK_FREQUENCY/2)/(2 * I2C_CLOCK);
*AT91C_TC0_IER = AT91C_TC_CPCS;
aic_mask_off(AT91C_ID_TC0);
aic_set_vector(AT91C_ID_TC0, AIC_INT_LEVEL_NORMAL, (int)i2c_timer_isr_entry);
aic_mask_on(AT91C_ID_TC0);
if(istate)
interrupts_enable();
}
nrfx_err_t nrfx_uarte_init(nrfx_uarte_t const * p_instance,
nrfx_uarte_config_t const * p_config,
nrfx_uarte_event_handler_t event_handler)
{
NRFX_ASSERT(p_config);
uarte_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
nrfx_err_t err_code = NRFX_SUCCESS;
if (p_cb->state != NRFX_DRV_STATE_UNINITIALIZED)
{
err_code = NRFX_ERROR_INVALID_STATE;
NRFX_LOG_WARNING("Function: %s, error code: %s.",
__func__,
NRFX_LOG_ERROR_STRING_GET(err_code));
return err_code;
}
#if NRFX_CHECK(NRFX_PRS_ENABLED)
static nrfx_irq_handler_t const irq_handlers[NRFX_UARTE_ENABLED_COUNT] = {
#if NRFX_CHECK(NRFX_UARTE0_ENABLED)
nrfx_uarte_0_irq_handler,
#endif
#if NRFX_CHECK(NRFX_UARTE1_ENABLED)
nrfx_uarte_1_irq_handler,
#endif
};
if (nrfx_prs_acquire(p_instance->p_reg,
irq_handlers[p_instance->drv_inst_idx]) != NRFX_SUCCESS)
{
err_code = NRFX_ERROR_BUSY;
NRFX_LOG_WARNING("Function: %s, error code: %s.",
__func__,
NRFX_LOG_ERROR_STRING_GET(err_code));
return err_code;
}
#endif // NRFX_CHECK(NRFX_PRS_ENABLED)
apply_config(p_instance, p_config);
p_cb->handler = event_handler;
p_cb->p_context = p_config->p_context;
if (p_cb->handler)
{
interrupts_enable(p_instance, p_config->interrupt_priority);
}
nrf_uarte_enable(p_instance->p_reg);
p_cb->rx_buffer_length = 0;
p_cb->rx_secondary_buffer_length = 0;
p_cb->tx_buffer_length = 0;
p_cb->state = NRFX_DRV_STATE_INITIALIZED;
NRFX_LOG_WARNING("Function: %s, error code: %s.",
__func__,
NRFX_LOG_ERROR_STRING_GET(err_code));
return err_code;
}
static inline void display_unhandled_pf_info(struct fault_ctx *fctx,
uintptr_t fault_addr)
{
interrupts_disable();
fault_describe("PAGE FAULT", fctx);
kprintf_fault(" Invalid address: %p, RIP: %p\n",
fault_addr, fctx->istack_frame->rip);
fault_dump_info(fctx);
interrupts_enable();
}
void *sched_ap_idle_thread (void *notused)
{
interrupts_disable();
lapic_common_init();
interrupts_enable();
thread_create_test();
cpu_heart_beat(this_cpu());
}
void
flash_write(U32 addr, void *buffer, U32 nBytes)
{
int i = 0;
int istate = interrupts_get_and_disable();
while (nBytes--) {
i++;
}
if (istate)
interrupts_enable();
}
void
flash_erase_range(U32 addr, U32 nBytes)
{
int i = 0;
int istate = interrupts_get_and_disable();
while (nBytes--) {
i++;
}
if (istate)
interrupts_enable();
}
INITCODE void arch_smp_init(void)
{
cpu_id_t c;
uint32_t *lapic_id;
char *ap_code = (char *)0x9000;
size_t size = &ap_boot_end - &ap_boot_start;
struct ap_config *apcfg;
/* FIXME DK: real-mode page must be reserved dynamically during mm initialization. */
apcfg = (struct ap_config *)&ap_config;
apcfg->page_addr = 0x9000;
apcfg->jmp_rip = (uint32_t)((uint64_t)smp_start32 & 0xffffffffU);
apcfg->gdtr.base += apcfg->page_addr;
memcpy(&apcfg->gdt[APGDT_KCOFF_DESCR], &apcfg->gdt[APGDT_KCNORM_DESCR],
sizeof(uint64_t));
apcfg->gdt[APGDT_KCOFF_DESCR] |= (uint64_t)apcfg->page_addr << 16;
/* Change bootstrap entry point (from kernel_main to main_smpap_routine) */
*(uint64_t *)&kernel_jump_addr = (uint64_t)main_smpap_routine;
/* And finally copy AP initialization code to the proper place */
memcpy(ap_code, &ap_boot_start, size);
/* ok setup new gdt */
for_each_cpu(c) {
int r;
if (!c) {
continue; /* Skip BSP CPU */
}
lapic_id = raw_percpu_get_var(lapic_ids, c);
kprintf("SEND INIT IPI TO CPU %d, cpuid=%d\n", *lapic_id, c);
if (lapic_init_ipi(*lapic_id)) {
panic("Can't send init interrupt\n");
}
interrupts_disable();
for (r = 0; r < 100; r++) {
default_hwclock->delay(1000);
if (is_cpu_online(c)) {
kprintf("online!\n");
break;
}
}
interrupts_enable();
if (!is_cpu_online(c)) {
kprintf("f**k! => %d\n", is_cpu_online(c));
for (;;);
panic("CPU %d is not online\n", c);
}
}
}
/**
* Write a page from the supplied flash buffer to flash memory
* The flash buffer must have been obtained through a call to
* flash_get_page_buffer, before making this call
* returns > 0 number of bytes written < 0 error
* Error returns:
* -1 Timeout waiting for TWI to complete
* -2 Timeout waiting for flash write to complete
* -3 Bad page number
* -4 bad flash buffer
*/
int
flash_write_page_buffer(FOURBYTES *page, int page_num)
{
/* Write page to flash memory.
* This function must run out of ram and while it executes no other code
* (especially any flash resident) code must run. This is becuase the
* flash memory is only a single plane and can not be accessed for both read
* and write at the same time.
*/
int istate;
int status;
if (page_num + flash_start_page >= FLASH_MAX_PAGES) return -3;
if (VINTPTR(page) != &(FLASH_BASE[page_num*FLASH_PAGE_SIZE])) return -4;
/* We must disbale interrupts. However we need to try and ensure that all
* current interrupt activity is complete before we do that. We talk to
* the avr every 1ms and this uses interrupt driven I/O so we try to make
* sure this is complete.
*/
// Allow any playing sound to complete
sound_wait();
// Turn off timer tick call backs
systick_suspend();
// Wait until next tick
systick_wait_ms(1);
// Force a tick to talk to the avr
nxt_avr_1kHz_update();
// Wait for it to complete
status = wait_twi_complete();
if (status != 0) return -1;
// Now we can turn off all ints
istate = interrupts_get_and_disable();
// Write the buffer to the selected page
status = flash_write(page_num + flash_start_page);
// Turn ints back on
if (istate) interrupts_enable();
// Ensure that we are back in-sync.
systick_wait_ms(1);
// Allow call backs on 1ms tick
systick_resume();
if (!(status & AT91C_MC_FRDY)) return -2;
return FLASH_PAGE_SIZE*sizeof(U32);
}
void interrupts_init(void) {
uint16_t i;
if (initialized == 0) {
interrupts_disable();
InitIrqLevels();
for (i = 0; i < 100; i++) {
ivt[i] = *((IRQHandler*) (0xFFFC00ul + 0x270ul + i * 4ul));
}
TBR = ((long) (&ivt[0]) & 0xfffc00l) >> 8;
initialized = 1;
interrupts_enable();
}
static void __get_timer_status(posix_timer_t *ptimer,itimerspec_t *kspec)
{
ktimer_t *timer=&ptimer->ktimer;
ticks_to_time(&kspec->it_interval,ptimer->interval);
/* We disable interrupts to prevent us from being preempted, and,
* therefore, from calculating wrong time delta.
*/
interrupts_disable();
if( timer->time_x > system_ticks ) {
ticks_to_time(&kspec->it_value,timer->time_x - system_ticks);
} else {
kspec->it_value.tv_sec=kspec->it_value.tv_nsec=0;
}
interrupts_enable();
}
/* This one get's called from the architecture-specific interrupt
* handlers, which do fiddling like EOIs (i386).
*/
isf_t* __attribute__((fastcall)) interrupts_callback(uint32_t intr, isf_t* regs) {
struct interrupt_reg reg = interrupt_handlers[intr];
task_t* task = scheduler_get_current();
#ifdef INTERRUPTS_DEBUG
debug("state before:\n");
dump_isf(LOG_DEBUG, regs);
#endif
if(reg.handler) {
if(reg.can_reent) {
interrupts_enable();
}
reg.handler(regs);
}
#ifdef ENABLE_PICOTCP
if(intr == IRQ(0)) {
net_tick();
}
#endif
// Run scheduler every 100th tick, or when task yields
if((intr == IRQ(0) && !(timer_get_tick() % 100)) || (task && task->interrupt_yield)) {
if((task && task->interrupt_yield)) {
task->interrupt_yield = false;
}
task_t* new_task = scheduler_select(regs);
if(new_task && new_task->state) {
#ifdef INTERRUPTS_DEBUG
debug("state after (task selection):\n");
dump_isf(LOG_DEBUG, new_task->state);
#endif
gdt_set_tss(new_task->kernel_stack + PAGE_SIZE);
return new_task->state;
}
}
#ifdef INTERRUPTS_DEBUG
debug("state after:\n");
dump_isf(LOG_DEBUG, regs);
#endif
return regs;
}
int main(void)
{
system_init();
led_init();
button_init();
interrupts_configure();
interrupts_enable();
led_on(LED_RED);
led_off(LED_GREEN);
// config timer A to toggle leds
timer_init(TIMER_A, TIMER_SRC_SMCLK, TIMER_DIV_8, TIMER_COUNT_UP);
timer_match_enable(TIMER_A, 32000, test_toggle);
while (1) {;}
return 0;
}
int kmain(void* UNUSED(mbd), unsigned int UNUSED(magic))
{
cpu_init(); //set up GDT
idt_install(); //set up IDT
interrupts_init(); //set up callback table
pic_init(); //set up PIC
print_clear();
print_string_static("Hello... I'm a C Kernel!1!!\nAnd I have a PIC and PIT intialized.\n");
interrupts_enable();
interrupts_registerHandler(IRQ_TIMER, timerHandler);
pit_init(50);
pic_unmask_irq(IRQ_TIMER);
for(;;);
return 0;
}
/* Why are satisfied signal bits cleared? Because there is no
need to clear it manually afterwards then. */
Signal task_wait(Signal mask)
{
Signal ret;
interrupts_disable();
task_line("{mask=");
log_hex(mask);
log_string(", rec=");
log_hex(running_task->sig_rec);
log_string("} ==> ");
if (!(mask & running_task->sig_rec)) {
running_task->sig_mask = mask;
list_remove_node((Node *) running_task);
list_enqueue(&waiting_tasks, (Node *) running_task);
log_string("blocked...");
port_reschedule();
/* Interrupts may occur here. */
interrupts_disable();
task_line("...unblocked ");
log_string("{mask=");
log_hex(mask);
log_string("(");
log_hex(running_task->sig_mask);
log_string(")");
log_string(", rec=");
log_hex(running_task->sig_rec);
log_string("} ==> ");
}
ret = running_task->sig_rec & mask;
running_task->sig_rec &= ~mask;
running_task->sig_mask = 0;
log_string("{rec=");
log_hex(running_task->sig_rec);
log_string("}, return ");
log_hex(ret);
interrupts_enable();
return ret;
}
void
init_rtc (void)
{
struct tm tim;
intr_install_handler (8, do_rtc);
interrupts_disable (); /* --------------- */
/* x : update in progress bit
* xxx : leave alone: 0b010 means 32768Hz
* xxxx : 32768Hz >> (0bxxxx - 1), defaults to: 0b0110, 1024Hz
* Defaults are good enough: */
/* rtc_write (0xa, 0b); */
/* x : PIE: periodic interrupt enable
* xxx : alarm, update-ended interrupt, square wave
* x : binary mode (1) or bcd (0)
* x : 24 hour format (1) or 12 (0)
* x : daylight savings enable
*/
rtc_write (0xb, rtc_read (0xb) | 0b1000110);
interrupts_enable (); /* --------------- */
/* FIXME: It takes some time to have effect.. ¿? */
msleep (500);
rtc_get_tm (&tim);
/* The int handler is already running, this should overwrite it */
unixtime = mktime (&tim);
/* TODO: zero pad this... */
kprintf ("System clock set to: %d-%d-%d %d:%d:%d (unix: %lld)\n",
tim.tm_year, tim.tm_mon, tim.tm_mday, tim.tm_hour, tim.tm_min,
tim.tm_sec, unixtime);
return;
}
// Add new task to schedule.
void scheduler_add(task_t *task)
{
interrupts_disable();
// No task yet?
if(currentTask == NULL)
{
currentTask = task;
task->next = task;
task->last = task;
} else {
task->next = currentTask->next;
task->last = currentTask;
currentTask->next = task;
}
interrupts_enable();
log(LOG_INFO, "scheduler: Registered new task with PID %d <%s>\n", task->pid, task->name);
}
void *sched_bsp_idle_thread (void *notused)
{
interrupts_disable();
clockeventer_subsystem_init();
pit_timer_init();
lapic_bsp_pre_init();
pci_init();
rtc_init();
keyboard_init();
lapic_common_init();
#ifdef CONFIG_ACPICA
acpica_sub_system_init ();
pci_scan_devices();
#endif
clockcounter_subsystem_init();
timerchain_subsystem_init();
real_wall_time_init();
tick_eventer_init();
lapic_bsp_post_init();
interrupts_enable();
thread_create_test();
lapic_ipi(1, 0, INTR_LAPIC_RESCHEDULE);
cpu_heart_beat(this_cpu());
}
void kernel_main(uint32_t arg)
{
volatile int gdb = 1;
serial_init();
printf(" | ___| \n");
printf(" __| _ \\ | _ \\ __ \\ \n");
printf("\\__ \\ ( | | ( | ) | \n");
printf("____/\\___/ _|\\___/____/ \n");
if (!gdb) printk("looping for gdb\n");
while ( gdb == 0 );
/* needs to be very early as it clears the bss */
mem_init((struct multiboot_info *)((uint64_t)arg));
interrupts_init();
/* ocaml needs floating point */
sse_enable();
time_init();
pci_enumerate();
interrupts_enable();
#if 0
gdb = 0;
gdb = 10/gdb;
#endif
blk_test();
sleep_test();
for(;;)
ping_serve(); /* does things if network packet comes in */
printf("Kernel done. \nGoodbye!\n");
kernel_hang();
}
int
flash_write_page(int start_page, U32 *page, int page_num)
{
int i, istate;
int status;
if (page_num + start_page > 1023) return 0;
systick_suspend();
systick_wait_ms(1);
nxt_avr_1kHz_update();
// modified based on the latest leJOS source (April 16th takashic)
// Wait for it to complete
status = wait_twi_complete();
if (status != 0) return -1;
// Now we can turn off all ints
istate = interrupts_get_and_disable();
for (i = 0; i < 64; i++)
FLASH_BASE[(page_num*64)+i] = page[i];
FLASH_CMD_REG = (0x5A000001 + (((page_num + start_page) & 0x000003FF) << 8));
status = wait_flash_ready();
// modified based on the latest leJOS source (April 16th takashic)
// Turn ints back on
if (istate) interrupts_enable();
// Ensure that we are back in-sync.
systick_wait_ms(1);
// Allow call backs on 1ms tick
systick_resume();
if (!(status & AT91C_MC_FRDY)) return -1;
return 1;
}
/*
* Return current RTC time. Note that due to waiting for the update cycle to
* complete, this call may take some time.
*/
static uint64_t rtc_gettimeofday(void) {
struct bmk_clock_ymdhms dt;
interrupts_disable();
/*
* If RTC_UIP is down, we have at least 244us to obtain a
* consistent reading before an update can occur.
*/
while (rtc_read(RTC_STATUS_A) & RTC_UIP)
continue;
dt.dt_sec = bcdtobin(rtc_read(RTC_SEC));
dt.dt_min = bcdtobin(rtc_read(RTC_MIN));
dt.dt_hour = bcdtobin(rtc_read(RTC_HOUR));
dt.dt_day = bcdtobin(rtc_read(RTC_DAY));
dt.dt_mon = bcdtobin(rtc_read(RTC_MONTH));
dt.dt_year = bcdtobin(rtc_read(RTC_YEAR)) + 2000;
interrupts_enable();
return clock_ymdhms_to_secs(&dt) * NSEC_PER_SEC;
}
/*
* Adds length bytes from buffer to the transmit circular buffer associated
* with the US1 interface. This function relies on the fact that it is the
* only function to *add* bytes to the buffer. Which this function is in
* progress, bytes may be removed, but not added. This function does not
* update the size field of the buffer until after all bytes have been added
* to minimize the number of times interrupts must be disabled.
*/
us1_error_t us1_send_buffer(uint8_t buffer[], uint16_t length)
{
us1_error_t ret_val = US1_SUCCESS;
uint16_t bytes_added = 0;
if((tx_circular_buffer.size + length) < tx_circular_buffer.capacity)
{
while(bytes_added != length)
{
cb_add_byte(&tx_circular_buffer, buffer[bytes_added++]);
}
// Update the number of bytes in the circular buffer
interrupts_disable();
tx_circular_buffer.size += length;
us1_kickstart_tx();
interrupts_enable();
}
else
{
ret_val = US1_NOT_ENOUGH_ROOM;
}
return ret_val;
}
void __do_handle_fault(void *rsp, enum fault_idx fault_num)
{
struct fault_ctx fctx;
if (unlikely((fault_num < MIN_FAULT_IDX) ||
(fault_num > MAX_FAULT_IDX))) {
panic("Unexpected fault number: %d. Expected fault indices in "
"range [%d, %d]", fault_num, MIN_FAULT_IDX, MAX_FAULT_IDX);
}
fill_fault_context(&fctx, rsp, fault_num);
/*
* On the momnet we jumped here from low level faults handling function
* interrupts are disabled. We should enable interrupts if and only
* if they were *enabled* before fault occured.
*/
if (fctx.istack_frame->rflags & RFLAGS_IF) {
interrupts_enable();
}
fault_handlers[fault_num](&fctx);
}
void
force_reset()
{
// reset the UDP connection.
int i_state;
// Take the hardware off line
*AT91C_PIOA_PER = (1 << 16);
*AT91C_PIOA_OER = (1 << 16);
*AT91C_PIOA_SODR = (1 << 16);
*AT91C_PMC_SCDR = AT91C_PMC_UDP;
*AT91C_PMC_PCDR = (1 << AT91C_ID_UDP);
systick_wait_ms(2);
// now bring it back online
i_state = interrupts_get_and_disable();
/* Make sure the USB PLL and clock are set up */
*AT91C_CKGR_PLLR |= AT91C_CKGR_USBDIV_1;
*AT91C_PMC_SCER = AT91C_PMC_UDP;
*AT91C_PMC_PCER = (1 << AT91C_ID_UDP);
*AT91C_UDP_FADDR = 0;
*AT91C_UDP_GLBSTATE = 0;
/* Enable the UDP pull up by outputting a zero on PA.16 */
*AT91C_PIOA_PER = (1 << 16);
*AT91C_PIOA_OER = (1 << 16);
*AT91C_PIOA_CODR = (1 << 16);
*AT91C_UDP_IDR = ~0;
/* Set up default state */
reset();
*AT91C_UDP_IER = (AT91C_UDP_EPINT0 | AT91C_UDP_RXSUSP | AT91C_UDP_RXRSM);
if (i_state)
interrupts_enable();
}