void
return_store_ack(struct pcx_pkt *pcx_pkt,
struct cpx_pkt *cpx_pkt,
taddr_opt_t t1_addr,
uint_t preinit_ctrl_flag,
int inv_flag)
{
int way;
int pabit5, pabit54;
int core_id;
core_id = PCX_PKT_GET_CORE_ID(pcx_pkt);
CPX_PKT_CTRL_STORE_ACK(cpx_pkt, preinit_ctrl_flag);
cpx_pkt->data3 = 0;
cpx_pkt->data2 = 0;
cpx_pkt->data1 = 0;
cpx_pkt->data0 = 0;
if (inv_flag != INVALIDATE_NONE) {
invalidate_other_cache(pcx_pkt, t1_addr);
if (inv_flag & INVALIDATE_DCACHE) {
way = invalidate_dcache(core_id, t1_addr);
} else {
way = search_dcache(core_id, t1_addr);
}
if (way != -1) {
pabit54 = (t1_addr & 0x30) >> 4;
switch (pabit54) {
case 0:
cpx_pkt->data0 |= (way << 2);
cpx_pkt->data0 |= 0x1;
cpx_pkt->data0 <<= (core_id * 4);
break;
case 1:
cpx_pkt->data1 = (way << 1);
cpx_pkt->data1 |= 0x1;
cpx_pkt->data1 <<= (core_id * 3);
break;
case 2:
/* assuming core_id < 2. this code needs to be modified if core_id >= 2 */
cpx_pkt->data1 = (way << 2);
cpx_pkt->data1 |= 0x1;
cpx_pkt->data1 <<= 24;
cpx_pkt->data1 <<= (core_id * 4);
break;
case 3:
/* assuming core_id < 3. this code needs to be modified if core_id >= 3 */
cpx_pkt->data2 = (way << 1);
cpx_pkt->data2 |= 0x1;
cpx_pkt->data2 <<= 24;
cpx_pkt->data2 <<= (core_id * 3);
break;
}
} else {
static int
invalidate_core_dcache(struct pcx_pkt *pcx_pkt, int core_id, int target_core_id, taddr_opt_t t1_addr)
{
int way, pabit54;
struct cpx_pkt cpx_pkt_buf;
struct cpx_pkt *cpx_pkt = &cpx_pkt_buf;
way = invalidate_dcache(target_core_id, t1_addr);
if (way == -1) {
return way;
}
CPX_PKT_CTRL_EVICT_INV(cpx_pkt, 0);
cpx_pkt->data3 = 0;
cpx_pkt->data2 = 0;
cpx_pkt->data1 = 0;
cpx_pkt->data0 = 0;
pabit54 = (t1_addr & 0x30) >> 4;
switch (pabit54) {
case 0:
cpx_pkt->data0 |= (way << 2);
cpx_pkt->data0 |= 0x1;
cpx_pkt->data0 <<= (target_core_id * 4);
break;
case 1:
cpx_pkt->data1 = (way << 1);
cpx_pkt->data1 |= 0x1;
cpx_pkt->data1 <<= (target_core_id * 3);
break;
case 2:
/* assuming core_id < 2. this code needs to be modified if core_id >= 2 */
cpx_pkt->data1 = (way << 2);
cpx_pkt->data1 |= 0x1;
cpx_pkt->data1 <<= 24;
cpx_pkt->data1 <<= (target_core_id * 4);
break;
case 3:
/* assuming core_id < 3. this code needs to be modified if core_id >= 3 */
cpx_pkt->data2 = (way << 1);
cpx_pkt->data2 |= 0x1;
cpx_pkt->data2 <<= 24;
cpx_pkt->data2 <<= (target_core_id * 3);
break;
}
CPX_PKT_REFLECT_THREAD_ID(cpx_pkt, pcx_pkt);
CPX_PKT_REFLECT_BIS(cpx_pkt, pcx_pkt);
CPX_PKT_REFLECT_ADDR_5_4(cpx_pkt, pcx_pkt);
CPX_PKT_REFLECT_ADDR_11_6(cpx_pkt, pcx_pkt);
CPX_PKT_REFLECT_CORE_ID(cpx_pkt, pcx_pkt);
send_cpx_pkt(target_core_id, cpx_pkt);
return way;
}
/******************************************************************************
* Routine: s_init
* Description: Does early system init of muxing and clocks.
* - Called path is with SRAM stack.
*****************************************************************************/
void s_init(void)
{
int in_sdram = is_running_in_sdram();
watchdog_init();
try_unlock_memory();
/*
* Right now flushing at low MPU speed.
* Need to move after clock init
*/
invalidate_dcache(get_device_type());
#ifdef CONFIG_L2_OFF
l2_cache_disable();
#else
l2_cache_enable();
#endif
/*
* Writing to AuxCR in U-boot using SMI for GP DEV
* Currently SMI in Kernel on ES2 devices seems to have an issue
* Once that is resolved, we can postpone this config to kernel
*/
if (get_device_type() == GP_DEVICE)
setup_auxcr();
set_muxconf_regs();
sdelay(100);
prcm_init();
per_clocks_enable();
#ifdef CONFIG_USB_EHCI_OMAP
ehci_clocks_enable();
#endif
#ifdef CONFIG_SPL_BUILD
preloader_console_init();
timer_init();
#endif
if (!in_sdram)
mem_init();
}
int cleanup_before_linux(void)
{
unsigned int i;
printf(" > deinit leds..\n");
leds_deinit();
/*
* this function is called just before we call linux
* it prepares the processor for linux
*
* we turn off caches etc ...
*/
disable_interrupts();
/* turn off I/D-cache */
icache_disable();
dcache_disable();
/* invalidate I-cache */
cache_flush();
#ifndef CONFIG_L2_OFF
/* turn off L2 cache */
l2_cache_disable();
/* invalidate L2 cache also */
invalidate_dcache(get_device_type());
#endif
i = 0;
/* mem barrier to sync up things */
asm("mcr p15, 0, %0, c7, c10, 4": :"r"(i));
#ifndef CONFIG_L2_OFF
l2_cache_enable();
#endif
return 0;
}
int sys_execve(const char *filename, char *const argv[], char *const envp[]){
__UNUSED_VARIABLE(envp);
int ret;
unsigned int sp;
unsigned int *tmp_sp;
char *tmp_argv[6];
unsigned int argv_pos;
int argc, i, len;
int stack_end;
ret = elf_load(filename);
if(ret < 0)
return ret;
stack_end = ret;
Task *prev_task = Kernel::getInstance()->taskmanager.getCurrentTask();
Task *current = Kernel::getInstance()->taskmanager.getTask();
if(current == NULL){
lcd_printf("Task Allocation Error\n");
for(;;);
}
sp = 0x80000; // max memory size
argc = 0;
while(argv[argc] != 0)
argc++;
for(i = 0; i < argc; i++){
len = strlen(argv[i]) + 1;
sp -= len;
sp &= 0xfffffff0; //16 byte alignment
tmp_argv[i] = (char *)sp;
memcpy((void *)sp, argv[i], len);
}
sp -= 4 * (argc + 1); // num of argv and argv[argc]
argv_pos = sp;
tmp_sp = (unsigned int *)sp;
for(i = 0; i < argc; i++){
*tmp_sp = (unsigned int)tmp_argv[i];
tmp_sp++;
}
*tmp_sp = 0;
sp -= 4*3; // argc, argv, envp
tmp_sp = (unsigned int *)sp;
*tmp_sp++ = argc;
*tmp_sp++ = argv_pos; //argv
*tmp_sp = 0; //envp
current->tss.sp = sp;
current->tss.ra = 0x20000;
current->tss.cp0_status = 0;
current->tss.cp0_epc = 0;
current->tss.cp0_cause = 0;
current->stack_start = sp;
current->stack_end = stack_end;
current->brk = stack_end;
invalidate_icache();
invalidate_dcache();
Kernel::getInstance()->taskmanager.switchContext(prev_task, current);
return 0;
}
/* IRQ handler */
void INT_USB_FUNC(void)
{
int i;
uint32_t ints = GINTSTS;
uint32_t epints;
if (ints & 0x1000) /* bus reset */
{
DCFG = 4; /* Address 0 */
reset_endpoints(1);
usb_core_bus_reset();
}
if (ints & 0x2000) /* enumeration done, we now know the speed */
{
/* Set up the maximum packet sizes accordingly */
uint32_t maxpacket = usb_drv_port_speed() ? 512 : 64;
DIEPCTL1 = (DIEPCTL1 & ~0x000003FF) | maxpacket;
DOEPCTL2 = (DOEPCTL2 & ~0x000003FF) | maxpacket;
DIEPCTL3 = (DIEPCTL3 & ~0x000003FF) | maxpacket;
DOEPCTL4 = (DOEPCTL4 & ~0x000003FF) | maxpacket;
}
if (ints & 0x40000) /* IN EP event */
for (i = 0; i < 4; i += i + 1) // 0, 1, 3
if ((epints = DIEPINT(i)))
{
if (epints & 1) /* Transfer completed */
{
invalidate_dcache();
int bytes = endpoints[i].size - (DIEPTSIZ(i) & 0x3FFFF);
if (endpoints[i].busy)
{
endpoints[i].busy = false;
endpoints[i].rc = 0;
endpoints[i].done = true;
usb_core_transfer_complete(i, USB_DIR_IN, 0, bytes);
semaphore_release(&endpoints[i].complete);
}
}
if (epints & 4) /* AHB error */
panicf("USB: AHB error on IN EP%d", i);
if (epints & 8) /* Timeout */
{
if (endpoints[i].busy)
{
endpoints[i].busy = false;
endpoints[i].rc = 1;
endpoints[i].done = true;
semaphore_release(&endpoints[i].complete);
}
}
DIEPINT(i) = epints;
}
if (ints & 0x80000) /* OUT EP event */
for (i = 0; i < USB_NUM_ENDPOINTS; i += 2)
if ((epints = DOEPINT(i)))
{
if (epints & 1) /* Transfer completed */
{
invalidate_dcache();
int bytes = endpoints[i].size - (DOEPTSIZ(i) & 0x3FFFF);
if (endpoints[i].busy)
{
endpoints[i].busy = false;
endpoints[i].rc = 0;
endpoints[i].done = true;
usb_core_transfer_complete(i, USB_DIR_OUT, 0, bytes);
semaphore_release(&endpoints[i].complete);
}
}
if (epints & 4) /* AHB error */
panicf("USB: AHB error on OUT EP%d", i);
if (epints & 8) /* SETUP phase done */
{
invalidate_dcache();
if (i == 0)
{
if (ctrlreq.bRequest == 5)
{
/* Already set the new address here,
before passing the packet to the core.
See below (usb_drv_set_address) for details. */
DCFG = (DCFG & ~0x7F0) | (ctrlreq.wValue << 4);
}
usb_core_control_request(&ctrlreq);
}
else panicf("USB: SETUP done on OUT EP%d!?", i);
}
/* Make sure EP0 OUT is set up to accept the next request */
if (!i)
{
DOEPTSIZ0 = 0x20080040;
DOEPDMA0 = &ctrlreq;
DOEPCTL0 |= 0x84000000;
}
DOEPINT(i) = epints;
}
GINTSTS = ints;
}
