int fman_dtsec_mii_write_reg(struct dtsec_mii_reg *regs, uint8_t addr,
uint8_t reg, uint16_t data, uint16_t dtsec_freq)
{
uint32_t tmp;
/* Setup the MII Mgmt clock speed */
iowrite32be((uint32_t)dtsec_mii_get_div(dtsec_freq), ®s->miimcfg);
wmb();
/* Stop the MII management read cycle */
iowrite32be(0, ®s->miimcom);
/* Dummy read to make sure MIIMCOM is written */
tmp = ioread32be(®s->miimcom);
wmb();
/* Setting up MII Management Address Register */
tmp = (uint32_t)((addr << MIIMADD_PHY_ADDR_SHIFT) | reg);
iowrite32be(tmp, ®s->miimadd);
wmb();
/* Setting up MII Management Control Register with data */
iowrite32be((uint32_t)data, ®s->miimcon);
/* Dummy read to make sure MIIMCON is written */
tmp = ioread32be(®s->miimcon);
wmb();
/* Wait until MII management write is complete */
/* todo: a timeout could be useful here */
while ((ioread32be(®s->miimind)) & MIIMIND_BUSY)
/* busy wait */;
return 0;
}
static int ulite_transmit(struct uart_port *port, int stat)
{
struct circ_buf *xmit = &port->state->xmit;
if (stat & ULITE_STATUS_TXFULL)
return 0;
if (port->x_char) {
iowrite32be(port->x_char, port->membase + ULITE_TX);
port->x_char = 0;
port->icount.tx++;
return 1;
}
if (uart_circ_empty(xmit) || uart_tx_stopped(port))
return 0;
iowrite32be(xmit->buf[xmit->tail], port->membase + ULITE_TX);
xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE-1);
port->icount.tx++;
/* wake up */
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
uart_write_wakeup(port);
return 1;
}
static void milkymist_uart_console_write(struct console *co, const char *s,
unsigned int count)
{
struct uart_port *port = &milkymist_uart_ports[co->index];
u32 ctrl;
unsigned long flags;
int locked = 1;
if (oops_in_progress)
locked = spin_trylock_irqsave(&port->lock, flags);
else
spin_lock_irqsave(&port->lock, flags);
/* wait until current transmission is finished */
milkymist_uart_console_wait_tx(port);
/* save ctrl and stat */
ctrl = ioread32be(port->membase + UART_CTRL);
/* disable irqs */
iowrite32be(ctrl & ~(UART_CTRL_RX_INT | UART_CTRL_TX_INT),
port->membase + UART_CTRL);
uart_console_write(port, s, count, milkymist_uart_console_putchar);
milkymist_uart_console_wait_tx(port);
/* ack write event */
iowrite32be(UART_STAT_TX_EVT, port->membase + UART_STAT);
/* restore control register */
iowrite32be(ctrl, port->membase + UART_CTRL);
if (locked)
spin_unlock_irqrestore(&port->lock, flags);
}
static void write_phy_reg_10g(struct memac_mii_access_mem_map *mii_regs,
uint8_t phy_addr, uint8_t reg, uint16_t data)
{
uint32_t tmp_reg;
tmp_reg = ioread32be(&mii_regs->mdio_cfg);
/* Leave only MDIO_CLK_DIV bits set on */
tmp_reg &= MDIO_CFG_CLK_DIV_MASK;
/* Set maximum MDIO_HOLD value to allow phy to see
change of data signal */
tmp_reg |= MDIO_CFG_HOLD_MASK;
/* Add 10G interface mode */
tmp_reg |= MDIO_CFG_ENC45;
iowrite32be(tmp_reg, &mii_regs->mdio_cfg);
/* Wait for command completion */
while ((ioread32be(&mii_regs->mdio_cfg)) & MDIO_CFG_BSY)
udelay(1);
/* Specify phy and register to be accessed */
iowrite32be(phy_addr, &mii_regs->mdio_ctrl);
iowrite32be(reg, &mii_regs->mdio_addr);
wmb();
while ((ioread32be(&mii_regs->mdio_cfg)) & MDIO_CFG_BSY)
udelay(1);
/* Write data */
iowrite32be(data, &mii_regs->mdio_data);
wmb();
/* Wait for write transaction end */
while ((ioread32be(&mii_regs->mdio_data)) & MDIO_DATA_BSY)
udelay(1);
}
static void write_phy_reg_1g(struct memac_mii_access_mem_map *mii_regs,
uint8_t phy_addr, uint8_t reg, uint16_t data)
{
uint32_t tmp_reg;
/* Leave only MDIO_CLK_DIV and MDIO_HOLD bits set on */
tmp_reg = ioread32be(&mii_regs->mdio_cfg);
tmp_reg &= (MDIO_CFG_CLK_DIV_MASK | MDIO_CFG_HOLD_MASK);
iowrite32be(tmp_reg, &mii_regs->mdio_cfg);
/* Wait for command completion */
while ((ioread32be(&mii_regs->mdio_cfg)) & MDIO_CFG_BSY)
udelay(1);
/* Write transaction */
tmp_reg = (phy_addr << MDIO_CTL_PHY_ADDR_SHIFT);
tmp_reg |= reg;
iowrite32be(tmp_reg, &mii_regs->mdio_ctrl);
while ((ioread32be(&mii_regs->mdio_cfg)) & MDIO_CFG_BSY)
udelay(1);
iowrite32be(data, &mii_regs->mdio_data);
wmb();
/* Wait for write transaction to end */
while ((ioread32be(&mii_regs->mdio_data)) & MDIO_DATA_BSY)
udelay(1);
}
static uint32_t read_phy_reg_1g(struct memac_mii_access_mem_map *mii_regs,
uint8_t phy_addr, uint8_t reg, uint16_t *data)
{
uint32_t tmp_reg;
/* Leave only MDIO_CLK_DIV and MDIO_HOLD bits set on */
tmp_reg = ioread32be(&mii_regs->mdio_cfg);
tmp_reg &= (MDIO_CFG_CLK_DIV_MASK | MDIO_CFG_HOLD_MASK);
iowrite32be(tmp_reg, &mii_regs->mdio_cfg);
/* Wait for command completion */
while ((ioread32be(&mii_regs->mdio_cfg)) & MDIO_CFG_BSY)
udelay(1);
/* Read transaction */
tmp_reg = (phy_addr << MDIO_CTL_PHY_ADDR_SHIFT);
tmp_reg |= reg;
tmp_reg |= MDIO_CTL_READ;
iowrite32be(tmp_reg, &mii_regs->mdio_ctrl);
while ((ioread32be(&mii_regs->mdio_cfg)) & MDIO_CFG_BSY)
udelay(1);
/* Wait for data to be available */
while ((ioread32be(&mii_regs->mdio_data)) & MDIO_DATA_BSY)
udelay(1);
*data = (uint16_t)ioread32be(&mii_regs->mdio_data);
/* Check error */
return ioread32be(&mii_regs->mdio_cfg);
}
int dtsec_enable(struct fman_mac *dtsec, enum comm_mode mode)
{
struct dtsec_regs __iomem *regs = dtsec->regs;
u32 tmp;
if (!is_init_done(dtsec->dtsec_drv_param))
return -EINVAL;
/* Enable */
tmp = ioread32be(®s->maccfg1);
if (mode & COMM_MODE_RX)
tmp |= MACCFG1_RX_EN;
if (mode & COMM_MODE_TX)
tmp |= MACCFG1_TX_EN;
iowrite32be(tmp, ®s->maccfg1);
/* Graceful start - clear the graceful receive stop bit */
if (mode & COMM_MODE_TX)
iowrite32be(ioread32be(®s->tctrl) & ~DTSEC_TCTRL_GTS,
®s->tctrl);
if (mode & COMM_MODE_RX)
iowrite32be(ioread32be(®s->rctrl) & ~RCTRL_GRS,
®s->rctrl);
return 0;
}
static void ulite_console_write(struct console *co, const char *s,
unsigned int count)
{
struct uart_port *port = &ulite_ports[co->index];
unsigned long flags;
unsigned int ier;
int locked = 1;
if (oops_in_progress) {
locked = spin_trylock_irqsave(&port->lock, flags);
} else
spin_lock_irqsave(&port->lock, flags);
/* save and disable interrupt */
ier = ioread32be(port->membase + ULITE_STATUS) & ULITE_STATUS_IE;
iowrite32be(0, port->membase + ULITE_CONTROL);
uart_console_write(port, s, count, ulite_console_putchar);
ulite_console_wait_tx(port);
/* restore interrupt state */
if (ier)
iowrite32be(ULITE_CONTROL_IE, port->membase + ULITE_CONTROL);
if (locked)
spin_unlock_irqrestore(&port->lock, flags);
}
void EnableCtrInterrupt(void) {
unsigned int val;
printk(KERN_DEBUG PFX "Enabling PPS interrupt on IRQ%d Vector %d\n",
CTR_IRQ_LEVEL, CTR_IRQ_VECTOR);
/* Setup the IRQ level and vector */
val = (unsigned long)((CTR_IRQ_LEVEL << 8) | (CTR_IRQ_VECTOR & 0xff));
iowrite32be(val, &mmap->Setup);
if (vme_bus_error_check(1))
printk(KERN_ERR PFX "Bus error writing Setup\n");
/* Will interrupt once per second */
iowrite32be(CtrDrvrInterruptMaskPPS, &mmap->InterruptEnable);
if (vme_bus_error_check(1))
printk(KERN_ERR PFX "Bus error writing InterruptEnable\n");
val = ioread32be(&mmap->InterruptEnable);
if (vme_bus_error_check(1))
printk(KERN_ERR PFX "Bus error reading InterruptEnable\n");
if (val != CtrDrvrInterruptMaskPPS)
printk(KERN_DEBUG PFX "Failed to enable PPS interrupt %08x\n",
val);
}
int dtsec_set_tx_pause_frames(struct fman_mac *dtsec,
u8 __maybe_unused priority,
u16 pause_time, u16 __maybe_unused thresh_time)
{
struct dtsec_regs __iomem *regs = dtsec->regs;
u32 ptv = 0;
if (!is_init_done(dtsec->dtsec_drv_param))
return -EINVAL;
if (pause_time) {
/* FM_BAD_TX_TS_IN_B_2_B_ERRATA_DTSEC_A003 Errata workaround */
if (dtsec->fm_rev_info.major == 2 && pause_time <= 320) {
pr_warn("pause-time: %d illegal.Should be > 320\n",
pause_time);
return -EINVAL;
}
ptv = ioread32be(®s->ptv);
ptv &= PTV_PTE_MASK;
ptv |= pause_time & PTV_PT_MASK;
iowrite32be(ptv, ®s->ptv);
/* trigger the transmission of a flow-control pause frame */
iowrite32be(ioread32be(®s->maccfg1) | MACCFG1_TX_FLOW,
®s->maccfg1);
} else
iowrite32be(ioread32be(®s->maccfg1) & ~MACCFG1_TX_FLOW,
®s->maccfg1);
return 0;
}
void fman_dtsec_mii_reset(struct dtsec_mii_reg *regs)
{
/* Reset the management interface */
iowrite32be(ioread32be(®s->miimcfg) | MIIMCFG_RESET_MGMT,
®s->miimcfg);
iowrite32be(ioread32be(®s->miimcfg) & ~MIIMCFG_RESET_MGMT,
®s->miimcfg);
}
static void set_mac_address(struct dtsec_regs __iomem *regs, u8 *adr)
{
u32 tmp;
tmp = (u32)((adr[5] << 24) |
(adr[4] << 16) | (adr[3] << 8) | adr[2]);
iowrite32be(tmp, ®s->macstnaddr1);
tmp = (u32)((adr[1] << 24) | (adr[0] << 16));
iowrite32be(tmp, ®s->macstnaddr2);
}
void fman_dtsec_set_mac_address(struct dtsec_regs *regs, uint8_t *adr)
{
uint32_t tmp;
tmp = (uint32_t)((adr[5] << 24) |
(adr[4] << 16) |
(adr[3] << 8) |
adr[2]);
iowrite32be(tmp, ®s->macstnaddr1);
tmp = (uint32_t)((adr[1] << 24) |
(adr[0] << 16));
iowrite32be(tmp, ®s->macstnaddr2);
}
static int ulite_startup(struct uart_port *port)
{
int ret;
ret = request_irq(port->irq, ulite_isr,
IRQF_SHARED | IRQF_SAMPLE_RANDOM, "uartlite", port);
if (ret)
return ret;
iowrite32be(ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX,
port->membase + ULITE_CONTROL);
iowrite32be(ULITE_CONTROL_IE, port->membase + ULITE_CONTROL);
return 0;
}
static void eznps_init_core(unsigned int cpu)
{
u32 sync_value;
struct nps_host_reg_aux_hw_comply hw_comply;
struct nps_host_reg_aux_lpc lpc;
if (NPS_CPU_TO_THREAD_NUM(cpu) != 0)
return;
hw_comply.value = read_aux_reg(AUX_REG_HW_COMPLY);
hw_comply.me = 1;
hw_comply.le = 1;
#ifdef CONFIG_EZNPS_SHARED_TIMER
hw_comply.te = 1;
#endif
write_aux_reg(AUX_REG_HW_COMPLY, hw_comply.value);
/* Enable MMU clock */
lpc.mep = 1;
write_aux_reg(CTOP_AUX_LPC, lpc.value);
/* Boot CPU only */
if (!cpu) {
/* Write to general purpose register in CRG */
sync_value = ioread32be(REG_GEN_PURP_0);
sync_value |= NPS_CRG_SYNC_BIT;
iowrite32be(sync_value, REG_GEN_PURP_0);
}
}
static void mpc8xxx_gpio_set_multiple(struct gpio_chip *gc,
unsigned long *mask, unsigned long *bits)
{
struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
unsigned long flags;
int i;
spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
for (i = 0; i < gc->ngpio; i++) {
if (*mask == 0)
break;
if (__test_and_clear_bit(i, mask)) {
if (test_bit(i, bits))
mpc8xxx_gc->data |= mpc8xxx_gpio2mask(i);
else
mpc8xxx_gc->data &= ~mpc8xxx_gpio2mask(i);
}
}
iowrite32be(mpc8xxx_gc->data, mm->regs + GPIO_DAT);
spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
}
static void mpc8xxx_irq_ack(struct irq_data *d)
{
struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
iowrite32be(mpc8xxx_gpio2mask(irqd_to_hwirq(d)), mm->regs + GPIO_IER);
}
static void ocfb_writereg(struct ocfb_dev *fbdev, loff_t offset, u32 data)
{
if (fbdev->little_endian)
iowrite32(data, fbdev->regs + offset);
else
iowrite32be(data, fbdev->regs + offset);
}
static inline void xiic_setreg32(struct xiic_i2c *i2c, int reg, int value)
{
if (i2c->endianness == LITTLE)
iowrite32(value, i2c->base + reg);
else
iowrite32be(value, i2c->base + reg);
}
static void apbps2_close(struct serio *io)
{
struct apbps2_priv *priv = io->port_data;
/* stop interrupts at PS/2 HW level */
iowrite32be(0, &priv->regs->ctrl);
}
static inline void ethoc_write(struct ethoc *dev, loff_t offset, u32 data)
{
if (dev->big_endian)
iowrite32be(data, dev->iobase + offset);
else
iowrite32(data, dev->iobase + offset);
}
static void dw8250_check_lcr(struct uart_port *p, int value)
{
void __iomem *offset = p->membase + (UART_LCR << p->regshift);
int tries = 1000;
/* Make sure LCR write wasn't ignored */
while (tries--) {
unsigned int lcr = p->serial_in(p, UART_LCR);
if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
return;
dw8250_force_idle(p);
#ifdef CONFIG_64BIT
if (p->type == PORT_OCTEON)
__raw_writeq(value & 0xff, offset);
else
#endif
if (p->iotype == UPIO_MEM32)
writel(value, offset);
else if (p->iotype == UPIO_MEM32BE)
iowrite32be(value, offset);
else
writeb(value, offset);
}
/*
* FIXME: this deadlocks if port->lock is already held
* dev_err(p->dev, "Couldn't set LCR to %d\n", value);
*/
}
static inline void ftm_writel(u32 val, void __iomem *addr)
{
if (priv->big_endian)
iowrite32be(val, addr);
else
iowrite32(val, addr);
}
static void cg_out(struct clockgen *cg, u32 val, u32 __iomem *reg)
{
if (cg->info.flags & CG_LITTLE_ENDIAN)
iowrite32(val, reg);
else
iowrite32be(val, reg);
}
static inline void clk_fd_writel(struct clk_fractional_divider *fd, u32 val)
{
if (fd->flags & CLK_FRAC_DIVIDER_BIG_ENDIAN)
iowrite32be(val, fd->reg);
else
writel(val, fd->reg);
}
static void edma_writel(struct fsl_edma_engine *edma, u32 val, void __iomem *addr)
{
if (edma->big_endian)
iowrite32be(val, addr);
else
iowrite32(val, addr);
}
/* original ISR behavior which manipulates the EVR's
* IRQFlag and IRQEnable.
*/
static
irqreturn_t
mrf_handler_evr(int irq, struct uio_info *info)
{
void __iomem *base = info->mem[2].internal_addr;
void __iomem *plx = info->mem[0].internal_addr;
struct pci_dev *dev = info->priv;
u32 plxctrl, status, enable;
int end;
switch(dev->device) {
case PCI_DEVICE_ID_PLX_9030:
plxctrl = ioread32(plx + LAS0BRD);
end = plxctrl & LAS0BRD_ENDIAN;
break;
case PCI_DEVICE_ID_PLX_9056:
plxctrl = ioread32(plx + BIGEND9056);
end = plxctrl & BIGEND9056_BIG;
break;
default:
return IRQ_NONE; /* hope this never happens :) */
}
/* Test endianness since we allow user
* apps to use whatever is convenient
*/
if (end) {
status = ioread32be(base + IRQFlag);
enable = ioread32be(base + IRQEnable);
} else {
status = ioread32(base + IRQFlag);
enable = ioread32(base + IRQEnable);
}
if (!(status & enable))
return IRQ_NONE;
if(!(enable & IRQ_Enable))
dev_info(&dev->dev, "Interrupt when not enabled! 0x%08lx 0x%08lx\n",
(unsigned long)enable, (unsigned long)status);
/* Disable interrupt */
if (end)
iowrite32be(enable & ~IRQ_Enable, base + IRQEnable);
else
iowrite32(enable & ~IRQ_Enable, base + IRQEnable);
/* Ensure interrupts have really been disabled */
wmb();
if (end) {
enable = ioread32be(base + IRQEnable);
} else {
enable = ioread32(base + IRQEnable);
}
if(enable & IRQ_Enable)
dev_info(&dev->dev, "Interrupt not disabled!!!");
return IRQ_HANDLED;
}
void DisableCtrInterrupt(void)
{
printk(KERN_DEBUG PFX "Disabling PPS interrupt\n");
iowrite32be(0, &mmap->InterruptEnable);
if (vme_bus_error_check(1))
printk(KERN_ERR PFX "Bus error writing InterruptEnable\n");
}
static void ulite_put_poll_char(struct uart_port *port, unsigned char ch)
{
while (ioread32be(port->membase + ULITE_STATUS) & ULITE_STATUS_TXFULL)
cpu_relax();
/* write char to device */
iowrite32be(ch, port->membase + ULITE_TX);
}
static inline void ocsdc_write(struct ocsdc_dev * dev, int offset, uint32_t data)
{
#ifdef CONFIG_WISHBONE_BUS_BIG_ENDIAN
iowrite32be(data, dev->iobase + offset);
#else
iowrite32(data, dev->iobase + offset);
#endif
}