static ssize_t set_volt_table(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
{
struct exynos_context *platform = (struct exynos_context *)pkbdev->platform_context;
int max = gpu_dvfs_get_level(platform->gpu_max_clock);
int min = gpu_dvfs_get_level(platform->gpu_min_clock);
int i, tokens, rest, target;
int t[min - max];
unsigned long flags;
if ((tokens = read_into((int*)&t, min-max, buf, count)) < 0)
return -EINVAL;
target = -1;
if (tokens == 2) {
for (i = max; i <= min; i++) {
if (t[0] == platform->table[i].clock) {
target = i;
break;
}
}
}
spin_lock_irqsave(&platform->gpu_dvfs_spinlock, flags);
if (tokens == 2 && target > -1) {
if ((rest = t[1] % GPU_VOLT_STEP) != 0)
t[1] += GPU_VOLT_STEP - rest;
sanitize_min_max(t[1], GPU_MIN_VOLT, GPU_MAX_VOLT);
platform->table[target].voltage = t[1];
} else {
for (i = 0; i < tokens; i++) {
if ((rest = t[i] % GPU_VOLT_STEP) != 0)
t[i] += GPU_VOLT_STEP - rest;
sanitize_min_max(t[i], GPU_MIN_VOLT, GPU_MAX_VOLT);
platform->table[i + max].voltage = t[i];
}
}
ipa_update();
spin_unlock_irqrestore(&platform->gpu_dvfs_spinlock, flags);
return count;
}
static ssize_t set_volt_table(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
{
struct kbase_device *kbdev;
struct exynos_context *platform;
int max = 0; /* max DVFS level (100MHz) */
int min = 7; /* min DVFS level (677MHz) */
int i, tokens, rest, target;
int t[min - max];
unsigned long flags;
kbdev = dev_get_drvdata(dev);
platform = (struct exynos_context *)kbdev->platform_context;
if ((tokens = read_into((int*)&t, min-max, buf, count)) < 0)
return -EINVAL;
target = -1;
if (tokens == 2) {
for (i = max; i <= min; i++) {
if (t[0] == platform->table[i].clock) {
target = i;
break;
}
}
}
spin_lock_irqsave(&platform->gpu_dvfs_spinlock, flags);
if (tokens == 2 && target > -1) {
sanitize_min_max(t[1], 600000, 1150000);
if ((rest = t[1] % 6250) != 0) t[1] += 6250-rest;
platform->table[target].voltage = t[1];
} else {
for (i = 0; i < tokens; i++) {
if ((rest = t[1] % 6250) != 0) t[1] += 6250-rest;
sanitize_min_max(t[i], 600000, 1150000);
platform->table[i + max].voltage = t[i];
}
}
ipa_update();
spin_unlock_irqrestore(&platform->gpu_dvfs_spinlock, flags);
return count;
}
