void ipu_srm_dp_sync_update(struct ipu_soc *ipu)
{
	u32 val;

	val = ipu_cm_read(ipu, IPU_SRM_PRI2);
	val |= 0x8;
	ipu_cm_write(ipu, val, IPU_SRM_PRI2);
}
static void _ipu_pixel_clk_disable(struct clk_hw *hw)
{
	struct clk_di_gate *gate = to_clk_di_gate(hw);
	struct ipu_soc *ipu = ipu_get_soc(gate->ipu_id);
	u32 disp_gen;

	disp_gen = ipu_cm_read(ipu, IPU_DISP_GEN);
	disp_gen &= gate->di_id ? ~DI1_COUNTER_RELEASE : ~DI0_COUNTER_RELEASE;
	ipu_cm_write(ipu, disp_gen, IPU_DISP_GEN);

}
static int _ipu_pixel_clk_enable(struct clk_hw *hw)
{
	struct clk_di_gate *gate = to_clk_di_gate(hw);
	struct ipu_soc *ipu = ipu_get_soc(gate->ipu_id);
	u32 disp_gen;

	disp_gen = ipu_cm_read(ipu, IPU_DISP_GEN);
	disp_gen |= gate->di_id ? DI1_COUNTER_RELEASE : DI0_COUNTER_RELEASE;
	ipu_cm_write(ipu, disp_gen, IPU_DISP_GEN);

	return 0;
}