static void pcap_irq_handler(struct irq_desc *desc) { struct pcap_chip *pcap = irq_desc_get_handler_data(desc); desc->irq_data.chip->irq_ack(&desc->irq_data); queue_work(pcap->workqueue, &pcap->isr_work); }
static void intel_mid_irq_handler(struct irq_desc *desc) { struct gpio_chip *gc = irq_desc_get_handler_data(desc); struct intel_mid_gpio *priv = gpiochip_get_data(gc); struct irq_data *data = irq_desc_get_irq_data(desc); struct irq_chip *chip = irq_data_get_irq_chip(data); u32 base, gpio, mask; unsigned long pending; void __iomem *gedr; /* check GPIO controller to check which pin triggered the interrupt */ for (base = 0; base < priv->chip.ngpio; base += 32) { gedr = gpio_reg(&priv->chip, base, GEDR); while ((pending = readl(gedr))) { gpio = __ffs(pending); mask = BIT(gpio); /* Clear before handling so we can't lose an edge */ writel(mask, gedr); generic_handle_irq(irq_find_mapping(gc->irqdomain, base + gpio)); } } chip->irq_eoi(data); }
static void combiner_handle_cascade_irq(struct irq_desc *desc) { struct combiner_chip_data *chip_data = irq_desc_get_handler_data(desc); struct irq_chip *chip = irq_desc_get_chip(desc); unsigned int cascade_irq, combiner_irq; unsigned long status; chained_irq_enter(chip, desc); spin_lock(&irq_controller_lock); status = readl_relaxed(chip_data->base + COMBINER_INT_STATUS); spin_unlock(&irq_controller_lock); status &= chip_data->irq_mask; if (status == 0) goto out; combiner_irq = chip_data->hwirq_offset + __ffs(status); cascade_irq = irq_find_mapping(combiner_irq_domain, combiner_irq); if (unlikely(!cascade_irq)) handle_bad_irq(desc); else generic_handle_irq(cascade_irq); out: chained_irq_exit(chip, desc); }
static void psc_irq(unsigned int irq, struct irq_desc *desc) { unsigned int offset = (unsigned int)irq_desc_get_handler_data(desc); int pIFR = pIFRbase + offset; int pIER = pIERbase + offset; int irq_num; unsigned char irq_bit, events; #ifdef DEBUG_IRQS printk("psc_irq: irq %u pIFR = 0x%02X pIER = 0x%02X\n", irq, (int) psc_read_byte(pIFR), (int) psc_read_byte(pIER)); #endif events = psc_read_byte(pIFR) & psc_read_byte(pIER) & 0xF; if (!events) return; irq_num = irq << 3; irq_bit = 1; do { if (events & irq_bit) { psc_write_byte(pIFR, irq_bit); generic_handle_irq(irq_num); } irq_num++; irq_bit <<= 1; } while (events >= irq_bit); }
static void altera_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) { struct altera_gpio_chip *altera_gc = irq_desc_get_handler_data(desc); struct irq_chip *chip = irq_desc_get_chip(desc); struct of_mm_gpio_chip *mm_gc = &altera_gc->mmchip; unsigned long status; int base; chip->irq_mask(&desc->irq_data); if (altera_gc->level_trigger) status = readl(mm_gc->regs + ALTERA_GPIO_DATA); else { status = readl(mm_gc->regs + ALTERA_GPIO_EDGE_CAP); writel(status, mm_gc->regs + ALTERA_GPIO_EDGE_CAP); } status &= readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK); for (base = 0; base < mm_gc->gc.ngpio; base++) { if ((1 << base) & status) { generic_handle_irq( irq_linear_revmap(altera_gc->irq, base)); } } chip->irq_eoi(irq_desc_get_irq_data(desc)); chip->irq_unmask(&desc->irq_data); }
static void tz1090_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) { irq_hw_number_t hw; unsigned int irq_stat, irq_no; struct tz1090_gpio_bank *bank; struct irq_desc *child_desc; bank = (struct tz1090_gpio_bank *)irq_desc_get_handler_data(desc); irq_stat = tz1090_gpio_read(bank, REG_GPIO_DIR) & tz1090_gpio_read(bank, REG_GPIO_IRQ_STS) & tz1090_gpio_read(bank, REG_GPIO_IRQ_EN) & 0x3FFFFFFF; /* 30 bits only */ for (hw = 0; irq_stat; irq_stat >>= 1, ++hw) { if (!(irq_stat & 1)) continue; irq_no = irq_linear_revmap(bank->domain, hw); child_desc = irq_to_desc(irq_no); /* Toggle edge for pin with both edges triggering enabled */ if (irqd_get_trigger_type(&child_desc->irq_data) == IRQ_TYPE_EDGE_BOTH) tz1090_gpio_irq_next_edge(bank, hw); generic_handle_irq_desc(irq_no, child_desc); } }
static void idu_cascade_isr(struct irq_desc *desc) { struct irq_domain *idu_domain = irq_desc_get_handler_data(desc); irq_hw_number_t core_hwirq = irqd_to_hwirq(irq_desc_get_irq_data(desc)); irq_hw_number_t idu_hwirq = core_hwirq - idu_first_hwirq; generic_handle_irq(irq_find_mapping(idu_domain, idu_hwirq)); }
static void idu_cascade_isr(unsigned int core_irq, struct irq_desc *desc) { struct irq_domain *domain = irq_desc_get_handler_data(desc); unsigned int idu_irq; idu_irq = core_irq - idu_first_irq; generic_handle_irq(irq_find_mapping(domain, idu_irq)); }
static void axon_msi_cascade(struct irq_desc *desc) { struct irq_chip *chip = irq_desc_get_chip(desc); struct axon_msic *msic = irq_desc_get_handler_data(desc); u32 write_offset, msi; int idx; int retry = 0; write_offset = dcr_read(msic->dcr_host, MSIC_WRITE_OFFSET_REG); pr_devel("axon_msi: original write_offset 0x%x\n", write_offset); /* write_offset doesn't wrap properly, so we have to mask it */ write_offset &= MSIC_FIFO_SIZE_MASK; while (msic->read_offset != write_offset && retry < 100) { idx = msic->read_offset / sizeof(__le32); msi = le32_to_cpu(msic->fifo_virt[idx]); msi &= 0xFFFF; pr_devel("axon_msi: woff %x roff %x msi %x\n", write_offset, msic->read_offset, msi); if (msi < nr_irqs && irq_get_chip_data(msi) == msic) { generic_handle_irq(msi); msic->fifo_virt[idx] = cpu_to_le32(0xffffffff); } else { /* * Reading the MSIC_WRITE_OFFSET_REG does not * reliably flush the outstanding DMA to the * FIFO buffer. Here we were reading stale * data, so we need to retry. */ udelay(1); retry++; pr_devel("axon_msi: invalid irq 0x%x!\n", msi); continue; } if (retry) { pr_devel("axon_msi: late irq 0x%x, retry %d\n", msi, retry); retry = 0; } msic->read_offset += MSIC_FIFO_ENTRY_SIZE; msic->read_offset &= MSIC_FIFO_SIZE_MASK; } if (retry) { printk(KERN_WARNING "axon_msi: irq timed out\n"); msic->read_offset += MSIC_FIFO_ENTRY_SIZE; msic->read_offset &= MSIC_FIFO_SIZE_MASK; } chip->irq_eoi(&desc->irq_data); }
static void ralink_intc_irq_handler(unsigned int irq, struct irq_desc *desc) { u32 pending = rt_intc_r32(INTC_REG_STATUS0); if (pending) { struct irq_domain *domain = irq_desc_get_handler_data(desc); generic_handle_irq(irq_find_mapping(domain, __ffs(pending))); } else { spurious_interrupt(); } }
static void idu_cascade_isr(struct irq_desc *desc) { struct irq_domain *idu_domain = irq_desc_get_handler_data(desc); struct irq_chip *core_chip = irq_desc_get_chip(desc); irq_hw_number_t core_hwirq = irqd_to_hwirq(irq_desc_get_irq_data(desc)); irq_hw_number_t idu_hwirq = core_hwirq - FIRST_EXT_IRQ; chained_irq_enter(core_chip, desc); generic_handle_irq(irq_find_mapping(idu_domain, idu_hwirq)); chained_irq_exit(core_chip, desc); }
static void cell_mpic_cascade(unsigned int irq, struct irq_desc *desc) { struct irq_chip *chip = irq_desc_get_chip(desc); struct mpic *mpic = irq_desc_get_handler_data(desc); unsigned int virq; virq = mpic_get_one_irq(mpic); if (virq != NO_IRQ) generic_handle_irq(virq); chip->irq_eoi(&desc->irq_data); }
static void mpc8xxx_gpio_irq_cascade(unsigned int irq, struct irq_desc *desc) { struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_desc_get_handler_data(desc); struct irq_chip *chip = irq_desc_get_chip(desc); struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; unsigned int mask; mask = in_be32(mm->regs + GPIO_IER) & in_be32(mm->regs + GPIO_IMR); if (mask) generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq, 32 - ffs(mask))); chip->irq_eoi(&desc->irq_data); }
static void jz4740_adc_irq_demux(struct irq_desc *desc) { struct irq_chip_generic *gc = irq_desc_get_handler_data(desc); uint8_t status; unsigned int i; status = readb(gc->reg_base + JZ_REG_ADC_STATUS); for (i = 0; i < 5; ++i) { if (status & BIT(i)) generic_handle_irq(gc->irq_base + i); } }
/* * Install handler for Neponset IRQ. Note that we have to loop here * since the ETHERNET and USAR IRQs are level based, and we need to * ensure that the IRQ signal is deasserted before returning. This * is rather unfortunate. */ static void neponset_irq_handler(struct irq_desc *desc) { struct neponset_drvdata *d = irq_desc_get_handler_data(desc); unsigned int irr; while (1) { /* * Acknowledge the parent IRQ. */ desc->irq_data.chip->irq_ack(&desc->irq_data); /* * Read the interrupt reason register. Let's have all * active IRQ bits high. Note: there is a typo in the * Neponset user's guide for the SA1111 IRR level. */ irr = readb_relaxed(d->base + IRR); irr ^= IRR_ETHERNET | IRR_USAR; if ((irr & (IRR_ETHERNET | IRR_USAR | IRR_SA1111)) == 0) break; /* * Since there is no individual mask, we have to * mask the parent IRQ. This is safe, since we'll * recheck the register for any pending IRQs. */ if (irr & (IRR_ETHERNET | IRR_USAR)) { desc->irq_data.chip->irq_mask(&desc->irq_data); /* * Ack the interrupt now to prevent re-entering * this neponset handler. Again, this is safe * since we'll check the IRR register prior to * leaving. */ desc->irq_data.chip->irq_ack(&desc->irq_data); if (irr & IRR_ETHERNET) generic_handle_irq(d->irq_base + NEP_IRQ_SMC91X); if (irr & IRR_USAR) generic_handle_irq(d->irq_base + NEP_IRQ_USAR); desc->irq_data.chip->irq_unmask(&desc->irq_data); } if (irr & IRR_SA1111) generic_handle_irq(d->irq_base + NEP_IRQ_SA1111); } }
static void jz_adc_irq_demux(unsigned int irq, struct irq_desc *desc) { struct jz_adc *adc = irq_desc_get_handler_data(desc); uint8_t status; unsigned int i; status = readb(adc->base + JZ_REG_ADC_STATUS); for (i = 0; i < SADC_NR_IRQS; i++) { if (status & BIT(i)) { generic_handle_irq(adc->irq_base + i); } } }
static void orion_bridge_irq_handler(unsigned int irq, struct irq_desc *desc) { struct irq_domain *d = irq_desc_get_handler_data(desc); struct irq_chip_generic *gc = irq_get_domain_generic_chip(d, 0); u32 stat = readl_relaxed(gc->reg_base + ORION_BRIDGE_IRQ_CAUSE) & gc->mask_cache; while (stat) { u32 hwirq = __fls(stat); generic_handle_irq(irq_find_mapping(d, gc->irq_base + hwirq)); stat &= ~(1 << hwirq); } }
static void shirq_handler(unsigned __irq, struct irq_desc *desc) { struct spear_shirq *shirq = irq_desc_get_handler_data(desc); u32 pend; pend = readl(shirq->base + shirq->status_reg) & shirq->mask; pend >>= shirq->offset; while (pend) { int irq = __ffs(pend); pend &= ~(0x1 << irq); generic_handle_irq(shirq->virq_base + irq); } }
static void mpc8xxx_gpio_irq_cascade(struct irq_desc *desc) { struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_desc_get_handler_data(desc); struct irq_chip *chip = irq_desc_get_chip(desc); struct gpio_chip *gc = &mpc8xxx_gc->gc; unsigned int mask; mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_IER) & gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR); if (mask) generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq, 32 - ffs(mask))); if (chip->irq_eoi) chip->irq_eoi(&desc->irq_data); }
static void fpga_irq_handle(unsigned int irq, struct irq_desc *desc) { struct fpga_irq_data *f = irq_desc_get_handler_data(desc); u32 status = readl(f->base + IRQ_STATUS); if (status == 0) { do_bad_IRQ(irq, desc); return; } do { irq = ffs(status) - 1; status &= ~(1 << irq); generic_handle_irq(irq_find_mapping(f->domain, irq)); } while (status); }
static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) { unsigned int port = (unsigned int)irq_desc_get_handler_data(desc); unsigned int gpio_irq_no, irq_stat; irq_stat = __raw_readl(GPIO_BASE(port) + GPIO_INT_STAT); gpio_irq_no = GPIO_IRQ_BASE + port * 32; for (; irq_stat != 0; irq_stat >>= 1, gpio_irq_no++) { if ((irq_stat & 1) == 0) continue; generic_handle_irq(gpio_irq_no); } }
static void demux_eic_irq(unsigned int irq, struct irq_desc *desc) { struct eic *eic = irq_desc_get_handler_data(desc); unsigned long status, pending; unsigned int i; status = eic_readl(eic, ISR); pending = status & eic_readl(eic, IMR); while (pending) { i = fls(pending) - 1; pending &= ~(1 << i); generic_handle_irq(i + eic->first_irq); } }
static void oxnas_gpio_irq_handler(struct irq_desc *desc) { struct gpio_chip *gc = irq_desc_get_handler_data(desc); struct oxnas_gpio_bank *bank = gpiochip_get_data(gc); struct irq_chip *chip = irq_desc_get_chip(desc); unsigned long stat; unsigned int pin; chained_irq_enter(chip, desc); stat = readl(bank->reg_base + IRQ_PENDING); for_each_set_bit(pin, &stat, BITS_PER_LONG) generic_handle_irq(irq_linear_revmap(gc->irqdomain, pin)); chained_irq_exit(chip, desc); }
static void byt_gpio_irq_handler(unsigned irq, struct irq_desc *desc) { struct irq_data *data = irq_desc_get_irq_data(desc); struct byt_gpio *vg = to_byt_gpio(irq_desc_get_handler_data(desc)); struct irq_chip *chip = irq_data_get_irq_chip(data); u32 base, pin, mask; void __iomem *reg; u32 pending; unsigned virq; int looplimit = 0; /* check from GPIO controller which pin triggered the interrupt */ for (base = 0; base < vg->chip.ngpio; base += 32) { reg = byt_gpio_reg(&vg->chip, base, BYT_INT_STAT_REG); while ((pending = readl(reg))) { pin = __ffs(pending); mask = BIT(pin); /* Clear before handling so we can't lose an edge */ writel(mask, reg); virq = irq_find_mapping(vg->chip.irqdomain, base + pin); generic_handle_irq(virq); /* In case bios or user sets triggering incorretly a pin * might remain in "interrupt triggered" state. */ if (looplimit++ > 32) { dev_err(&vg->pdev->dev, "Gpio %d interrupt flood, disabling\n", base + pin); reg = byt_gpio_reg(&vg->chip, base + pin, BYT_CONF0_REG); mask = readl(reg); mask &= ~(BYT_TRIG_NEG | BYT_TRIG_POS | BYT_TRIG_LVL); writel(mask, reg); mask = readl(reg); /* flush */ break; } } } chip->irq_eoi(data); }
static void ftgpio_gpio_irq_handler(struct irq_desc *desc) { struct gpio_chip *gc = irq_desc_get_handler_data(desc); struct ftgpio_gpio *g = gpiochip_get_data(gc); struct irq_chip *irqchip = irq_desc_get_chip(desc); int offset; unsigned long stat; chained_irq_enter(irqchip, desc); stat = readl(g->base + GPIO_INT_STAT_RAW); if (stat) for_each_set_bit(offset, &stat, gc->ngpio) generic_handle_irq(irq_find_mapping(gc->irq.domain, offset)); chained_irq_exit(irqchip, desc); }
static void pl061_irq_handler(unsigned irq, struct irq_desc *desc) { unsigned long pending; int offset; struct pl061_gpio *chip = irq_desc_get_handler_data(desc); struct irq_chip *irqchip = irq_desc_get_chip(desc); chained_irq_enter(irqchip, desc); pending = readb(chip->base + GPIOMIS); writeb(pending, chip->base + GPIOIC); if (pending) { for_each_set_bit(offset, &pending, PL061_GPIO_NR) generic_handle_irq(pl061_to_irq(&chip->gc, offset)); } chained_irq_exit(irqchip, desc); }
static void mx25_tsadc_irq_handler(struct irq_desc *desc) { struct mx25_tsadc *tsadc = irq_desc_get_handler_data(desc); struct irq_chip *chip = irq_desc_get_chip(desc); u32 status; chained_irq_enter(chip, desc); regmap_read(tsadc->regs, MX25_TSC_TGSR, &status); if (status & MX25_TGSR_GCQ_INT) generic_handle_irq(irq_find_mapping(tsadc->domain, 1)); if (status & MX25_TGSR_TCQ_INT) generic_handle_irq(irq_find_mapping(tsadc->domain, 0)); chained_irq_exit(chip, desc); }
static void goldfish_pic_cascade(struct irq_desc *desc) { struct goldfish_pic_data *gfpic = irq_desc_get_handler_data(desc); struct irq_chip *host_chip = irq_desc_get_chip(desc); u32 pending, hwirq, virq; chained_irq_enter(host_chip, desc); pending = readl(gfpic->base + GFPIC_REG_IRQ_PENDING); while (pending) { hwirq = __fls(pending); virq = irq_linear_revmap(gfpic->irq_domain, hwirq); generic_handle_irq(virq); pending &= ~(1 << hwirq); } chained_irq_exit(host_chip, desc); }
static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) { struct davinci_gpio_regs __iomem *g; u32 mask = 0xffff; struct davinci_gpio_controller *d; d = (struct davinci_gpio_controller *)irq_desc_get_handler_data(desc); g = (struct davinci_gpio_regs __iomem *)d->regs; if (irq & 1) mask <<= 16; desc->irq_data.chip->irq_mask(&desc->irq_data); desc->irq_data.chip->irq_ack(&desc->irq_data); while (1) { u32 status; int n; int res; status = __raw_readl(&g->intstat) & mask; if (!status) break; __raw_writel(status, &g->intstat); n = d->irq_base; if (irq & 1) { n += 16; status >>= 16; } while (status) { res = ffs(status); n += res; generic_handle_irq(n - 1); status >>= res; } }
static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) { struct davinci_gpio_regs __iomem *g; u32 mask = 0xffff; struct davinci_gpio_controller *d; d = (struct davinci_gpio_controller *)irq_desc_get_handler_data(desc); g = (struct davinci_gpio_regs __iomem *)d->regs; /* we only care about one bank */ if (irq & 1) mask <<= 16; /* temporarily mask (level sensitive) parent IRQ */ desc->irq_data.chip->irq_mask(&desc->irq_data); desc->irq_data.chip->irq_ack(&desc->irq_data); while (1) { u32 status; int n; int res; /* ack any irqs */ status = __raw_readl(&g->intstat) & mask; if (!status) break; __raw_writel(status, &g->intstat); /* now demux them to the right lowlevel handler */ n = d->irq_base; if (irq & 1) { n += 16; status >>= 16; } while (status) { res = ffs(status); n += res; generic_handle_irq(n - 1); status >>= res; } }