static int s5p64x0_alloc_gc(void) { struct irq_chip_generic *gc; struct irq_chip_type *ct; gc = irq_alloc_generic_chip("s5p64x0-eint", 1, S5P_IRQ_EINT_BASE, S5P_VA_GPIO, handle_level_irq); if (!gc) { printk(KERN_ERR "%s: irq_alloc_generic_chip for group 0" "external interrupts failed\n", __func__); return -EINVAL; } ct = gc->chip_types; ct->chip.irq_ack = irq_gc_ack_set_bit; ct->chip.irq_mask = irq_gc_mask_set_bit; ct->chip.irq_unmask = irq_gc_mask_clr_bit; ct->chip.irq_set_type = s5p64x0_irq_eint_set_type; ct->chip.irq_set_wake = s3c_irqext_wake; ct->regs.ack = EINT0PEND_OFFSET; ct->regs.mask = EINT0MASK_OFFSET; irq_setup_generic_chip(gc, IRQ_MSK(16), IRQ_GC_INIT_MASK_CACHE, IRQ_NOREQUEST | IRQ_NOPROBE, 0); return 0; }
/** * s3c_init_vic_timer_irq() - initialise timer irq chanined off VIC.\ * @num: Number of timers to initialize * @timer_irq: Base IRQ number to be used for the timers. * * Register the necessary IRQ chaining and support for the timer IRQs * chained of the VIC. */ void __init s3c_init_vic_timer_irq(unsigned int num, unsigned int timer_irq) { unsigned int pirq[5] = { IRQ_TIMER0_VIC, IRQ_TIMER1_VIC, IRQ_TIMER2_VIC, IRQ_TIMER3_VIC, IRQ_TIMER4_VIC }; struct irq_chip_generic *s3c_tgc; struct irq_chip_type *ct; unsigned int i; s3c_tgc = irq_alloc_generic_chip("s3c-timer", 1, timer_irq, S3C64XX_TINT_CSTAT, handle_level_irq); if (!s3c_tgc) { pr_err("%s: irq_alloc_generic_chip for IRQ %d failed\n", __func__, timer_irq); return; } ct = s3c_tgc->chip_types; ct->chip.irq_mask = irq_gc_mask_clr_bit; ct->chip.irq_unmask = irq_gc_mask_set_bit; ct->chip.irq_ack = s3c_irq_timer_ack; irq_setup_generic_chip(s3c_tgc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, IRQ_NOREQUEST | IRQ_NOPROBE, 0); /* Clear the upper bits of the mask_cache*/ s3c_tgc->mask_cache &= 0x1f; for (i = 0; i < num; i++, timer_irq++) { irq_set_chained_handler(pirq[i], s3c_irq_demux_vic_timer); irq_set_handler_data(pirq[i], (void *)timer_irq); } }
void __init arch_init_irq(void) { struct irq_chip_generic *gc; struct irq_chip_type *ct; mips_cpu_irq_init(); jz_intc_base = ioremap(JZ4740_INTC_BASE_ADDR, 0x14); /* Mask all irqs */ writel(0xffffffff, jz_intc_base + JZ_REG_INTC_SET_MASK); gc = irq_alloc_generic_chip("INTC", 1, JZ4740_IRQ_BASE, jz_intc_base, handle_level_irq); gc->wake_enabled = IRQ_MSK(32); ct = gc->chip_types; ct->regs.enable = JZ_REG_INTC_CLEAR_MASK; ct->regs.disable = JZ_REG_INTC_SET_MASK; ct->chip.irq_unmask = irq_gc_unmask_enable_reg; ct->chip.irq_mask = irq_gc_mask_disable_reg; ct->chip.irq_mask_ack = irq_gc_mask_disable_reg; ct->chip.irq_set_wake = irq_gc_set_wake; ct->chip.irq_suspend = jz4740_irq_suspend; ct->chip.irq_resume = jz4740_irq_resume; irq_setup_generic_chip(gc, IRQ_MSK(32), 0, 0, IRQ_NOPROBE | IRQ_LEVEL); setup_irq(2, &jz4740_cascade_action); }
static void __init or1k_irq_init(void) { struct irq_chip_generic *gc; struct irq_chip_type *ct; /* Disable all interrupts until explicitly requested */ mtspr(SPR_PICMR, (0UL)); gc = irq_alloc_generic_chip("or1k-PIC", 1, 0, 0, handle_level_irq); ct = gc->chip_types; ct->chip.irq_unmask = or1k_pic_unmask; ct->chip.irq_mask = or1k_pic_mask; ct->chip.irq_ack = or1k_pic_ack; ct->chip.irq_mask_ack = or1k_pic_mask_ack; ct->chip.irq_set_type = or1k_pic_set_type; /* The OR1K PIC can handle both level and edge trigged * interrupts in roughly the same manner */ #if 0 /* FIXME: chip.type??? */ ct->chip.type = IRQ_TYPE_EDGE_BOTH | IRQ_TYPE_LEVEL_MASK; #endif irq_setup_generic_chip(gc, IRQ_MSK(NR_IRQS), 0, IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE); }
static void __init s3c_init_uart_irq(struct s3c_uart_irq *uirq) { void __iomem *reg_base = uirq->regs; struct irq_chip_generic *gc; struct irq_chip_type *ct; /* mask all interrupts at the start. */ __raw_writel(0xf, reg_base + S3C64XX_UINTM); gc = irq_alloc_generic_chip("s3c-uart", 1, uirq->base_irq, reg_base, handle_level_irq); if (!gc) { pr_err("%s: irq_alloc_generic_chip for IRQ %u failed\n", __func__, uirq->base_irq); return; } ct = gc->chip_types; ct->chip.irq_ack = irq_gc_ack_set_bit; ct->chip.irq_mask = irq_gc_mask_set_bit; ct->chip.irq_unmask = irq_gc_mask_clr_bit; ct->chip.irq_mask_ack = irq_gc_mask_and_ack_set; ct->chip.irq_disable = irq_gc_mask_and_ack_set; ct->regs.ack = S3C64XX_UINTP; ct->regs.mask = S3C64XX_UINTM; irq_setup_generic_chip(gc, IRQ_MSK(4), IRQ_GC_INIT_MASK_CACHE, IRQ_NOREQUEST | IRQ_NOPROBE, 0); irq_set_handler_data(uirq->parent_irq, uirq); irq_set_chained_handler(uirq->parent_irq, s3c_irq_demux_uart); }
static __init void sirfsoc_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num) { struct irq_chip_generic *gc; struct irq_chip_type *ct; gc = irq_alloc_generic_chip("SIRFINTC", 1, irq_start, base, handle_level_irq); ct = gc->chip_types; ct->chip.irq_mask = irq_gc_mask_clr_bit; ct->chip.irq_unmask = irq_gc_mask_set_bit; ct->regs.mask = SIRFSOC_INT_RISC_MASK0; irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, IRQ_NOREQUEST, 0); }
static __init void davinci_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num) { struct irq_chip_generic *gc; struct irq_chip_type *ct; gc = irq_alloc_generic_chip("AINTC", 1, irq_start, base, handle_edge_irq); ct = gc->chip_types; ct->chip.irq_ack = irq_gc_ack; ct->chip.irq_mask = irq_gc_mask_clr_bit; ct->chip.irq_unmask = irq_gc_mask_set_bit; ct->regs.ack = IRQ_REG0_OFFSET; ct->regs.mask = IRQ_ENT_REG0_OFFSET; irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, IRQ_NOREQUEST | IRQ_NOPROBE, 0); }
void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr) { struct irq_chip_generic *gc; struct irq_chip_type *ct; /* * Mask all interrupts initially. */ writel(0, maskaddr); gc = irq_alloc_generic_chip("orion_irq", 1, irq_start, maskaddr, handle_level_irq); ct = gc->chip_types; ct->chip.irq_mask = irq_gc_mask_clr_bit; ct->chip.irq_unmask = irq_gc_mask_set_bit; irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_MASK_CACHE, IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE); }
static void __init omap_alloc_gc_legacy(void __iomem *base, unsigned int irq_start, unsigned int num) { struct irq_chip_generic *gc; struct irq_chip_type *ct; gc = irq_alloc_generic_chip("INTC", 1, irq_start, base, handle_level_irq); ct = gc->chip_types; ct->chip.irq_ack = omap_mask_ack_irq; ct->chip.irq_mask = irq_gc_mask_disable_reg; ct->chip.irq_unmask = irq_gc_unmask_enable_reg; ct->chip.flags |= IRQCHIP_SKIP_SET_WAKE; ct->regs.enable = INTC_MIR_CLEAR0; ct->regs.disable = INTC_MIR_SET0; irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, IRQ_NOREQUEST | IRQ_NOPROBE, 0); }
static void __init mcs814x_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num) { struct irq_chip_generic *gc; struct irq_chip_type *ct; gc = irq_alloc_generic_chip("mcs814x-intc", 1, irq_start, base, handle_level_irq); if (!gc) panic("unable to allocate generic irq chip"); ct = gc->chip_types; ct->chip.irq_ack = irq_gc_unmask_enable_reg; ct->chip.irq_mask = irq_gc_mask_clr_bit; ct->chip.irq_unmask = irq_gc_mask_set_bit; ct->regs.mask = MCS814X_IRQ_MASK; ct->regs.enable = MCS814X_IRQ_ICR; irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, IRQ_NOREQUEST, 0); /* Clear all interrupts */ writel_relaxed(0xffffffff, base + MCS814X_IRQ_ICR); }
static int jz4740_adc_probe(struct platform_device *pdev) { struct irq_chip_generic *gc; struct irq_chip_type *ct; struct jz4740_adc *adc; struct resource *mem_base; int ret; int irq_base; adc = devm_kzalloc(&pdev->dev, sizeof(*adc), GFP_KERNEL); if (!adc) { dev_err(&pdev->dev, "Failed to allocate driver structure\n"); return -ENOMEM; } adc->irq = platform_get_irq(pdev, 0); if (adc->irq < 0) { ret = adc->irq; dev_err(&pdev->dev, "Failed to get platform irq: %d\n", ret); return ret; } irq_base = platform_get_irq(pdev, 1); if (irq_base < 0) { dev_err(&pdev->dev, "Failed to get irq base: %d\n", irq_base); return irq_base; } mem_base = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!mem_base) { dev_err(&pdev->dev, "Failed to get platform mmio resource\n"); return -ENOENT; } /* Only request the shared registers for the MFD driver */ adc->mem = request_mem_region(mem_base->start, JZ_REG_ADC_STATUS, pdev->name); if (!adc->mem) { dev_err(&pdev->dev, "Failed to request mmio memory region\n"); return -EBUSY; } adc->base = ioremap_nocache(adc->mem->start, resource_size(adc->mem)); if (!adc->base) { ret = -EBUSY; dev_err(&pdev->dev, "Failed to ioremap mmio memory\n"); goto err_release_mem_region; } adc->clk = clk_get(&pdev->dev, "adc"); if (IS_ERR(adc->clk)) { ret = PTR_ERR(adc->clk); dev_err(&pdev->dev, "Failed to get clock: %d\n", ret); goto err_iounmap; } spin_lock_init(&adc->lock); atomic_set(&adc->clk_ref, 0); platform_set_drvdata(pdev, adc); gc = irq_alloc_generic_chip("INTC", 1, irq_base, adc->base, handle_level_irq); ct = gc->chip_types; ct->regs.mask = JZ_REG_ADC_CTRL; ct->regs.ack = JZ_REG_ADC_STATUS; ct->chip.irq_mask = irq_gc_mask_set_bit; ct->chip.irq_unmask = irq_gc_mask_clr_bit; ct->chip.irq_ack = irq_gc_ack_set_bit; irq_setup_generic_chip(gc, IRQ_MSK(5), IRQ_GC_INIT_MASK_CACHE, 0, IRQ_NOPROBE | IRQ_LEVEL); adc->gc = gc; irq_set_chained_handler_and_data(adc->irq, jz4740_adc_irq_demux, gc); writeb(0x00, adc->base + JZ_REG_ADC_ENABLE); writeb(0xff, adc->base + JZ_REG_ADC_CTRL); ret = mfd_add_devices(&pdev->dev, 0, jz4740_adc_cells, ARRAY_SIZE(jz4740_adc_cells), mem_base, irq_base, NULL); if (ret < 0) goto err_clk_put; return 0; err_clk_put: clk_put(adc->clk); err_iounmap: iounmap(adc->base); err_release_mem_region: release_mem_region(adc->mem->start, resource_size(adc->mem)); return ret; }
static int __init goldfish_pic_of_init(struct device_node *of_node, struct device_node *parent) { struct goldfish_pic_data *gfpic; struct irq_chip_generic *gc; struct irq_chip_type *ct; unsigned int parent_irq; int ret = 0; gfpic = kzalloc(sizeof(*gfpic), GFP_KERNEL); if (!gfpic) { ret = -ENOMEM; goto out_err; } parent_irq = irq_of_parse_and_map(of_node, 0); if (!parent_irq) { pr_err("Failed to map parent IRQ!\n"); ret = -EINVAL; goto out_free; } gfpic->base = of_iomap(of_node, 0); if (!gfpic->base) { pr_err("Failed to map base address!\n"); ret = -ENOMEM; goto out_unmap_irq; } /* Mask interrupts. */ writel(1, gfpic->base + GFPIC_REG_IRQ_DISABLE_ALL); gc = irq_alloc_generic_chip("GFPIC", 1, GFPIC_IRQ_BASE, gfpic->base, handle_level_irq); if (!gc) { pr_err("Failed to allocate chip structures!\n"); ret = -ENOMEM; goto out_iounmap; } ct = gc->chip_types; ct->regs.enable = GFPIC_REG_IRQ_ENABLE; ct->regs.disable = GFPIC_REG_IRQ_DISABLE; ct->chip.irq_unmask = irq_gc_unmask_enable_reg; ct->chip.irq_mask = irq_gc_mask_disable_reg; irq_setup_generic_chip(gc, IRQ_MSK(GFPIC_NR_IRQS), 0, IRQ_NOPROBE | IRQ_LEVEL, 0); gfpic->irq_domain = irq_domain_add_legacy(of_node, GFPIC_NR_IRQS, GFPIC_IRQ_BASE, 0, &goldfish_irq_domain_ops, NULL); if (!gfpic->irq_domain) { pr_err("Failed to add irqdomain!\n"); ret = -ENOMEM; goto out_destroy_generic_chip; } irq_set_chained_handler_and_data(parent_irq, goldfish_pic_cascade, gfpic); pr_info("Successfully registered.\n"); return 0; out_destroy_generic_chip: irq_destroy_generic_chip(gc, IRQ_MSK(GFPIC_NR_IRQS), IRQ_NOPROBE | IRQ_LEVEL, 0); out_iounmap: iounmap(gfpic->base); out_unmap_irq: irq_dispose_mapping(parent_irq); out_free: kfree(gfpic); out_err: pr_err("Failed to initialize! (errno = %d)\n", ret); return ret; }