/*
* The shift value is now the number of bits to shift, not the number of
* bits/4. This is to make it easier to read the value directly from the
* datasheets. The IPR address is calculated using the ipr_offset table.
*/
void register_ipr_controller(struct ipr_desc *desc)
{
int i;
desc->chip.mask = disable_ipr_irq;
desc->chip.unmask = enable_ipr_irq;
desc->chip.mask_ack = disable_ipr_irq;
for (i = 0; i < desc->nr_irqs; i++) {
struct ipr_data *p = desc->ipr_data + i;
struct irq_desc *irq_desc;
BUG_ON(p->ipr_idx >= desc->nr_offsets);
BUG_ON(!desc->ipr_offsets[p->ipr_idx]);
irq_desc = irq_to_desc_alloc_node(p->irq, numa_node_id());
if (unlikely(!irq_desc)) {
printk(KERN_INFO "can not get irq_desc for %d\n",
p->irq);
continue;
}
disable_irq_nosync(p->irq);
set_irq_chip_and_handler_name(p->irq, &desc->chip,
handle_level_irq, "level");
set_irq_chip_data(p->irq, p);
disable_ipr_irq(p->irq);
}
}
static int pcifront_enable_irq(struct pci_dev *dev)
{
u8 irq;
pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
irq_to_desc_alloc_node(irq, numa_node_id());
evtchn_register_pirq(irq);
dev->irq = irq;
return 0;
}
void lguest_setup_irq(unsigned int irq)
{
irq_to_desc_alloc_node(irq, 0);
set_irq_chip_and_handler_name(irq, &lguest_irq_controller,
handle_level_irq, "level");
}
