strvec MtxLP::getEssentials(stomap* obj, strvec q, bool max, bool presolve){ strvec rv; for (strvec::iterator it = q.begin(); it != q.end(); ++it){ if (isEssential(obj, *it, max, presolve)) rv.push_back(*it); } return rv; }
void initInstructions(Trace* trace, IRInstruction::List& wl) { IRInstruction::List instructions = trace->getInstructionList(); IRInstruction::Iterator it; bool unreachable = false; TRACE(5, "DCE:vvvvvvvvvvvvvvvvvvvv\n"); for (it = instructions.begin(); it != instructions.end(); it++) { IRInstruction* inst = *it; ASSERT(inst->getParent() == trace); Simplifier::copyProp(inst); // if this is a load that does not generate a guard, then get rid // of its label so that its not an essential control-flow // instruction if (isUnguardedLoad(inst)) { // LdStack and LdLoc instructions that produce generic types // and LdStack instruction that produce Cell types will not // generate guards, so remove the label from this instruction so // that its no longer an essential control-flow instruction inst->setLabel(NULL); } Opcode opc = inst->getOpcode(); // decref of anything that isn't ref counted is a nop if ((opc == DecRef || opc == DecRefNZ) && !isRefCounted(inst->getSrc(0))) { inst->setId(DEAD); continue; } if (!unreachable && inst->isControlFlowInstruction()) { // mark the destination label so that the destination trace // is marked reachable inst->getLabel()->setId(LIVE); } if (!unreachable && isEssential(inst)) { inst->setId(LIVE); wl.push_back(inst); } else { if (moduleEnabled(HPHP::Trace::hhir, 5)) { std::ostringstream ss1; inst->printSrcs(ss1); TRACE(5, "DCE: %s\n", ss1.str().c_str()); std::ostringstream ss2; inst->print(ss2); TRACE(5, "DCE: %s\n", ss2.str().c_str()); } inst->setId(DEAD); } if (inst->getOpcode() == Jmp_) { unreachable = true; } } TRACE(5, "DCE:^^^^^^^^^^^^^^^^^^^^\n"); }