static void put_cpsr(QEMUFile *f, void *opaque, size_t size)
{
ARMCPU *cpu = opaque;
CPUARMState *env = &cpu->env;
uint32_t val;
if (is_a64(env)) {
val = pstate_read(env);
} else {
val = cpsr_read(env);
}
qemu_put_be32(f, val);
}
static void aarch64_cpu_set_pc(CPUState *cs, vaddr value)
{
CPUARMState *env = cs->env_ptr;
ARMCPU *cpu = ARM_CPU(env->uc, cs);
/* It's OK to look at env for the current mode here, because it's
* never possible for an AArch64 TB to chain to an AArch32 TB.
* (Otherwise we would need to use synchronize_from_tb instead.)
*/
if (is_a64(&cpu->env)) {
cpu->env.pc = value;
} else {
cpu->env.regs[15] = value;
}
}
bool arm_is_psci_call(ARMCPU *cpu, int excp_type)
{
/* Return true if the r0/x0 value indicates a PSCI call and
* the exception type matches the configured PSCI conduit. This is
* called before the SMC/HVC instruction is executed, to decide whether
* we should treat it as a PSCI call or with the architecturally
* defined behaviour for an SMC or HVC (which might be UNDEF or trap
* to EL2 or to EL3).
*/
CPUARMState *env = &cpu->env;
uint64_t param = is_a64(env) ? env->xregs[0] : env->regs[0];
switch (excp_type) {
case EXCP_HVC:
if (cpu->psci_conduit != QEMU_PSCI_CONDUIT_HVC) {
return false;
}
break;
case EXCP_SMC:
if (cpu->psci_conduit != QEMU_PSCI_CONDUIT_SMC) {
return false;
}
break;
default:
return false;
}
switch (param) {
case QEMU_PSCI_0_2_FN_PSCI_VERSION:
case QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE:
case QEMU_PSCI_0_2_FN_AFFINITY_INFO:
case QEMU_PSCI_0_2_FN64_AFFINITY_INFO:
case QEMU_PSCI_0_2_FN_SYSTEM_RESET:
case QEMU_PSCI_0_2_FN_SYSTEM_OFF:
case QEMU_PSCI_0_1_FN_CPU_ON:
case QEMU_PSCI_0_2_FN_CPU_ON:
case QEMU_PSCI_0_2_FN64_CPU_ON:
case QEMU_PSCI_0_1_FN_CPU_OFF:
case QEMU_PSCI_0_2_FN_CPU_OFF:
case QEMU_PSCI_0_1_FN_CPU_SUSPEND:
case QEMU_PSCI_0_2_FN_CPU_SUSPEND:
case QEMU_PSCI_0_2_FN64_CPU_SUSPEND:
case QEMU_PSCI_0_1_FN_MIGRATE:
case QEMU_PSCI_0_2_FN_MIGRATE:
return true;
default:
return false;
}
}
int aarch64_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
{
ARMCPU *cpu = ARM_CPU(cs);
CPUARMState *env = &cpu->env;
#ifndef CONFIG_USER_ONLY
if (!is_a64(env)) {
map_a32_to_a64_regs(env);
}
#endif
if (n < 31) {
/* Core integer register. */
return gdb_get_reg64(mem_buf, env->xregs[n]);
}
switch (n) {
case 31:
{
unsigned int cur_el = arm_current_el(env);
uint64_t sp;
aarch64_save_sp(env, cur_el);
switch (env->debug_ctx) {
case DEBUG_EL0:
sp = env->sp_el[0];
break;
case DEBUG_EL1:
sp = env->sp_el[1];
break;
case DEBUG_EL2:
sp = env->sp_el[2];
break;
case DEBUG_EL3:
sp = env->sp_el[3];
break;
default:
sp = env->xregs[31];
break;
}
return gdb_get_reg64(mem_buf, sp);
}
case 32:
return gdb_get_reg64(mem_buf, env->pc);
case 33:
return gdb_get_reg32(mem_buf, pstate_read(env));
}
/* Unknown register. */
return 0;
}
static int get_cpsr(QEMUFile *f, void *opaque, size_t size)
{
ARMCPU *cpu = opaque;
CPUARMState *env = &cpu->env;
uint32_t val = qemu_get_be32(f);
env->aarch64 = ((val & PSTATE_nRW) == 0);
if (is_a64(env)) {
pstate_write(env, val);
return 0;
}
cpsr_write(env, val, 0xffffffff, CPSRWriteRaw);
return 0;
}
static int get_cpsr(QEMUFile *f, void *opaque, size_t size)
{
ARMCPU *cpu = opaque;
CPUARMState *env = &cpu->env;
uint32_t val = qemu_get_be32(f);
env->aarch64 = ((val & PSTATE_nRW) == 0);
if (is_a64(env)) {
pstate_write(env, val);
return 0;
}
/* Avoid mode switch when restoring CPSR */
env->uncached_cpsr = val & CPSR_M;
cpsr_write(env, val, 0xffffffff);
return 0;
}
void arm_handle_psci_call(ARMCPU *cpu)
{
/*
* This function partially implements the logic for dispatching Power State
* Coordination Interface (PSCI) calls (as described in ARM DEN 0022B.b),
* to the extent required for bringing up and taking down secondary cores,
* and for handling reset and poweroff requests.
* Additional information about the calling convention used is available in
* the document 'SMC Calling Convention' (ARM DEN 0028)
*/
CPUARMState *env = &cpu->env;
uint64_t param[4];
uint64_t context_id, mpidr;
target_ulong entry;
int32_t ret = 0;
int i;
for (i = 0; i < 4; i++) {
/*
* All PSCI functions take explicit 32-bit or native int sized
* arguments so we can simply zero-extend all arguments regardless
* of which exact function we are about to call.
*/
param[i] = is_a64(env) ? env->xregs[i] : env->regs[i];
}
if ((param[0] & QEMU_PSCI_0_2_64BIT) && !is_a64(env)) {
ret = QEMU_PSCI_RET_INVALID_PARAMS;
goto err;
}
switch (param[0]) {
CPUState *target_cpu_state;
ARMCPU *target_cpu;
case QEMU_PSCI_0_2_FN_PSCI_VERSION:
ret = QEMU_PSCI_0_2_RET_VERSION_0_2;
break;
case QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE:
ret = QEMU_PSCI_0_2_RET_TOS_MIGRATION_NOT_REQUIRED; /* No trusted OS */
break;
case QEMU_PSCI_0_2_FN_AFFINITY_INFO:
case QEMU_PSCI_0_2_FN64_AFFINITY_INFO:
mpidr = param[1];
switch (param[2]) {
case 0:
target_cpu_state = arm_get_cpu_by_id(mpidr);
if (!target_cpu_state) {
ret = QEMU_PSCI_RET_INVALID_PARAMS;
break;
}
target_cpu = ARM_CPU(target_cpu_state);
g_assert(qemu_mutex_iothread_locked());
ret = target_cpu->power_state;
break;
default:
/* Everything above affinity level 0 is always on. */
ret = 0;
}
break;
case QEMU_PSCI_0_2_FN_SYSTEM_RESET:
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
/* QEMU reset and shutdown are async requests, but PSCI
* mandates that we never return from the reset/shutdown
* call, so power the CPU off now so it doesn't execute
* anything further.
*/
goto cpu_off;
case QEMU_PSCI_0_2_FN_SYSTEM_OFF:
qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
goto cpu_off;
case QEMU_PSCI_0_1_FN_CPU_ON:
case QEMU_PSCI_0_2_FN_CPU_ON:
case QEMU_PSCI_0_2_FN64_CPU_ON:
{
/* The PSCI spec mandates that newly brought up CPUs start
* in the highest exception level which exists and is enabled
* on the calling CPU. Since the QEMU PSCI implementation is
* acting as a "fake EL3" or "fake EL2" firmware, this for us
* means that we want to start at the highest NS exception level
* that we are providing to the guest.
* The execution mode should be that which is currently in use
* by the same exception level on the calling CPU.
* The CPU should be started with the context_id value
* in x0 (if AArch64) or r0 (if AArch32).
*/
int target_el = arm_feature(env, ARM_FEATURE_EL2) ? 2 : 1;
bool target_aarch64 = arm_el_is_aa64(env, target_el);
mpidr = param[1];
entry = param[2];
context_id = param[3];
ret = arm_set_cpu_on(mpidr, entry, context_id,
target_el, target_aarch64);
break;
}
case QEMU_PSCI_0_1_FN_CPU_OFF:
case QEMU_PSCI_0_2_FN_CPU_OFF:
goto cpu_off;
case QEMU_PSCI_0_1_FN_CPU_SUSPEND:
case QEMU_PSCI_0_2_FN_CPU_SUSPEND:
case QEMU_PSCI_0_2_FN64_CPU_SUSPEND:
/* Affinity levels are not supported in QEMU */
if (param[1] & 0xfffe0000) {
ret = QEMU_PSCI_RET_INVALID_PARAMS;
break;
}
/* Powerdown is not supported, we always go into WFI */
if (is_a64(env)) {
env->xregs[0] = 0;
} else {
env->regs[0] = 0;
}
helper_wfi(env, 4);
break;
case QEMU_PSCI_0_1_FN_MIGRATE:
case QEMU_PSCI_0_2_FN_MIGRATE:
ret = QEMU_PSCI_RET_NOT_SUPPORTED;
break;
default:
g_assert_not_reached();
}
err:
if (is_a64(env)) {
env->xregs[0] = ret;
} else {
env->regs[0] = ret;
}
return;
cpu_off:
ret = arm_set_cpu_off(cpu->mp_affinity);
/* notreached */
/* sanity check in case something failed */
assert(ret == QEMU_ARM_POWERCTL_RET_SUCCESS);
}
int aarch64_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
{
ARMCPU *cpu = ARM_CPU(cs);
CPUARMState *env = &cpu->env;
uint64_t tmp;
int rlen = 0;
#ifndef CONFIG_USER_ONLY
if (!is_a64(env)) {
map_a32_to_a64_regs(env);
}
#endif
tmp = ldq_p(mem_buf);
if (n < 31) {
/* Core integer register. */
env->xregs[n] = tmp;
rlen = 8;
}
switch (n) {
case 31: {
unsigned int cur_el = arm_current_el(env);
aarch64_save_sp(env, cur_el);
switch (env->debug_ctx) {
case DEBUG_EL0:
env->sp_el[0] = tmp;
break;
case DEBUG_EL1:
env->sp_el[1] = tmp;
break;
case DEBUG_EL2:
env->sp_el[2] = tmp;
break;
case DEBUG_EL3:
env->sp_el[3] = tmp;
break;
default:
env->xregs[31] = tmp;
break;
}
aarch64_restore_sp(env, cur_el);
rlen = 8;
break;
}
case 32:
env->pc = tmp;
rlen = 8;
break;
case 33:
/* CPSR */
pstate_write(env, tmp);
rlen = 4;
break;
}
#ifndef CONFIG_USER_ONLY
if (!is_a64(env)) {
map_a64_to_a32_regs(env);
}
#endif
/* Unknown register. */
return rlen;
}