int sched_init_vcpu(struct vcpu *v, unsigned int processor)
{
struct domain *d = v->domain;
/*
* Initialize processor and affinity settings. The idler, and potentially
* domain-0 VCPUs, are pinned onto their respective physical CPUs.
*/
v->processor = processor;
if ( is_idle_domain(d) || d->is_pinned )
v->cpu_affinity = cpumask_of_cpu(processor);
else
cpus_setall(v->cpu_affinity);
/* Initialise the per-vcpu timers. */
init_timer(&v->periodic_timer, vcpu_periodic_timer_fn,
v, v->processor);
init_timer(&v->singleshot_timer, vcpu_singleshot_timer_fn,
v, v->processor);
init_timer(&v->poll_timer, poll_timer_fn,
v, v->processor);
/* Idle VCPUs are scheduled immediately. */
if ( is_idle_domain(d) )
{
per_cpu(schedule_data, v->processor).curr = v;
per_cpu(schedule_data, v->processor).idle = v;
v->is_running = 1;
}
TRACE_2D(TRC_SCHED_DOM_ADD, v->domain->domain_id, v->vcpu_id);
return SCHED_OP(init_vcpu, v);
}
int arch_domain_create(struct domain *d, unsigned int domcr_flags)
{
int rc;
d->arch.relmem = RELMEM_not_started;
/* Idle domains do not need this setup */
if ( is_idle_domain(d) )
return 0;
if ( (rc = p2m_init(d)) != 0 )
goto fail;
rc = -ENOMEM;
if ( (d->shared_info = alloc_xenheap_pages(0, 0)) == NULL )
goto fail;
/* Default the virtual ID to match the physical */
d->arch.vpidr = boot_cpu_data.midr.bits;
clear_page(d->shared_info);
share_xen_page_with_guest(
virt_to_page(d->shared_info), d, XENSHARE_writable);
if ( (rc = p2m_alloc_table(d)) != 0 )
goto fail;
if ( (rc = gicv_setup(d)) != 0 )
goto fail;
if ( (rc = domain_vgic_init(d)) != 0 )
goto fail;
if ( (rc = domain_vtimer_init(d)) != 0 )
goto fail;
if ( d->domain_id )
d->arch.evtchn_irq = GUEST_EVTCHN_PPI;
else
d->arch.evtchn_irq = platform_dom0_evtchn_ppi();
/*
* Virtual UART is only used by linux early printk and decompress code.
* Only use it for the hardware domain because the linux kernel may not
* support multi-platform.
*/
if ( is_hardware_domain(d) && (rc = domain_vuart_init(d)) )
goto fail;
if ( (rc = iommu_domain_init(d)) != 0 )
goto fail;
return 0;
fail:
d->is_dying = DOMDYING_dead;
arch_domain_destroy(d);
return rc;
}
void p2m_load_VTTBR(struct domain *d)
{
if ( is_idle_domain(d) )
return;
BUG_ON(!d->arch.vttbr);
WRITE_SYSREG64(d->arch.vttbr, VTTBR_EL2);
isb(); /* Ensure update is visible */
}
int sched_init_vcpu(struct vcpu *v, unsigned int processor)
{
struct domain *d = v->domain;
/*
* Initialize processor and affinity settings. The idler, and potentially
* domain-0 VCPUs, are pinned onto their respective physical CPUs.
*/
v->processor = processor;
if ( is_idle_domain(d) || d->is_pinned )
cpumask_copy(v->cpu_hard_affinity, cpumask_of(processor));
else
cpumask_setall(v->cpu_hard_affinity);
cpumask_setall(v->cpu_soft_affinity);
/* Initialise the per-vcpu timers. */
init_timer(&v->periodic_timer, vcpu_periodic_timer_fn,
v, v->processor);
init_timer(&v->singleshot_timer, vcpu_singleshot_timer_fn,
v, v->processor);
init_timer(&v->poll_timer, poll_timer_fn,
v, v->processor);
/* Idle VCPUs are scheduled immediately. */
if ( is_idle_domain(d) )
{
per_cpu(schedule_data, v->processor).curr = v;
v->is_running = 1;
}
TRACE_2D(TRC_SCHED_DOM_ADD, v->domain->domain_id, v->vcpu_id);
v->sched_priv = SCHED_OP(DOM2OP(d), alloc_vdata, v, d->sched_priv);
if ( v->sched_priv == NULL )
return 1;
SCHED_OP(DOM2OP(d), insert_vcpu, v);
return 0;
}
int virt_timer_restore(struct vcpu *v)
{
if ( is_idle_domain(v->domain) )
return 0;
stop_timer(&v->arch.virt_timer.timer);
WRITE_SYSREG64(v->arch.virt_timer.offset, CNTVOFF_EL2);
WRITE_SYSREG64(v->arch.virt_timer.cval, CNTV_CVAL_EL0);
WRITE_SYSREG32(v->arch.virt_timer.ctl, CNTV_CTL_EL0);
return 0;
}
int virt_timer_save(struct vcpu *v)
{
if ( is_idle_domain(v->domain) )
return 0;
v->arch.virt_timer.ctl = READ_SYSREG32(CNTV_CTL_EL0);
WRITE_SYSREG32(v->arch.virt_timer.ctl & ~CNTx_CTL_ENABLE, CNTV_CTL_EL0);
v->arch.virt_timer.cval = READ_SYSREG64(CNTV_CVAL_EL0);
if ( v->arch.virt_timer.ctl & CNTx_CTL_ENABLE )
{
set_timer(&v->arch.virt_timer.timer, ticks_to_ns(v->arch.virt_timer.cval +
v->arch.virt_timer.offset - boot_count));
}
return 0;
}
struct domain *domain_create(
domid_t domid, unsigned int domcr_flags, uint32_t ssidref)
{
struct domain *d, **pd;
enum { INIT_xsm = 1u<<0, INIT_watchdog = 1u<<1, INIT_rangeset = 1u<<2,
INIT_evtchn = 1u<<3, INIT_gnttab = 1u<<4, INIT_arch = 1u<<5 };
int err, init_status = 0;
int poolid = CPUPOOLID_NONE;
if ( (d = alloc_domain_struct()) == NULL )
return ERR_PTR(-ENOMEM);
d->domain_id = domid;
lock_profile_register_struct(LOCKPROF_TYPE_PERDOM, d, domid, "Domain");
if ( (err = xsm_alloc_security_domain(d)) != 0 )
goto fail;
init_status |= INIT_xsm;
watchdog_domain_init(d);
init_status |= INIT_watchdog;
atomic_set(&d->refcnt, 1);
spin_lock_init_prof(d, domain_lock);
spin_lock_init_prof(d, page_alloc_lock);
spin_lock_init(&d->hypercall_deadlock_mutex);
INIT_PAGE_LIST_HEAD(&d->page_list);
INIT_PAGE_LIST_HEAD(&d->xenpage_list);
spin_lock_init(&d->node_affinity_lock);
d->node_affinity = NODE_MASK_ALL;
d->auto_node_affinity = 1;
spin_lock_init(&d->shutdown_lock);
d->shutdown_code = -1;
err = -ENOMEM;
if ( !zalloc_cpumask_var(&d->domain_dirty_cpumask) )
goto fail;
if ( domcr_flags & DOMCRF_hvm )
d->is_hvm = 1;
if ( domid == 0 )
{
d->is_pinned = opt_dom0_vcpus_pin;
d->disable_migrate = 1;
}
rangeset_domain_initialise(d);
init_status |= INIT_rangeset;
d->iomem_caps = rangeset_new(d, "I/O Memory", RANGESETF_prettyprint_hex);
d->irq_caps = rangeset_new(d, "Interrupts", 0);
if ( (d->iomem_caps == NULL) || (d->irq_caps == NULL) )
goto fail;
if ( domcr_flags & DOMCRF_dummy )
return d;
if ( !is_idle_domain(d) )
{
if ( (err = xsm_domain_create(XSM_HOOK, d, ssidref)) != 0 )
goto fail;
d->is_paused_by_controller = 1;
atomic_inc(&d->pause_count);
if ( domid )
d->nr_pirqs = nr_static_irqs + extra_domU_irqs;
else
d->nr_pirqs = nr_static_irqs + extra_dom0_irqs;
if ( d->nr_pirqs > nr_irqs )
d->nr_pirqs = nr_irqs;
radix_tree_init(&d->pirq_tree);
if ( (err = evtchn_init(d)) != 0 )
goto fail;
init_status |= INIT_evtchn;
if ( (err = grant_table_create(d)) != 0 )
goto fail;
init_status |= INIT_gnttab;
poolid = 0;
err = -ENOMEM;
d->mem_event = xzalloc(struct mem_event_per_domain);
if ( !d->mem_event )
goto fail;
}
if ( (err = arch_domain_create(d, domcr_flags)) != 0 )
goto fail;
init_status |= INIT_arch;
if ( (err = cpupool_add_domain(d, poolid)) != 0 )
goto fail;
if ( (err = sched_init_domain(d)) != 0 )
goto fail;
if ( !is_idle_domain(d) )
{
spin_lock(&domlist_update_lock);
pd = &domain_list; /* NB. domain_list maintained in order of domid. */
for ( pd = &domain_list; *pd != NULL; pd = &(*pd)->next_in_list )
if ( (*pd)->domain_id > d->domain_id )
break;
d->next_in_list = *pd;
d->next_in_hashbucket = domain_hash[DOMAIN_HASH(domid)];
rcu_assign_pointer(*pd, d);
rcu_assign_pointer(domain_hash[DOMAIN_HASH(domid)], d);
spin_unlock(&domlist_update_lock);
}
return d;
fail:
d->is_dying = DOMDYING_dead;
atomic_set(&d->refcnt, DOMAIN_DESTROYED);
xfree(d->mem_event);
if ( init_status & INIT_arch )
arch_domain_destroy(d);
if ( init_status & INIT_gnttab )
grant_table_destroy(d);
if ( init_status & INIT_evtchn )
{
evtchn_destroy(d);
evtchn_destroy_final(d);
radix_tree_destroy(&d->pirq_tree, free_pirq_struct);
}
if ( init_status & INIT_rangeset )
rangeset_domain_destroy(d);
if ( init_status & INIT_watchdog )
watchdog_domain_destroy(d);
if ( init_status & INIT_xsm )
xsm_free_security_domain(d);
free_cpumask_var(d->domain_dirty_cpumask);
free_domain_struct(d);
return ERR_PTR(err);
}
struct vcpu *alloc_vcpu(
struct domain *d, unsigned int vcpu_id, unsigned int cpu_id)
{
struct vcpu *v;
BUG_ON((!is_idle_domain(d) || vcpu_id) && d->vcpu[vcpu_id]);
if ( (v = alloc_vcpu_struct()) == NULL )
return NULL;
v->domain = d;
v->vcpu_id = vcpu_id;
spin_lock_init(&v->virq_lock);
tasklet_init(&v->continue_hypercall_tasklet, NULL, 0);
if ( !zalloc_cpumask_var(&v->cpu_affinity) ||
!zalloc_cpumask_var(&v->cpu_affinity_tmp) ||
!zalloc_cpumask_var(&v->cpu_affinity_saved) ||
!zalloc_cpumask_var(&v->vcpu_dirty_cpumask) )
goto fail_free;
if ( is_idle_domain(d) )
{
v->runstate.state = RUNSTATE_running;
}
else
{
v->runstate.state = RUNSTATE_offline;
v->runstate.state_entry_time = NOW();
set_bit(_VPF_down, &v->pause_flags);
v->vcpu_info = ((vcpu_id < XEN_LEGACY_MAX_VCPUS)
? (vcpu_info_t *)&shared_info(d, vcpu_info[vcpu_id])
: &dummy_vcpu_info);
v->vcpu_info_mfn = INVALID_MFN;
init_waitqueue_vcpu(v);
}
if ( sched_init_vcpu(v, cpu_id) != 0 )
goto fail_wq;
if ( vcpu_initialise(v) != 0 )
{
sched_destroy_vcpu(v);
fail_wq:
destroy_waitqueue_vcpu(v);
fail_free:
free_cpumask_var(v->cpu_affinity);
free_cpumask_var(v->cpu_affinity_tmp);
free_cpumask_var(v->cpu_affinity_saved);
free_cpumask_var(v->vcpu_dirty_cpumask);
free_vcpu_struct(v);
return NULL;
}
d->vcpu[vcpu_id] = v;
if ( vcpu_id != 0 )
{
int prev_id = v->vcpu_id - 1;
while ( (prev_id >= 0) && (d->vcpu[prev_id] == NULL) )
prev_id--;
BUG_ON(prev_id < 0);
v->next_in_list = d->vcpu[prev_id]->next_in_list;
d->vcpu[prev_id]->next_in_list = v;
}
/* Must be called after making new vcpu visible to for_each_vcpu(). */
vcpu_check_shutdown(v);
domain_update_node_affinity(d);
return v;
}
int arch_domain_create(struct domain *d, unsigned int domcr_flags,
struct xen_arch_domainconfig *config)
{
int rc;
uint8_t gic_version;
d->arch.relmem = RELMEM_not_started;
/* Idle domains do not need this setup */
if ( is_idle_domain(d) )
return 0;
ASSERT(config != NULL);
if ( (rc = p2m_init(d)) != 0 )
goto fail;
rc = -ENOMEM;
if ( (d->shared_info = alloc_xenheap_pages(0, 0)) == NULL )
goto fail;
/* Default the virtual ID to match the physical */
d->arch.vpidr = boot_cpu_data.midr.bits;
clear_page(d->shared_info);
share_xen_page_with_guest(
virt_to_page(d->shared_info), d, XENSHARE_writable);
if ( (rc = domain_io_init(d)) != 0 )
goto fail;
if ( (rc = p2m_alloc_table(d)) != 0 )
goto fail;
/*
* Currently the vGIC is emulating the same version of the
* hardware GIC. Only the value XEN_DOMCTL_CONFIG_GIC_DEFAULT
* is allowed. The DOMCTL will return the actual version of the
* GIC.
*/
rc = -EOPNOTSUPP;
if ( config->gic_version != XEN_DOMCTL_CONFIG_GIC_DEFAULT )
goto fail;
switch ( gic_hw_version() )
{
case GIC_V3:
gic_version = XEN_DOMCTL_CONFIG_GIC_V3;
break;
case GIC_V2:
gic_version = XEN_DOMCTL_CONFIG_GIC_V2;
break;
default:
BUG();
}
config->gic_version = gic_version;
if ( (rc = gicv_setup(d)) != 0 )
goto fail;
if ( (rc = domain_vgic_init(d)) != 0 )
goto fail;
if ( (rc = domain_vtimer_init(d)) != 0 )
goto fail;
/*
* The hardware domain will get a PPI later in
* arch/arm/domain_build.c depending on the
* interrupt map of the hardware.
*/
if ( !is_hardware_domain(d) )
{
d->arch.evtchn_irq = GUEST_EVTCHN_PPI;
/* At this stage vgic_reserve_virq should never fail */
if ( !vgic_reserve_virq(d, GUEST_EVTCHN_PPI) )
BUG();
}
/*
* Virtual UART is only used by linux early printk and decompress code.
* Only use it for the hardware domain because the linux kernel may not
* support multi-platform.
*/
if ( is_hardware_domain(d) && (rc = domain_vuart_init(d)) )
goto fail;
if ( (rc = iommu_domain_init(d)) != 0 )
goto fail;
return 0;
fail:
d->is_dying = DOMDYING_dead;
arch_domain_destroy(d);
return rc;
}
int arch_domain_create(struct domain *d, unsigned int domcr_flags,
struct xen_arch_domainconfig *config)
{
int rc, count = 0;
BUILD_BUG_ON(GUEST_MAX_VCPUS < MAX_VIRT_CPUS);
d->arch.relmem = RELMEM_not_started;
/* Idle domains do not need this setup */
if ( is_idle_domain(d) )
return 0;
ASSERT(config != NULL);
/* p2m_init relies on some value initialized by the IOMMU subsystem */
if ( (rc = iommu_domain_init(d)) != 0 )
goto fail;
if ( (rc = p2m_init(d)) != 0 )
goto fail;
rc = -ENOMEM;
if ( (d->shared_info = alloc_xenheap_pages(0, 0)) == NULL )
goto fail;
/* Default the virtual ID to match the physical */
d->arch.vpidr = boot_cpu_data.midr.bits;
clear_page(d->shared_info);
share_xen_page_with_guest(
virt_to_page(d->shared_info), d, XENSHARE_writable);
switch ( config->gic_version )
{
case XEN_DOMCTL_CONFIG_GIC_NATIVE:
switch ( gic_hw_version () )
{
case GIC_V2:
config->gic_version = XEN_DOMCTL_CONFIG_GIC_V2;
d->arch.vgic.version = GIC_V2;
break;
case GIC_V3:
config->gic_version = XEN_DOMCTL_CONFIG_GIC_V3;
d->arch.vgic.version = GIC_V3;
break;
default:
BUG();
}
break;
case XEN_DOMCTL_CONFIG_GIC_V2:
d->arch.vgic.version = GIC_V2;
break;
case XEN_DOMCTL_CONFIG_GIC_V3:
d->arch.vgic.version = GIC_V3;
break;
default:
rc = -EOPNOTSUPP;
goto fail;
}
if ( (rc = domain_vgic_register(d, &count)) != 0 )
goto fail;
if ( (rc = domain_io_init(d, count + MAX_IO_HANDLER)) != 0 )
goto fail;
if ( (rc = domain_vgic_init(d, config->nr_spis)) != 0 )
goto fail;
if ( (rc = domain_vtimer_init(d, config)) != 0 )
goto fail;
update_domain_wallclock_time(d);
/*
* The hardware domain will get a PPI later in
* arch/arm/domain_build.c depending on the
* interrupt map of the hardware.
*/
if ( !is_hardware_domain(d) )
{
d->arch.evtchn_irq = GUEST_EVTCHN_PPI;
/* At this stage vgic_reserve_virq should never fail */
if ( !vgic_reserve_virq(d, GUEST_EVTCHN_PPI) )
BUG();
}
/*
* Virtual UART is only used by linux early printk and decompress code.
* Only use it for the hardware domain because the linux kernel may not
* support multi-platform.
*/
if ( is_hardware_domain(d) && (rc = domain_vuart_init(d)) )
goto fail;
return 0;
fail:
d->is_dying = DOMDYING_dead;
arch_domain_destroy(d);
return rc;
}
struct domain *domain_create(domid_t dom_id, unsigned int cpu)
{
struct domain *d, **pd;
struct vcpu *v;
if ( (d = alloc_domain()) == NULL )
return NULL;
d->domain_id = dom_id;
atomic_set(&d->refcnt, 1);
spin_lock_init(&d->big_lock);
spin_lock_init(&d->page_alloc_lock);
INIT_LIST_HEAD(&d->page_list);
INIT_LIST_HEAD(&d->xenpage_list);
rangeset_domain_initialise(d);
if ( !is_idle_domain(d) )
{
set_bit(_DOMF_ctrl_pause, &d->domain_flags);
if ( evtchn_init(d) != 0 )
goto fail1;
if ( grant_table_create(d) != 0 )
goto fail2;
}
if ( arch_domain_create(d) != 0 )
goto fail3;
if ( (v = alloc_vcpu(d, 0, cpu)) == NULL )
goto fail4;
d->iomem_caps = rangeset_new(d, "I/O Memory", RANGESETF_prettyprint_hex);
d->irq_caps = rangeset_new(d, "Interrupts", 0);
if ( (d->iomem_caps == NULL) || (d->irq_caps == NULL) )
goto fail4; /* NB. alloc_vcpu() is undone in free_domain() */
#if 0
if ( sched_init_domain(d) != 0 )
goto fail4;
#endif
if ( !is_idle_domain(d) )
{
write_lock(&domlist_lock);
pd = &domain_list; /* NB. domain_list maintained in order of dom_id. */
for ( pd = &domain_list; *pd != NULL; pd = &(*pd)->next_in_list )
if ( (*pd)->domain_id > d->domain_id )
break;
d->next_in_list = *pd;
*pd = d;
d->next_in_hashbucket = domain_hash[DOMAIN_HASH(dom_id)];
domain_hash[DOMAIN_HASH(dom_id)] = d;
write_unlock(&domlist_lock);
}
return d;
fail4:
arch_domain_destroy(d);
fail3:
if ( !is_idle_domain(d) )
grant_table_destroy(d);
fail2:
if ( !is_idle_domain(d) )
evtchn_destroy(d);
fail1:
rangeset_domain_destroy(d);
free_domain(d);
return NULL;
}
/* Machine Check Handler for AMD K8 family series */
void k8_machine_check(struct cpu_user_regs *regs, long error_code)
{
struct vcpu *vcpu = current;
struct domain *curdom;
struct mc_info *mc_data;
struct mcinfo_global mc_global;
struct mcinfo_bank mc_info;
uint64_t status, addrv, miscv, uc;
uint32_t i;
unsigned int cpu_nr;
uint32_t xen_impacted = 0;
#define DOM_NORMAL 0
#define DOM0_TRAP 1
#define DOMU_TRAP 2
#define DOMU_KILLED 4
uint32_t dom_state = DOM_NORMAL;
/* This handler runs as interrupt gate. So IPIs from the
* polling service routine are defered until we finished.
*/
/* Disable interrupts for the _vcpu_. It may not re-scheduled to
* an other physical CPU or the impacted process in the guest
* continues running with corrupted data, otherwise. */
vcpu_schedule_lock_irq(vcpu);
mc_data = x86_mcinfo_getptr();
cpu_nr = smp_processor_id();
curdom = vcpu->domain;
memset(&mc_global, 0, sizeof(mc_global));
mc_global.common.type = MC_TYPE_GLOBAL;
mc_global.common.size = sizeof(mc_global);
mc_global.mc_domid = curdom->domain_id; /* impacted domain */
mc_global.mc_coreid = vcpu->processor; /* impacted physical cpu */
BUG_ON(cpu_nr != vcpu->processor);
mc_global.mc_core_threadid = 0;
mc_global.mc_vcpuid = vcpu->vcpu_id; /* impacted vcpu */
#if 0 /* TODO: on which socket is this physical core?
It's not clear to me how to figure this out. */
mc_global.mc_socketid = ???;
#endif
mc_global.mc_flags |= MC_FLAG_UNCORRECTABLE;
rdmsrl(MSR_IA32_MCG_STATUS, mc_global.mc_gstatus);
/* Quick check, who is impacted */
xen_impacted = is_idle_domain(curdom);
/* Dom0 */
x86_mcinfo_clear(mc_data);
x86_mcinfo_add(mc_data, &mc_global);
for (i = 0; i < nr_mce_banks; i++) {
struct domain *d;
rdmsrl(MSR_IA32_MC0_STATUS + 4 * i, status);
if (!(status & MCi_STATUS_VAL))
continue;
/* An error happened in this bank.
* This is expected to be an uncorrectable error,
* since correctable errors get polled.
*/
uc = status & MCi_STATUS_UC;
memset(&mc_info, 0, sizeof(mc_info));
mc_info.common.type = MC_TYPE_BANK;
mc_info.common.size = sizeof(mc_info);
mc_info.mc_bank = i;
mc_info.mc_status = status;
addrv = 0;
if (status & MCi_STATUS_ADDRV) {
rdmsrl(MSR_IA32_MC0_ADDR + 4 * i, addrv);
d = maddr_get_owner(addrv);
if (d != NULL)
mc_info.mc_domid = d->domain_id;
}
miscv = 0;
if (status & MCi_STATUS_MISCV)
rdmsrl(MSR_IA32_MC0_MISC + 4 * i, miscv);
mc_info.mc_addr = addrv;
mc_info.mc_misc = miscv;
x86_mcinfo_add(mc_data, &mc_info); /* Dom0 */
if (mc_callback_bank_extended)
mc_callback_bank_extended(mc_data, i, status);
/* clear status */
wrmsrl(MSR_IA32_MC0_STATUS + 4 * i, 0x0ULL);
wmb();
add_taint(TAINT_MACHINE_CHECK);
}
status = mc_global.mc_gstatus;
/* clear MCIP or cpu enters shutdown state
* in case another MCE occurs. */
status &= ~MCG_STATUS_MCIP;
wrmsrl(MSR_IA32_MCG_STATUS, status);
wmb();
/* For the details see the discussion "MCE/MCA concept" on xen-devel.
* The thread started here:
* http://lists.xensource.com/archives/html/xen-devel/2007-05/msg01015.html
*/
/* MCG_STATUS_RIPV:
* When this bit is not set, then the instruction pointer onto the stack
* to resume at is not valid. If xen is interrupted, then we panic anyway
* right below. Otherwise it is up to the guest to figure out if
* guest kernel or guest userland is affected and should kill either
* itself or the affected process.
*/
/* MCG_STATUS_EIPV:
* Evaluation of EIPV is the job of the guest.
*/
if (xen_impacted) {
/* Now we are going to panic anyway. Allow interrupts, so that
* printk on serial console can work. */
vcpu_schedule_unlock_irq(vcpu);
/* Uh, that means, machine check exception
* inside Xen occured. */
printk("Machine check exception occured in Xen.\n");
/* if MCG_STATUS_EIPV indicates, the IP on the stack is related
* to the error then it makes sense to print a stack trace.
* That can be useful for more detailed error analysis and/or
* error case studies to figure out, if we can clear
* xen_impacted and kill a DomU instead
* (i.e. if a guest only control structure is affected, but then
* we must ensure the bad pages are not re-used again).
*/
if (status & MCG_STATUS_EIPV) {
printk("MCE: Instruction Pointer is related to the error. "
"Therefore, print the execution state.\n");
show_execution_state(regs);
}
x86_mcinfo_dump(mc_data);
mc_panic("End of MCE. Use mcelog to decode above error codes.\n");
}
/* If Dom0 registered a machine check handler, which is only possible
* with a PV MCA driver, then ... */
if ( guest_has_trap_callback(dom0, 0, TRAP_machine_check) ) {
dom_state = DOM0_TRAP;
/* ... deliver machine check trap to Dom0. */
send_guest_trap(dom0, 0, TRAP_machine_check);
/* Xen may tell Dom0 now to notify the DomU.
* But this will happen through a hypercall. */
} else
/* Dom0 did not register a machine check handler, but if DomU
* did so, then... */
if ( guest_has_trap_callback(curdom, vcpu->vcpu_id, TRAP_machine_check) ) {
dom_state = DOMU_TRAP;
/* ... deliver machine check trap to DomU */
send_guest_trap(curdom, vcpu->vcpu_id, TRAP_machine_check);
} else {
/* hmm... noone feels responsible to handle the error.
* So, do a quick check if a DomU is impacted or not.
*/
if (curdom == dom0) {
/* Dom0 is impacted. Since noone can't handle
* this error, panic! */
x86_mcinfo_dump(mc_data);
mc_panic("MCE occured in Dom0, which it can't handle\n");
/* UNREACHED */
} else {
dom_state = DOMU_KILLED;
/* Enable interrupts. This basically results in
* calling sti on the *physical* cpu. But after
* domain_crash() the vcpu pointer is invalid.
* Therefore, we must unlock the irqs before killing
* it. */
vcpu_schedule_unlock_irq(vcpu);
/* DomU is impacted. Kill it and continue. */
domain_crash(curdom);
}
}
switch (dom_state) {
case DOM0_TRAP:
case DOMU_TRAP:
/* Enable interrupts. */
vcpu_schedule_unlock_irq(vcpu);
/* guest softirqs and event callbacks are scheduled
* immediately after this handler exits. */
break;
case DOMU_KILLED:
/* Nothing to do here. */
break;
default:
BUG();
}
}
