Esempio n. 1
0
int ar7240_platform_init(void)
{
	int ret;
	/* need to set clock appropriately */
#ifdef CONFIG_WASP_SUPPORT
	ar7240_uart_data[0].uartclk = ath_ref_clk_freq;
#else
	ar7240_uart_data[0].uartclk = ar7240_ahb_freq;
#endif
#if 1
	ret = platform_add_devices(ar724x_platform_devices,
				ARRAY_SIZE(ar724x_platform_devices));
        printk("===== ar7240_platform_init: %d\n", ret);
	if (ret < 0)
		return ret;
#endif
	if (is_ar7241() || is_ar7242() || is_ar933x() || is_wasp()) {
		return (platform_add_devices(ar7241_platform_devices,
				ARRAY_SIZE(ar7241_platform_devices)));
	}
	if (is_ar7240()) {
		return (platform_add_devices(ar7240_platform_devices,
				ARRAY_SIZE(ar7240_platform_devices)));
	}

	return 0;
}
Esempio n. 2
0
File: ag934x.c Progetto: jhbsz/102
static int ag7240_check_link(ag7240_mac_t *mac)
{
    u32 link, duplex, speed, fdx;

    ag7240_phy_link(mac->mac_unit, &link);
    ag7240_phy_duplex(mac->mac_unit, &duplex);
    ag7240_phy_speed(mac->mac_unit, &speed);

    mac->link = link;
#ifdef SUPPORT_PLC
    if(strcmp(mac->dev->name, "eth0") == 0) {
        printf("ag7240_check_link: %s link forced down\n",mac->dev->name);
        return 0;
    }
#endif

    if(!mac->link) {
        printf("%s link down\n",mac->dev->name);
        return 0;
    }

    switch (speed)
    {
    case _1000BASET:
        ag7240_set_mac_if(mac, 1);
        ag7240_reg_rmw_set(mac, AG7240_MAC_FIFO_CFG_5, (1 << 19));
        if (is_ar7242() && (mac->mac_unit == 0)) {
            ar7240_reg_wr(AR7242_ETH_XMII_CONFIG,0x1c000000);
        }
#ifdef CONFIG_F1E_PHY
        if (is_wasp() && (mac->mac_unit == 0)) {
            ar7240_reg_wr(AR7242_ETH_XMII_CONFIG,0x0e000000);
        }
#elif CONFIG_VIR_PHY
        if (is_wasp() && (mac->mac_unit == 0)) {
            ar7240_reg_wr(AR7242_ETH_XMII_CONFIG,0x82000000);
            ar7240_reg_wr(AG7240_ETH_CFG,0x000c0001);
        }
#else
        if (is_wasp() && (mac->mac_unit == 0) && !is_f2e()) {
            ar7240_reg_wr(AR7242_ETH_XMII_CONFIG,0x06000000);
        }
#endif
        if (is_wasp() && mac->mac_unit == 0 && is_f1e() ) {
            ar7240_reg_rmw_set(AG7240_ETH_CFG,AG7240_ETH_CFG_RXD_DELAY);
            ar7240_reg_rmw_set(AG7240_ETH_CFG,AG7240_ETH_CFG_RDV_DELAY);
        }

        break;

    case _100BASET:
        ag7240_set_mac_if(mac, 0);
        ag7240_set_mac_speed(mac, 1);
        ag7240_reg_rmw_clear(mac, AG7240_MAC_FIFO_CFG_5, (1 << 19));
        if ((is_ar7242() || is_wasp()) && (mac->mac_unit == 0) && !is_f2e())
            ar7240_reg_wr(AR7242_ETH_XMII_CONFIG,0x0101);

        if (is_wasp() && mac->mac_unit == 0 && is_f1e()) {
            ar7240_reg_rmw_clear(AG7240_ETH_CFG,AG7240_ETH_CFG_RXD_DELAY);
            ar7240_reg_rmw_clear(AG7240_ETH_CFG,AG7240_ETH_CFG_RDV_DELAY);
        }
        break;

    case _10BASET:
        ag7240_set_mac_if(mac, 0);
        ag7240_set_mac_speed(mac, 0);
        ag7240_reg_rmw_clear(mac, AG7240_MAC_FIFO_CFG_5, (1 << 19));

        if ((is_ar7242() || is_wasp()) && (mac->mac_unit == 0) && !is_f2e())
            ar7240_reg_wr(AR7242_ETH_XMII_CONFIG,0x1616);

        if (is_wasp() && mac->mac_unit == 0 && is_f1e()) {
            ar7240_reg_rmw_clear(AG7240_ETH_CFG,AG7240_ETH_CFG_RXD_DELAY);
            ar7240_reg_rmw_clear(AG7240_ETH_CFG,AG7240_ETH_CFG_RDV_DELAY);
            ar7240_reg_wr(AR7242_ETH_XMII_CONFIG,0x1313);
        }
        if (is_f2e()) {
            ar7240_reg_rmw_clear(AG7240_ETH_CFG, AG7240_ETH_CFG_RMII_HISPD_GE0);
        }
        break;

    default:
        printf("Invalid speed detected\n");
        return 0;
    }

    if (mac->link && (duplex == mac->duplex) && (speed == mac->speed))
        return 1;

    mac->duplex = duplex;
    mac->speed = speed;

    printf("dup %d speed %d\n", duplex, speed);

    ag7240_set_mac_duplex(mac,duplex);

    return 1;
}
Esempio n. 3
0
File: ag934x.c Progetto: jhbsz/102
static void ag7240_get_ethaddr(struct eth_device *dev)
{
    unsigned char *eeprom;
    unsigned char *mac = dev->enetaddr;
#ifndef CONFIG_AR7240_EMU

#ifdef CONFIG_ATH_NAND_BR
    unsigned char sectorBuff[ATH_ETH_MAC_READ_SIZE];

    eeprom = ath_eth_mac_addr(sectorBuff);
    if(eeprom == NULL) {
        /* mac address will be set to default mac address */
        mac[0] = 0xff;
    }
    else {
#else  /* CONFIG_ATH_NAND_BR */
    eeprom = ag7240_mac_addr_loc();
#endif  /* CONFIG_ATH_NAND_BR */

        if (strcmp(dev->name, "eth0") == 0) {
            memcpy(mac, eeprom, 6);
        } else if (strcmp(dev->name, "eth1") == 0) {
            eeprom += 6;
            memcpy(mac, eeprom, 6);
        } else {
            printf("%s: unknown ethernet device %s\n", __func__, dev->name);
            return;
        }
#ifdef CONFIG_ATH_NAND_BR
    }
#endif  /* CONFIG_ATH_NAND_BR */
    /* Use fixed address if the above address is invalid */
    if (mac[0] != 0x00 || (mac[0] == 0xff && mac[5] == 0xff)) {
#else
    if (1) {
#endif
        mac[0] = 0x00;
        mac[1] = 0x03;
        mac[2] = 0x7f;
        mac[3] = 0x09;
        mac[4] = 0x0b;
        mac[5] = 0xad;
        printf("No valid address in Flash. Using fixed address\n");
    } else {
        printf("Fetching MAC Address from 0x%p\n", __func__, eeprom);
    }
}


int ag7240_enet_initialize(bd_t * bis)
{
    struct eth_device *dev[CFG_AG7240_NMACS];
    u32 mask, mac_h, mac_l;
    int i;

    printf("ag934x_enet_initialize...\n");

    if(is_ar933x() && (ar7240_reg_rd(AR7240_RESET)!=0))
        ar7240_reg_wr(AR7240_RESET,0);

    if(is_ar933x())  //Turn on LED
        ar7240_reg_wr(AR7240_GPIO_BASE + 0x28 , ar7240_reg_rd(AR7240_GPIO_BASE + 0x28)  | (0xF8));

    for (i = 0; i < CFG_AG7240_NMACS; i++) {

        if ((dev[i] = (struct eth_device *) malloc(sizeof (struct eth_device))) == NULL) {
            puts("malloc failed\n");
            return 0;
        }

        if ((ag7240_macs[i] = (ag7240_mac_t *) malloc(sizeof (ag7240_mac_t))) == NULL) {
            puts("malloc failed\n");
            return 0;
        }

        memset(ag7240_macs[i], 0, sizeof(ag7240_macs[i]));
        memset(dev[i], 0, sizeof(dev[i]));

        sprintf(dev[i]->name, "eth%d", i);
        ag7240_get_ethaddr(dev[i]);

        ag7240_macs[i]->mac_unit = i;
        ag7240_macs[i]->mac_base = i ? AR7240_GE1_BASE : AR7240_GE0_BASE ;
        ag7240_macs[i]->dev = dev[i];

        dev[i]->iobase = 0;
        dev[i]->init = ag7240_clean_rx;
        dev[i]->halt = ag7240_halt;
        dev[i]->send = ag7240_send;
        dev[i]->recv = ag7240_recv;
        dev[i]->priv = (void *)ag7240_macs[i];
    }
#if !defined(CONFIG_ATH_NAND_BR)
    mask = AR7240_RESET_GE1_PHY;
    ar7240_reg_rmw_set(AR7240_RESET, mask);
    udelay(1000 * 100);
    ar7240_reg_rmw_clear(AR7240_RESET, mask);
    udelay(100);
#endif
    mask = AR7240_RESET_GE0_PHY;
    ar7240_reg_rmw_set(AR7240_RESET, mask);
    udelay(1000 * 100);
    ar7240_reg_rmw_clear(AR7240_RESET, mask);
    udelay(100);


    for (i = 0; i < CFG_AG7240_NMACS; i++) {
        eth_register(dev[i]);
#if(CONFIG_COMMANDS & CFG_CMD_MII)
        miiphy_register(dev[i]->name, ag7240_miiphy_read, ag7240_miiphy_write);
#endif

        ag7240_reg_rmw_set(ag7240_macs[i], AG7240_MAC_CFG1, AG7240_MAC_CFG1_SOFT_RST
                           | AG7240_MAC_CFG1_RX_RST | AG7240_MAC_CFG1_TX_RST);

        if(!i) {
            mask = (AR7240_RESET_GE0_MAC  | AR7240_RESET_GE1_MAC);

            if (is_ar7241() || is_ar7242() ||  is_wasp())
                mask = mask | AR7240_RESET_GE0_MDIO | AR7240_RESET_GE1_MDIO;

            printf(" wasp  reset mask:%x \n",mask);

            ar7240_reg_rmw_set(AR7240_RESET, mask);
            udelay(1000 * 100);

            ar7240_reg_rmw_clear(AR7240_RESET, mask);
            udelay(1000 * 100);

            udelay(10 * 1000);
        }

        ag7240_mii_setup(ag7240_macs[i]);

        /* if using header for register configuration, we have to     */
        /* configure s26 register after frame transmission is enabled */

        if (ag7240_macs[i]->mac_unit == 0) { /* WAN Phy */
#ifdef CONFIG_AR7242_S16_PHY
            if (is_ar7242() || is_wasp()) {
                athrs16_reg_init();
            } else
#endif
            {
#ifdef  CONFIG_ATHRS17_PHY
                athrs17_reg_init();
#endif

#ifdef CFG_ATHRS26_PHY
                athrs26_reg_init();
#endif
#ifdef CFG_ATHRS27_PHY
                printf("s27 reg init \n");
                athrs27_reg_init();
#endif
#ifdef CONFIG_F1E_PHY
                printf("F1Phy reg init \n");
                athr_reg_init();
#endif
#ifdef CONFIG_VIR_PHY
                printf("VIRPhy reg init \n");
                athr_vir_reg_init();
#endif
#ifdef CONFIG_F2E_PHY
                printf("F2Phy reg init \n");
                athr_reg_init();
#endif

            }
        } else {
#ifdef CFG_ATHRS26_PHY
            athrs26_reg_init_lan();
#endif
#ifdef CFG_ATHRS27_PHY
            printf("s27 reg init lan \n");
            athrs27_reg_init_lan();
#endif
        }
        ag7240_hw_start(ag7240_macs[i]);
        ag7240_setup_fifos(ag7240_macs[i]);

        udelay(100 * 1000);

        {
            unsigned char *mac = dev[i]->enetaddr;

            printf("%s: %02x:%02x:%02x:%02x:%02x:%02x\n", dev[i]->name,
                   mac[0] & 0xff, mac[1] & 0xff, mac[2] & 0xff,
                   mac[3] & 0xff, mac[4] & 0xff, mac[5] & 0xff);
        }
        mac_l = (dev[i]->enetaddr[4] << 8) | (dev[i]->enetaddr[5]);
        mac_h = (dev[i]->enetaddr[0] << 24) | (dev[i]->enetaddr[1] << 16) |
                (dev[i]->enetaddr[2] << 8) | (dev[i]->enetaddr[3] << 0);

        ag7240_reg_wr(ag7240_macs[i], AG7240_GE_MAC_ADDR1, mac_l);
        ag7240_reg_wr(ag7240_macs[i], AG7240_GE_MAC_ADDR2, mac_h);


        ag7240_phy_setup(ag7240_macs[i]->mac_unit);
        printf("%s up\n",dev[i]->name);
    }

    return 1;
}

#if (CONFIG_COMMANDS & CFG_CMD_MII)
int
ag7240_miiphy_read(char *devname, uint32_t phy_addr, uint8_t reg, uint16_t *data)
{
    ag7240_mac_t *mac   = ag7240_name2mac(devname);
    uint16_t      addr  = (phy_addr << AG7240_ADDR_SHIFT) | reg, val;
    volatile int           rddata;
    uint16_t      ii = 0xFFFF;


    /*
     * Check for previous transactions are complete. Added to avoid
     * race condition while running at higher frequencies.
     */
    do
    {
        udelay(5);
        rddata = ag7240_reg_rd(mac, AG7240_MII_MGMT_IND) & 0x1;
    } while(rddata && --ii);

    if (ii == 0)
        printf("ERROR:%s:%d transaction failed\n",__func__,__LINE__);


    ag7240_reg_wr(mac, AG7240_MII_MGMT_CMD, 0x0);
    ag7240_reg_wr(mac, AG7240_MII_MGMT_ADDRESS, addr);
    ag7240_reg_wr(mac, AG7240_MII_MGMT_CMD, AG7240_MGMT_CMD_READ);

    do
    {
        udelay(5);
        rddata = ag7240_reg_rd(mac, AG7240_MII_MGMT_IND) & 0x1;
    } while(rddata && --ii);

    if(ii==0)
        printf("Error!!! Leave ag7240_miiphy_read without polling correct status!\n");

    val = ag7240_reg_rd(mac, AG7240_MII_MGMT_STATUS);
    ag7240_reg_wr(mac, AG7240_MII_MGMT_CMD, 0x0);

    if(data != NULL)
        *data = val;

    return val;
}
Esempio n. 4
0
int ag7240_enet_initialize(bd_t * bis) {
	struct eth_device *dev[CFG_AG7240_NMACS];
	u32 mask, mac_h, mac_l;
	int i;

#ifdef AG7240_DEBUG
	printf("ag7240_enet_initialize...\n");
#endif

	// TODO check this register!
	ar7240_reg_wr(HORNET_BOOTSTRAP_STATUS, ar7240_reg_rd(HORNET_BOOTSTRAP_STATUS) & ~HORNET_BOOTSTRAP_MDIO_SLAVE_MASK);

	if (is_ar933x()) {
		u32 rd = 0x0;

		/* 
		 * To get s26 out of reset, we have to...
		 * bit0~bit3: has to be deasserted
		 * bit4:      has to be asserted
		 */
		rd = ar7240_reg_rd(AR7240_S26_CLK_CTRL_OFFSET) & ~(0x1f);
		rd |= 0x10;
		ar7240_reg_wr(AR7240_S26_CLK_CTRL_OFFSET, rd);

		if (ar7240_reg_rd(AR7240_RESET) != 0) {
			ar7240_reg_wr(AR7240_RESET, 0);
		}
	}

	for (i = 0; i < CFG_AG7240_NMACS; i++) {

		if ((dev[i] = (struct eth_device *) malloc(sizeof(struct eth_device))) == NULL) {
			puts("## Error: malloc failed\n");
			return 0;
		}

		if ((ag7240_macs[i] = (ag7240_mac_t *) malloc(sizeof(ag7240_mac_t))) == NULL) {
			puts("## Error: malloc failed\n");
			return 0;
		}

		memset(ag7240_macs[i], 0, sizeof(ag7240_macs[i]));
		memset(dev[i], 0, sizeof(dev[i]));

		sprintf(dev[i]->name, "eth%d", i);
		ag7240_get_ethaddr(dev[i]);

		ag7240_macs[i]->mac_unit = i;
		ag7240_macs[i]->mac_base = i ? AR7240_GE1_BASE : AR7240_GE0_BASE;
		ag7240_macs[i]->dev = dev[i];

		dev[i]->iobase = 0;
		dev[i]->init = ag7240_clean_rx;
		dev[i]->halt = ag7240_halt;
		dev[i]->send = ag7240_send;
		dev[i]->recv = ag7240_recv;
		dev[i]->priv = (void *) ag7240_macs[i];
	}

	for (i = 0; i < CFG_AG7240_NMACS; i++) {

		eth_register(dev[i]);

#if(CONFIG_COMMANDS & CFG_CMD_MII)
		miiphy_register(dev[i]->name, ag7240_miiphy_read, ag7240_miiphy_write);
#endif

		ag7240_reg_rmw_set(ag7240_macs[i], AG7240_MAC_CFG1, AG7240_MAC_CFG1_SOFT_RST | AG7240_MAC_CFG1_RX_RST | AG7240_MAC_CFG1_TX_RST);

		if (!i) {
			mask = (AR7240_RESET_GE0_MAC | AR7240_RESET_GE0_PHY | AR7240_RESET_GE1_MAC | AR7240_RESET_GE1_PHY);

			if (is_ar7241() || is_ar7242() || is_wasp()){
				mask = mask | AR7240_RESET_GE0_MDIO | AR7240_RESET_GE1_MDIO;
			}

			ar7240_reg_rmw_set(AR7240_RESET, mask);

			if (!is_ar933x()){
				udelay(1000 * 100);
			}

			ar7240_reg_rmw_clear(AR7240_RESET, mask);

			if (!is_ar933x()){
				udelay(1000 * 100);
			}

			if (!is_ar933x()){
				udelay(10 * 1000);
			}
		}

		ag7240_hw_start(ag7240_macs[i]);

		ag7240_setup_fifos(ag7240_macs[i]);

		if (!is_ar933x()){
			udelay(100 * 1000);
		}

#ifdef AG7240_DEBUG
		unsigned char *mac = dev[i]->enetaddr;
		printf("\nInterface %s MAC address: %02X:%02X:%02X:%02X:%02X:%02X\n", dev[i]->name, mac[0] & 0xff, mac[1] & 0xff, mac[2] & 0xff, mac[3] & 0xff, mac[4] & 0xff, mac[5] & 0xff);
#endif

		mac_l = (dev[i]->enetaddr[4] << 8) | (dev[i]->enetaddr[5]);
		mac_h = (dev[i]->enetaddr[0] << 24) | (dev[i]->enetaddr[1] << 16) | (dev[i]->enetaddr[2] << 8) | (dev[i]->enetaddr[3] << 0);

		ag7240_reg_wr(ag7240_macs[i], AG7240_GE_MAC_ADDR1, mac_l);
		ag7240_reg_wr(ag7240_macs[i], AG7240_GE_MAC_ADDR2, mac_h);

		/* if using header for register configuration, we have to     */
		/* configure s26 register after frame transmission is enabled */

		if (ag7240_macs[i]->mac_unit == 0) { /* WAN Phy */
#ifdef CONFIG_AR7242_S16_PHY
			if (is_ar7242() || is_wasp()) {
				athrs16_reg_init();
			} else
#endif
			{
#ifdef CFG_ATHRS26_PHY
	#ifdef AG7240_DEBUG
				printf("s26 reg init \n");
	#endif
				athrs26_reg_init();
#endif
#ifdef CFG_ATHRS27_PHY
	#ifdef AG7240_DEBUG
				printf("s27 reg init \n");
	#endif
				athrs27_reg_init();
#endif
#ifdef CONFIG_F1E_PHY
	#ifdef AG7240_DEBUG
				printf("F1Phy reg init \n");
	#endif
				athr_reg_init();
#endif
			}
		} else {
#ifdef CFG_ATHRS26_PHY
	#ifdef AG7240_DEBUG
			printf("athrs26_reg_init_lan\n");
	#endif
			athrs26_reg_init_lan();
#endif
#ifdef CFG_ATHRS27_PHY
	#ifdef AG7240_DEBUG
			printf("s27 reg init lan \n");
	#endif
			athrs27_reg_init_lan();
#endif
		}

#ifdef AG7240_DEBUG
		printf("ag7240_phy_setup\n");
#endif
		//udelay(100*1000);

		ag7240_phy_setup(ag7240_macs[i]->mac_unit);

#ifdef AG7240_DEBUG
		printf("Interface %s is up\n", dev[i]->name);
#endif
	}

	return 1;
}
Esempio n. 5
0
File: ag934x.c Progetto: jhbsz/102
void ag7240_mii_setup(ag7240_mac_t *mac)
{
    u32 mgmt_cfg_val;
    u32 cpu_freq,ddr_freq,ahb_freq;
    u32 check_cnt,revid_val;

    if ((ar7240_reg_rd(WASP_BOOTSTRAP_REG) & WASP_REF_CLK_25) == 0) {
#ifndef CFG_DUAL_PHY_SUPPORT
        ar7240_reg_wr(AR934X_SWITCH_CLOCK_SPARE, 0x271);
#endif
    } else {
        ar7240_reg_wr(AR934X_SWITCH_CLOCK_SPARE, 0x570);
    }

#if defined(CONFIG_AR7242_S16_PHY) || defined(CONFIG_ATHRS17_PHY)
    if (is_wasp() && mac->mac_unit == 0) {
#ifdef CONFIG_AR7242_S16_PHY
        printf("WASP  ----> S16 PHY *\n");
#else
        printf("WASP  ----> S17 PHY *\n");
#endif
        mgmt_cfg_val = 4;
        if(mac->mac_unit == 0)
            ar7240_reg_wr(AG7240_ETH_CFG, AG7240_ETH_CFG_RGMII_GE0);

        udelay(1000);

        ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
        ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);

        return;
    }
#endif

#ifdef CFG_ATHRS27_PHY
    if (is_wasp()) {
        printf("WASP ----> S27 PHY \n");
        mgmt_cfg_val = 2;
        ag7240_reg_wr(ag7240_macs[1], AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
        ag7240_reg_wr(ag7240_macs[1], AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
        return;
    }
#endif

#ifdef CONFIG_F2E_PHY
    if (is_wasp()) {
        printf("WASP  ----> F2 PHY *\n");
        ar7240_reg_wr(AG7240_ETH_CFG, (AG7240_ETH_CFG_RMII_MASTER_MODE | AG7240_ETH_CFG_RMII_GE0
                                       | AG7240_ETH_CFG_RMII_HISPD_GE0));

        mgmt_cfg_val = 6;

        ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
        ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);

        return;
    }
#endif


#if defined(CONFIG_F1E_PHY) || defined(CONFIG_VIR_PHY)
    if (is_wasp()) {
#ifdef CONFIG_VIR_PHY
        printf("WASP  ----> VIR PHY *\n");
#else
        printf("WASP  ----> F1 PHY *\n");
#endif
        if(mac->mac_unit == 0)
            ar7240_reg_wr(AG7240_ETH_CFG, AG7240_ETH_CFG_RGMII_GE0);

        mgmt_cfg_val = 6;

        ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
        ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);

        return;
    }
#endif

    if ((ar7240_reg_rd(AR7240_REV_ID) & AR7240_REV_ID_MASK) == AR7240_REV_1_2) {
        mgmt_cfg_val = 0x2;
        if (mac->mac_unit == 0) {
            ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
            ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
        }
    }
    else {
        ar7240_sys_frequency(&cpu_freq, &ddr_freq, &ahb_freq);
        switch (ahb_freq/1000000) {
        case 150:
            mgmt_cfg_val = 0x7;
            break;
        case 175:
            mgmt_cfg_val = 0x5;
            break;
        case 200:
            mgmt_cfg_val = 0x4;
            break;
        case 210:
            mgmt_cfg_val = 0x9;
            break;
        case 220:
            mgmt_cfg_val = 0x9;
            break;
        default:
            mgmt_cfg_val = 0x7;
        }
        if ((is_ar7241() || is_ar7242())) {

            /* External MII mode */
            if (mac->mac_unit == 0 && is_ar7242()) {
                mgmt_cfg_val = 0x6;
                ar7240_reg_rmw_set(AG7240_ETH_CFG, AG7240_ETH_CFG_RGMII_GE0);
                ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
                ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
            }
            /* Virian */
            mgmt_cfg_val = 0x4;
            ag7240_reg_wr(ag7240_macs[1], AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
            ag7240_reg_wr(ag7240_macs[1], AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
            printf("Virian MDC CFG Value ==> %x\n",mgmt_cfg_val);

        }
        else if(is_ar933x()) {
            //GE0 receives Rx/Tx clock, and use S26 phy
            ar7240_reg_rmw_set(AG7240_ETH_CFG, AG7240_ETH_CFG_MII_GE0_SLAVE);
            mgmt_cfg_val = 0xF;
            if (mac->mac_unit == 1) {
                check_cnt = 0;
                while (check_cnt++ < 10) {
                    ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
                    ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
#ifdef CFG_ATHRS26_PHY
                    if(athrs26_mdc_check() == 0)
                        break;
#endif
                }
                if(check_cnt == 11)
                    printf("%s: MDC check failed\n", __func__);
            }
        }
        else { /* Python 1.0 & 1.1 */
            if (mac->mac_unit == 0) {
                check_cnt = 0;
                while (check_cnt++ < 10) {
                    ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
                    ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
#ifdef CFG_ATHRS26_PHY
                    if(athrs26_mdc_check() == 0)
                        break;
#endif
                }
                if(check_cnt == 11)
                    printf("%s: MDC check failed\n", __func__);
            }
        }

    }
}
Esempio n. 6
0
static int ag7240_check_link(ag7240_mac_t *mac) {
	int link = 0, duplex = 0, speed = 0;
	char *s;

	s = getenv("stdin");

	ag7240_phy_link(mac->mac_unit, &link);
	ag7240_phy_duplex(mac->mac_unit, &duplex);
	ag7240_phy_speed(mac->mac_unit, &speed);

	mac->link = link;

	if (!mac->link) {
		if((s != NULL) && (strcmp(s, "nc") != 0)){
			printf("Link down: %s\n", mac->dev->name);
		}
		return 0;
	}

	switch (speed) {
	case _1000BASET:
		ag7240_set_mac_if(mac, 1);
		ag7240_reg_rmw_set(mac, AG7240_MAC_FIFO_CFG_5, (1 << 19));
		if (is_ar7242() && (mac->mac_unit == 0)) {
			ar7240_reg_wr(AR7242_ETH_XMII_CONFIG, 0x1c000000);
		}
#ifdef CONFIG_F1E_PHY
		if (is_wasp() && (mac->mac_unit == 0)) {
			ar7240_reg_wr(AR7242_ETH_XMII_CONFIG,0x0e000000);
		}
#else      
		if (is_wasp() && (mac->mac_unit == 0)) {
			ar7240_reg_wr(AR7242_ETH_XMII_CONFIG, 0x06000000);
		}
#endif
		break;

	case _100BASET:
		ag7240_set_mac_if(mac, 0);
		ag7240_set_mac_speed(mac, 1);
		ag7240_reg_rmw_clear(mac, AG7240_MAC_FIFO_CFG_5, (1 << 19));
		if ((is_ar7242() || is_wasp()) && (mac->mac_unit == 0)){
			ar7240_reg_wr(AR7242_ETH_XMII_CONFIG, 0x0101);
		}
		break;

	case _10BASET:
		ag7240_set_mac_if(mac, 0);
		ag7240_set_mac_speed(mac, 0);
		ag7240_reg_rmw_clear(mac, AG7240_MAC_FIFO_CFG_5, (1 << 19));
		if ((is_ar7242() || is_wasp()) && (mac->mac_unit == 0)){
			ar7240_reg_wr(AR7242_ETH_XMII_CONFIG, 0x1616);
		}
		break;

	default:
		if((s != NULL) && (strcmp(s, "nc") != 0)){
			printf("## Error: invalid speed detected\n");
		}
		return 0;
	}

	if (mac->link && (duplex == mac->duplex) && (speed == mac->speed)){
		return 1;
	}

	mac->duplex = duplex;
	mac->speed = speed;

	if((s != NULL) && (strcmp(s, "nc") != 0)){
		printf("Ethernet mode (duplex/speed): %d/%d Mbps\n", duplex, speed);
	}

	ag7240_set_mac_duplex(mac, duplex);

	return 1;
}
Esempio n. 7
0
/*
 * Called in ag7240_hw_start() function
 * */
void ag7240_mii_setup(ag7240_mac_t *mac) {
	u32 mgmt_cfg_val;
	u32 cpu_freq, ddr_freq, ahb_freq;
	u32 check_cnt;

#ifdef CFG_ATHRS27_PHY
	if (is_wasp()) {
		printf("WASP ----> S27 PHY \n");
		mgmt_cfg_val = 2;
		ar7240_reg_wr(0xb8050024, 0x271); // 25MHz ref clock
		//ar7240_reg_wr(0xb8050024, 0x570);	// 40MHz ref clock
		ag7240_reg_wr(ag7240_macs[1], AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
		ag7240_reg_wr(ag7240_macs[1], AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
		return;
	}
#endif

#ifdef CONFIG_AR7242_S16_PHY
	if (is_wasp()) {
		printf("WASP  ----> S16 PHY *\n");
		mgmt_cfg_val = 4;
		if(mac->mac_unit == 0)
		ar7240_reg_wr(AG7240_ETH_CFG, AG7240_ETH_CFG_RGMII_GE0);

		ar7240_reg_rmw_clear(AG7240_ETH_SWITCH_CLK_SPARE, (1 << 6));
		ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
		ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);

		return;
	}
#endif

#ifdef CONFIG_F1E_PHY
	if (is_wasp()) {
		printf("WASP  ----> F1 PHY *\n");
		mgmt_cfg_val = 6;
		if(mac->mac_unit == 0)
		ar7240_reg_wr(AG7240_ETH_CFG, AG7240_ETH_CFG_RGMII_GE0);

		ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
		ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);

		return;
	}
#endif

	if ((ar7240_reg_rd(AR7240_REV_ID) & AR7240_REV_ID_MASK) == AR7240_REV_1_2) {
		mgmt_cfg_val = 0x2;
		if (mac->mac_unit == 0) {
			ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
			ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
		}
	} else {
		ar933x_sys_frequency(&cpu_freq, &ddr_freq, &ahb_freq);

		switch (ahb_freq / 1000000) {
		case 150:
			mgmt_cfg_val = 0x7;
			break;
		case 175:
			mgmt_cfg_val = 0x5;
			break;
		case 200:
			mgmt_cfg_val = 0x4;
			break;
		case 210:
			mgmt_cfg_val = 0x9;
			break;
		case 220:
			mgmt_cfg_val = 0x9;
			break;
		default:
			mgmt_cfg_val = 0x7;
		}
		if ((is_ar7241() || is_ar7242())) {

			/* External MII mode */
			if (mac->mac_unit == 0 && is_ar7242()) {
				mgmt_cfg_val = 0x6;
				ar7240_reg_rmw_set(AG7240_ETH_CFG, AG7240_ETH_CFG_RGMII_GE0);
				ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
				ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
			}
			/* Virian */
			mgmt_cfg_val = 0x4;
			ag7240_reg_wr(ag7240_macs[1], AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
			ag7240_reg_wr(ag7240_macs[1], AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
			printf("Virian MDC CFG Value ==> %x\n", mgmt_cfg_val);

		} else if (is_ar933x()) {
			//GE0 receives Rx/Tx clock, and use S26 phy
			ar7240_reg_rmw_set(AG7240_ETH_CFG, AG7240_ETH_CFG_MII_GE0_SLAVE);
			mgmt_cfg_val = 0xF;
			if (mac->mac_unit == 1) {
				check_cnt = 0;
				while (check_cnt++ < 10) {
					ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
					ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
#ifdef CFG_ATHRS26_PHY
					if (athrs26_mdc_check() == 0) {
						break;
					}
#endif
				}
				if (check_cnt == 11) {
					printf("%s: MDC check failed\n", __func__);
				}
			}
		} else { /* Python 1.0 & 1.1 */
			if (mac->mac_unit == 0) {
				check_cnt = 0;
				while (check_cnt++ < 10) {
					ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
					ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
#ifdef CFG_ATHRS26_PHY
					if (athrs26_mdc_check() == 0) {
						break;
					}
#endif
				}
				if (check_cnt == 11) {
					printf("%s: MDC check failed\n", __func__);
				}
			}
		}

	}
}
Esempio n. 8
0
int ag7240_enet_initialize(bd_t * bis){
	struct eth_device *dev[CFG_AG7240_NMACS];
	u32 mask, mac_h, mac_l;
	int i;

	//printf("ag934x_enet_initialize...\n");

	/*
	if(is_ar933x() && (ar7240_reg_rd(AR7240_RESET)!=0)){
		ar7240_reg_wr(AR7240_RESET,0);
	}

	if(is_ar933x())  //Turn on LED
	ar7240_reg_wr(AR7240_GPIO_BASE + 0x28 , ar7240_reg_rd(AR7240_GPIO_BASE + 0x28)  | (0xF8));
	*/

	for(i = 0;i < CFG_AG7240_NMACS;i++){
		if((dev[i] = (struct eth_device *)malloc(sizeof(struct eth_device))) == NULL){
			//puts("malloc failed\n");
			return(0);
		}

		if((ag7240_macs[i] = (ag7240_mac_t *)malloc(sizeof(ag7240_mac_t))) == NULL){
			//puts("malloc failed\n");
			return(0);
		}

		memset(ag7240_macs[i], 0, sizeof(ag7240_macs[i]));
		memset(dev[i], 0, sizeof(dev[i]));

		sprintf(dev[i]->name, "eth%d", i);
		ag7240_get_ethaddr(dev[i]);

		ag7240_macs[i]->mac_unit = i;
		ag7240_macs[i]->mac_base = i ? AR7240_GE1_BASE : AR7240_GE0_BASE ;
		ag7240_macs[i]->dev = dev[i];

		dev[i]->iobase = 0;
		dev[i]->init = ag7240_clean_rx;
		dev[i]->halt = ag7240_halt;
		dev[i]->send = ag7240_send;
		dev[i]->recv = ag7240_recv;
		dev[i]->priv = (void *)ag7240_macs[i];
	}
	
	for(i = 0;i < CFG_AG7240_NMACS;i++){
		eth_register(dev[i]);
	
#if(CONFIG_COMMANDS & CFG_CMD_MII)
		miiphy_register(dev[i]->name, ag7240_miiphy_read, ag7240_miiphy_write);
#endif

		ag7240_reg_rmw_set(ag7240_macs[i], AG7240_MAC_CFG1, AG7240_MAC_CFG1_SOFT_RST | AG7240_MAC_CFG1_RX_RST | AG7240_MAC_CFG1_TX_RST);

		if(!i){
			mask = (AR7240_RESET_GE0_MAC | AR7240_RESET_GE0_PHY | AR7240_RESET_GE1_MAC | AR7240_RESET_GE1_PHY);

			if(is_ar7241() || is_ar7242() ||  is_wasp()){
				mask = mask | AR7240_RESET_GE0_MDIO | AR7240_RESET_GE1_MDIO;
			}

			//printf(" wasp  reset mask:%x \n",mask);

			ar7240_reg_rmw_set(AR7240_RESET, mask);
			udelay(1000 * 100);

			ar7240_reg_rmw_clear(AR7240_RESET, mask);
			udelay(1000 * 100);

			udelay(10 * 1000);
		}

		ag7240_hw_start(ag7240_macs[i]);
		ag7240_setup_fifos(ag7240_macs[i]);

		udelay(100 * 1000);

		//unsigned char *mac = dev[i]->enetaddr;
		//printf("%s: %02x:%02x:%02x:%02x:%02x:%02x\n", dev[i]->name, mac[0] & 0xff, mac[1] & 0xff, mac[2] & 0xff, mac[3] & 0xff, mac[4] & 0xff, mac[5] & 0xff);

		mac_l = (dev[i]->enetaddr[4] << 8) | (dev[i]->enetaddr[5]);
		mac_h = (dev[i]->enetaddr[0] << 24) | (dev[i]->enetaddr[1] << 16) | (dev[i]->enetaddr[2] << 8) | (dev[i]->enetaddr[3] << 0);

		ag7240_reg_wr(ag7240_macs[i], AG7240_GE_MAC_ADDR1, mac_l);
		ag7240_reg_wr(ag7240_macs[i], AG7240_GE_MAC_ADDR2, mac_h);

		/* if using header for register configuration, we have to     */
		/* configure s26 register after frame transmission is enabled */
		if(ag7240_macs[i]->mac_unit == 0){ /* WAN Phy */
#ifdef CONFIG_AR7242_S16_PHY
			if(is_ar7242() || is_wasp()){
				athrs16_reg_init();
			} else
#endif
			{
#ifdef  CFG_ATHRS17_PHY
			athrs17_reg_init();
#endif

#ifdef CFG_ATHRS26_PHY
			athrs26_reg_init();
#endif

#ifdef CFG_ATHRS27_PHY
			//printf("s27 reg init \n");
			athrs27_reg_init();
#endif

#ifdef CONFIG_F1E_PHY
			//printf("F1Phy reg init \n");
			athr_reg_init();
#endif

#ifdef CONFIG_VIR_PHY
			//printf("VIRPhy reg init \n");
			athr_vir_reg_init();
#endif

#ifdef CONFIG_F2E_PHY
			//printf("F2Phy reg init \n");
			athr_reg_init();
#endif

			}
		} else {
#ifdef CFG_ATHRS26_PHY
			athrs26_reg_init_lan();
#endif

#ifdef CFG_ATHRS27_PHY
			//printf("s27 reg init lan \n");
			athrs27_reg_init_lan();
#endif
		}

		ag7240_phy_setup(ag7240_macs[i]->mac_unit);
		//printf("%s up\n",dev[i]->name);
	}

	return(1);
}
Esempio n. 9
0
void pci_init_board (void)
#endif /* #ifdef COMPRESSED_UBOOT */
{
	uint32_t cmd;


	ar7240_reg_rmw_clear(AR7240_RESET,AR7240_RESET_PCIE_PHY_SERIAL);
	udelay(100);

	ar7240_reg_rmw_clear(AR7240_RESET, AR7240_RESET_PCIE_PHY);


	ar7240_reg_rmw_clear(AR7240_RESET, AR7240_RESET_PCIE);

	ar7240_reg_wr_nf(AR7240_PCI_LCL_RESET, 0);
	udelay(100000);

	/*
	 * Initialize PCIE PLL and get it out of RESET
	 */
	ar7240_reg_wr(AR7240_PCIE_PLL_CONFIG,0x02050800);

	ar7240_reg_wr(AR7240_PCIE_PLL_CONFIG,0x00050800);
	udelay(100);

	ar7240_reg_wr(AR7240_PCIE_PLL_CONFIG,0x00040800);
	udelay(100000);

	ar7240_reg_wr_nf(AR7240_PCI_LCL_RESET, 4);
	udelay(100000);

	cmd = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE |
	      PCI_COMMAND_PARITY|PCI_COMMAND_SERR|PCI_COMMAND_FAST_BACK;

	ar7240_local_write_config(PCI_COMMAND, 4, cmd);
	ar7240_local_write_config(0x20, 4, 0x1ff01000);
	ar7240_local_write_config(0x24, 4, 0x1ff01000);

	if ((is_ar7241() || is_ar7242() || is_wasp())) {
		ar7240_reg_wr(0x180f0000, 0x1ffc1);
	} else {
		ar7240_reg_wr(0x180f0000, 0x1);
	}

#ifdef COMPRESSED_UBOOT
	udelay(100);
#else
	udelay(1000);

	/*
	 * Check if the WLAN PCI-E H/W is present, If the
	 * WLAN H/W is not present, skip the PCI platform
	 * initialization code and return
	 */

	if (((ar7240_reg_rd(AR7240_PCI_LCL_RESET)) & 0x1) == 0x0) {
		printf("*** Warning *** : PCIe WLAN Module not found !!!\n");
		return;
	}
#endif

#ifndef COMPRESSED_UBOOT
	/*
	 * Now, configure for u-boot tools
	 */

	hose.first_busno = 0;
	hose.last_busno = 0xff;

	/* System space */
	pci_set_region(	&hose.regions[0],
			0x80000000,
			0x00000000,
			32 * 1024 * 1024,
			PCI_REGION_MEM | PCI_REGION_MEMORY);

	/* PCI memory space */
	pci_set_region(	&hose.regions[1],
			0x10000000,
			0x10000000,
			128 * 1024 * 1024,
			PCI_REGION_MEM);

	hose.region_count = 2;

	pci_register_hose(&hose);

	pci_set_ops(	&hose,
			pci_hose_read_config_byte_via_dword,
			pci_hose_read_config_word_via_dword,
			ar7240_pci_read_config,
			pci_hose_write_config_byte_via_dword,
			pci_hose_write_config_word_via_dword,
			ar7240_pci_write_config);
#endif
	plat_dev_init();
#ifdef COMPRESSED_UBOOT
	return 0;
#endif
}
Esempio n. 10
0
void pci_init_board (void)
#endif /* #ifdef COMPRESSED_UBOOT */
{
#ifdef CONFIG_AP123
	return;
#else
	uint32_t cmd = 0, reg_val;


	//printf("%s: PCIe PLL 0x%x\n", __func__, mips3_cp0_count_read());
	//printf("%s: PCIe PLL 0x%x  0xb8000008 =  0x%08x\n", __func__, mips3_cp0_count_read(), ar7240_reg_rd(0xb8040008));

	pci_udelay(100000);
	//count ++;

	if ((ar7240_reg_rd(WASP_BOOTSTRAP_REG) & WASP_REF_CLK_25) == 0) {
		ar7240_reg_wr_nf(AR934X_PCIE_PLL_DITHER_DIV_MAX,
			PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_SET(0) |
			PCIE_PLL_DITHER_DIV_MAX_USE_MAX_SET(1) |
			PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_SET(0x20) |
			PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_SET(0));
	} else {
#ifndef COMPRESSED_UBOOT
		printf("%s: PCIe PLL not set for 40MHz refclk\n", __func__);
#endif
	}

	ar7240_reg_rmw_set(AR7240_RESET, AR7240_RESET_PCIE);	// core in reset
	pci_udelay(10000);
	ar7240_reg_rmw_set(AR7240_RESET, AR7240_RESET_PCIE_PHY);// phy in reset
	pci_udelay(10000);
	ar7240_reg_rmw_clear(RST_MISC2_ADDRESS, RST_MISC2_PERSTN_RCPHY_SET(1)); // pci phy analog in reset
	pci_udelay(10000);
	ar7240_reg_wr(0x180f0000, 0x1ffc0);			// ltssm is disabled
	pci_udelay(100);
	ar7240_reg_wr_nf(AR7240_PCI_LCL_RESET, 0);	// End point in reset
	pci_udelay(100000);


	//ar7240_reg_rmw_clear(AR7240_RESET, AR7240_RESET_PCIE_PHY);

	if ((ar7240_reg_rd(AR7240_REV_ID) & 0xf) == 0) {
		ar7240_reg_wr_nf(AR934X_PCIE_PLL_CONFIG,
			PCIE_PLL_CONFIG_REFDIV_SET(1) |
			PCIE_PLL_CONFIG_BYPASS_SET(1) |
			PCIE_PLL_CONFIG_PLLPWD_SET(1));
		pci_udelay(10000);
		ar7240_reg_wr_nf(AR934X_PCIE_PLL_CONFIG,
			PCIE_PLL_CONFIG_REFDIV_SET(1) |
			PCIE_PLL_CONFIG_BYPASS_SET(1) |
			PCIE_PLL_CONFIG_PLLPWD_SET(0));
		pci_udelay(1000);
		ar7240_reg_wr_nf(AR934X_PCIE_PLL_CONFIG,
			ar7240_reg_rd(AR934X_PCIE_PLL_CONFIG) &
			(~PCIE_PLL_CONFIG_BYPASS_SET(1)));
		pci_udelay(1000);
	} else {
		ar7240_reg_wr_nf(AR934X_PCIE_PLL_CONFIG,
			PCIE_PLL_CONFIG_REFDIV_SET(2) |
			PCIE_PLL_CONFIG_BYPASS_SET(1) |
			PCIE_PLL_CONFIG_PLLPWD_SET(1));
		pci_udelay(10000);

		if ((ar7240_reg_rd(WASP_BOOTSTRAP_REG) & WASP_REF_CLK_25) == 0) {
			ar7240_reg_wr_nf(0xb8116c00, (0x5 << 27) | (160 << 18) | 0);
		} else {
			ar7240_reg_wr_nf(0xb8116c00, (0x2 << 27) | (0x28 << 18) | 0);
		}
		do {
			ar7240_reg_wr_nf(0xb8116c04, (0x1 << 30) | (0x4 << 26) | (0x32 << 19) | (1 << 16) | (3 << 13) | (0x1e << 7));
			ar7240_reg_wr_nf(0xb8116c08, (6 << 23));
			pci_udelay(10000);
			ar7240_reg_wr_nf(0xb8116c04, (0x1 << 30) | (0x4 << 26) | (0x32 << 19) | (3 << 13) | (0x1e << 7));

			ar7240_reg_rmw_clear(KSEG1ADDR(PCIe_DPLL3_ADDRESS), PCIe_DPLL3_DO_MEAS_SET(1));
			ar7240_reg_rmw_set(KSEG1ADDR(PCIe_DPLL3_ADDRESS), PCIe_DPLL3_DO_MEAS_SET(1));

			ar7240_reg_wr(0xb804000c, 1 << 2);

			pci_udelay(1000);

			while (((cmd = ar7240_reg_rd(PCIe_DPLL4_ADDRESS)) & PCIe_DPLL4_MEAS_DONE_SET(1)) == 0) {
				printf("0x%x 0x%x 0x%x\n", KSEG1ADDR(PCIe_DPLL4_ADDRESS), cmd);
				pci_udelay(10);
			}

			{ int i; for (i = 0; i < 100; i++) udelay(10); }
#if 0
			msdvc = PCIe_DPLL4_MEAN_DVC_GET(cmd);
			cmd = PCIe_DPLL3_SQSUM_DVC_GET(ar7240_reg_rd(PCIe_DPLL3_ADDRESS));

			if (msdvc & 0x400) msdvc = ((~msdvc & 0x7FF) + 1); /* 11 bit signed number , but not intentioanlly multiply by (-1), ASK VIPUL*/
			msdvc =  cmd - (msdvc *msdvc);
			msdvc_sq = msdvc * msdvc;

			if (cmd >= 0x40000) {
				err_count++;
				if (sqsum_min_fail == 0)
					sqsum_min_fail = cmd;
				if (cmd > sqsum_max_fail)
					sqsum_max_fail = cmd;
				if (cmd < sqsum_min_fail)
					sqsum_min_fail = cmd;
				sqsum_avg_fail = (sqsum_avg_fail - (sqsum_avg_fail / err_count)) + (cmd / err_count);

				if (num_pll_loops == 0)
					err_pll1++;
				if (num_pll_loops == 1)
					err_pll2++;
				if (num_pll_loops == 2)
					err_pll3++;
				if (num_pll_loops == 3)
					err_pll4++;
				if (num_pll_loops == 4) {
					err_pll5++;
					break;
				}
			} else {
				if (sqsum_min == 0)
					sqsum_min = cmd;
				if (cmd < sqsum_min)
					sqsum_min = cmd;
				if (cmd > sqsum_max)
					sqsum_max = cmd;
				//sqsum_avg = (sqsum_avg - (sqsum_avg / count)) + (cmd / count);
				sqsum_avg += cmd;

				/*msdvc calc*/
				if (msdvc_min == 0) msdvc_min = msdvc;
				if (msdvc < msdvc_min) msdvc_min =msdvc;
				if (msdvc > msdvc_max) msdvc_max =msdvc;
				msdvc_avg += msdvc;
				msdvc_sq_avg += msdvc_sq;

			}
			num_pll_loops++;
#endif

		} while ((cmd = PCIe_DPLL3_SQSUM_DVC_GET(ar7240_reg_rd(PCIe_DPLL3_ADDRESS))) >= 0x40000);

		ar7240_reg_rmw_clear(AR934X_PCIE_PLL_CONFIG, PCIE_PLL_CONFIG_PLLPWD_SET(1));
		pci_udelay(10000);
		ar7240_reg_rmw_clear(AR934X_PCIE_PLL_CONFIG, PCIE_PLL_CONFIG_BYPASS_SET(1));
		pci_udelay(10000);

		/*
		 * PCIe Dithering configuration
		 */
		if (is_ar934x_12_or_later()) {
			ar7240_reg_wr_nf(PCIe_DPLL2_ADDRESS,
					PCIe_DPLL2_LOCAL_PLL_SET(0) | 
					PCIe_DPLL2_KI_SET(0x4)| 
					PCIe_DPLL2_KD_SET(0x40));
			ar7240_reg_wr_nf(AR934X_PCIE_PLL_CONFIG, 0x40010800);
			ar7240_reg_wr_nf(AR934X_PCIE_PLL_DITHER_DIV_MAX, 0xc013fffe);
			ar7240_reg_wr_nf(AR934X_PCIE_PLL_DITHER_DIV_MIN, 0x0013e666);

			ar7240_reg_wr_nf(AR934X_PCIE_PLL_CONFIG, 0x00010800);  
			ar7240_reg_wr_nf(AR934X_PCIE_PLL_CONFIG, 0x00000800);  
		}

		//run_command("md 0xb8116c00 4", 0);
	}
	ar7240_reg_rmw_set(RST_MISC2_ADDRESS, RST_MISC2_PERSTN_RCPHY_SET(1)); // pci phy analog out of reset
	pci_udelay(10000);

	ar7240_reg_rmw_clear(AR7240_RESET, AR7240_RESET_PCIE_PHY);	// phy out of reset
	pci_udelay(10000);

	ar7240_reg_rmw_clear(AR7240_RESET, AR7240_RESET_PCIE);	// core out of reset
	pci_udelay(1000);

	cmd = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE |
	      PCI_COMMAND_PARITY|PCI_COMMAND_SERR|PCI_COMMAND_FAST_BACK;

	ar7240_local_write_config(PCI_COMMAND, 4, cmd);		// pci cmd reg init
	ar7240_local_write_config(0x20, 4, 0x1ff01000);		// membase setting
	ar7240_local_write_config(0x24, 4, 0x1ff01000);		// prefetch membase setting


	if ((is_ar7241() || is_ar7242() || is_wasp())) {
		ar7240_reg_wr(0x180f0000, 0x1ffc1);		// ltssm enable
	} else {
		ar7240_reg_wr(0x180f0000, 0x1);
	}
	pci_udelay(100000);

	ar7240_reg_wr_nf(AR7240_PCI_LCL_RESET, 4);		// EP out of reset
	pci_udelay(100000);


#ifdef COMPRESSED_UBOOT
	pci_udelay(100);
#else
	/*
	 *  Delay increased from 100 to 1000, so as to
	 *  get the correct status from PCI LCL RESET register
	 */
	pci_udelay(100000);

	/*
	 * Check if the WLAN PCI-E H/W is present, If the
	 * WLAN H/W is not present, skip the PCI platform
	 * initialization code and return
	 */

	if (((ar7240_reg_rd(AR7240_PCI_LCL_RESET)) & 0x1) == 0x0) {
		printf("*** Warning *** : PCIe WLAN Module not found !!!\n");
		return;
	}
#endif

#ifndef COMPRESSED_UBOOT
	/*
	 * Now, configure for u-boot tools
	 */

	hose.first_busno = 0;
	hose.last_busno = 0xff;

	/* System space */
	pci_set_region(	&hose.regions[0],
			0x80000000,
			0x00000000,
			32 * 1024 * 1024,
			PCI_REGION_MEM | PCI_REGION_MEMORY);

	/* PCI memory space */
	pci_set_region(	&hose.regions[1],
			0x10000000,
			0x10000000,
			128 * 1024 * 1024,
			PCI_REGION_MEM);

	hose.region_count = 2;

	pci_register_hose(&hose);

	pci_set_ops(	&hose,
			pci_hose_read_config_byte_via_dword,
			pci_hose_read_config_word_via_dword,
			ar7240_pci_read_config,
			pci_hose_write_config_byte_via_dword,
			pci_hose_write_config_word_via_dword,
			ar7240_pci_write_config);
#endif
	plat_dev_init();
#endif	// CONFIG_AP123
#ifdef COMPRESSED_UBOOT
	return 0;
#endif
}