/** * ispccdc_free_lsc - Frees Lens Shading Compensation table * * Always returns 0. **/ static int ispccdc_free_lsc(void) { if (!lsc_ispmmu_addr) return 0; ispccdc_enable_lsc(0); lsc_initialized = 0; isp_reg_writel(0, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_LSC_TABLE_BASE); ispmmu_kunmap(lsc_ispmmu_addr); kfree(lsc_gain_table); return 0; }
/** * isp_ccdc_cleanup - CCDC module cleanup. **/ void isp_ccdc_cleanup(void) { if (is_isplsc_activated()) { ispccdc_free_lsc(); kfree(lsc_gain_table_tmp); } if (fpc_table_add_m != 0) { ispmmu_kunmap(fpc_table_add_m); kfree(fpc_table_add); } }
void isp_af_exit(void) { int i; /* Free buffers */ for (i = 0; i < H3A_MAX_BUFF; i++) { if (!afstat.af_buff[i].phy_addr) continue; ispmmu_kunmap(afstat.af_buff[i].ispmmu_addr); dma_free_coherent(NULL, afstat.min_buf_size, (void *)afstat.af_buff[i].virt_addr, (dma_addr_t)afstat.af_buff[i].phy_addr); } kfree(af_dev_configptr->config); kfree(af_dev_configptr); memset(&afstat, 0, sizeof(afstat)); af_major = -1; }
/* Function to perform hardware set up */ int isp_af_configure(struct af_configuration *afconfig) { int result; int buff_size, i; unsigned int busyaf; struct af_configuration *af_curr_cfg = af_dev_configptr->config; if (NULL == afconfig) { printk(KERN_ERR "Null argument in configuration. \n"); return -EINVAL; } memcpy(af_curr_cfg, afconfig, sizeof(struct af_configuration)); /* Get the value of PCR register */ busyaf = isp_reg_readl(OMAP3_ISP_IOMEM_H3A, ISPH3A_PCR); if ((busyaf & AF_BUSYAF) == AF_BUSYAF) { DPRINTK_ISP_AF("AF_register_setup_ERROR : Engine Busy"); DPRINTK_ISP_AF("\n Configuration cannot be done "); return -AF_ERR_ENGINE_BUSY; } /* Check IIR Coefficient and start Values */ result = isp_af_check_iir(); if (result < 0) return result; /* Check Paxel Values */ result = isp_af_check_paxel(); if (result < 0) return result; /* Check HMF Threshold Values */ if (af_curr_cfg->hmf_config.threshold > AF_THRESHOLD_MAX) { DPRINTK_ISP_AF("Error : HMF Threshold is incorrect"); return -AF_ERR_THRESHOLD; } /* Compute buffer size */ buff_size = (af_curr_cfg->paxel_config.hz_cnt + 1) * (af_curr_cfg->paxel_config.vt_cnt + 1) * AF_PAXEL_SIZE; afstat.curr_cfg_buf_size = buff_size; /* Deallocate the previous buffers */ if (afstat.stats_buf_size && buff_size > afstat.stats_buf_size) { isp_af_enable(0); for (i = 0; i < H3A_MAX_BUFF; i++) { ispmmu_kunmap(afstat.af_buff[i].ispmmu_addr); free_pages_exact((void *)afstat.af_buff[i].virt_addr, afstat.min_buf_size); afstat.af_buff[i].virt_addr = 0; } afstat.stats_buf_size = 0; } if (!afstat.af_buff[0].virt_addr) { afstat.stats_buf_size = buff_size; afstat.min_buf_size = PAGE_ALIGN(afstat.stats_buf_size); for (i = 0; i < H3A_MAX_BUFF; i++) { afstat.af_buff[i].virt_addr = (unsigned long)alloc_pages_exact( afstat.min_buf_size, GFP_KERNEL | GFP_DMA); if (afstat.af_buff[i].virt_addr == 0) { printk(KERN_ERR "Can't acquire memory for " "buffer[%d]\n", i); return -ENOMEM; } afstat.af_buff[i].phy_addr = dma_map_single(NULL, (void *)afstat.af_buff[i].virt_addr, afstat.min_buf_size, DMA_FROM_DEVICE); afstat.af_buff[i].addr_align = afstat.af_buff[i].virt_addr; while ((afstat.af_buff[i].addr_align & 0xFFFFFFC0) != afstat.af_buff[i].addr_align) afstat.af_buff[i].addr_align++; afstat.af_buff[i].ispmmu_addr = ispmmu_kmap(afstat.af_buff[i].phy_addr, afstat.min_buf_size); } isp_af_unlock_buffers(); isp_af_link_buffers(); /* First active buffer */ if (active_buff == NULL) active_buff = &afstat.af_buff[0]; isp_af_set_address(active_buff->ispmmu_addr); } result = isp_af_register_setup(af_dev_configptr); if (result < 0) return result; af_dev_configptr->size_paxel = buff_size; atomic_inc(&afstat.config_counter); afstat.initialized = 1; afstat.frame_count = 1; active_buff->frame_num = 1; /* Set configuration flag to indicate HW setup done */ if (af_curr_cfg->af_config) isp_af_enable(1); else isp_af_enable(0); /* Success */ return 0; }