void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; u8 byte; device_t dev; #if IS_ENABLED(CONFIG_POST_DEVICE_PCI_PCIE) hudson_pci_port80(); #endif #if IS_ENABLED(CONFIG_POST_DEVICE_LPC) hudson_lpc_port80(); #endif val = agesawrapper_amdinitmmio(); if (!cpu_init_detectedx && boot_cpu()) { /* enable SIO LPC decode */ dev = PCI_DEV(0, 0x14, 3); byte = pci_read_config8(dev, 0x48); byte |= 3; /* 2e, 2f */ pci_write_config8(dev, 0x48, byte); /* enable serial decode */ byte = pci_read_config8(dev, 0x44); byte |= (1 << 6); /* 0x3f8 */ pci_write_config8(dev, 0x44, byte); post_code(0x30); /* enable SB MMIO space */ outb(0x24, 0xcd6); outb(0x1, 0xcd7); /* enable SIO clock */ sbxxx_enable_48mhzout(); ite_kill_watchdog(GPIO_DEV); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); ite_enable_3vsbsw(GPIO_DEV); console_init(); /* turn on secondary smbus at b20 */ outb(0x28, 0xcd6); byte = inb(0xcd7); byte |= 1; outb(byte, 0xcd7); /* set DDR3 voltage */ byte = CONFIG_BOARD_ASUS_F2A85_M_DDR3_VOLT_VAL; /* default is byte = 0x0, so no need to set it in this case */ if (byte) do_smbus_write_byte(0xb20, 0x15, 0x3, byte); } /* Halt if there was a built in self test failure */ post_code(0x34); report_bist_failure(bist); /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); post_code(0x37); printk(BIOS_DEBUG, "agesawrapper_amdinitreset "); val = agesawrapper_amdinitreset(); if(val) { printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val); } post_code(0x39); val = agesawrapper_amdinitearly (); if(val) { printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val); } printk(BIOS_DEBUG, "Got past agesawrapper_amdinitearly\n"); int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); if (!s3resume) { post_code(0x40); val = agesawrapper_amdinitpost (); if(val) { printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val); } printk(BIOS_DEBUG, "Got past agesawrapper_amdinitpost\n"); post_code(0x41); val = agesawrapper_amdinitenv (); if(val) { printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val); } printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n"); disable_cache_as_ram(); } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); printk(BIOS_DEBUG, "agesawrapper_amdinitresume "); val = agesawrapper_amdinitresume(); if (val) printk(BIOS_DEBUG, "error level: %x \n", val); else printk(BIOS_DEBUG, "passed.\n"); printk(BIOS_DEBUG, "agesawrapper_amds3laterestore "); val = agesawrapper_amds3laterestore (); if (val) printk(BIOS_DEBUG, "error level: %x \n", val); else printk(BIOS_DEBUG, "passed.\n"); post_code(0x61); prepare_for_resume(); } post_code(0x50); copy_and_run(); post_code(0x54); /* Should never see this post code. */ }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { // Node 0 DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, // Node 1 DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0, }; unsigned bsp_apicid = 0; int needs_reset = 0; struct sys_info *sysinfo = &sysinfo_car; ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); ite_kill_watchdog(GPIO_DEV); ite_enable_3vsbsw(GPIO_DEV); console_init(); enable_rom_decode(); printk(BIOS_INFO, "now booting...\n"); if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* Halt if there was a built in self test failure. */ report_bist_failure(bist); setup_default_resource_map(); setup_coherent_ht_domain(); wait_all_core0_started(); printk(BIOS_INFO, "now booting... All core 0 started\n"); #if CONFIG_LOGICAL_CPUS /* It is said that we should start core1 after all core0 launched. */ start_other_cores(); wait_all_other_cores_started(bsp_apicid); #endif init_timer(); ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */ needs_reset = optimize_link_coherent_ht(); print_debug_hex8(needs_reset); needs_reset |= optimize_link_incoherent_ht(sysinfo); print_debug_hex8(needs_reset); needs_reset |= k8t890_early_setup_ht(); print_debug_hex8(needs_reset); vt8237_early_network_init(NULL); vt8237_early_spi_init(); if (needs_reset) { printk(BIOS_DEBUG, "ht reset -\n"); soft_reset(); printk(BIOS_DEBUG, "FAILED!\n"); } /* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */ /* allow LDT STOP asserts */ vt8237_sb_enable_fid_vid(); enable_fid_change(); print_debug("after enable_fid_change\n"); init_fidvid_bsp(bsp_apicid); /* Stop the APs so we can start them later in init. */ allow_all_aps_stop(bsp_apicid); /* It's the time to set ctrl now. */ fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); enable_smbus(); sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); post_cache_as_ram(); }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; u8 byte; device_t dev; #if IS_ENABLED(CONFIG_POST_DEVICE_PCI_PCIE) hudson_pci_port80(); #endif #if IS_ENABLED(CONFIG_POST_DEVICE_LPC) hudson_lpc_port80(); #endif #if CONFIG_HAVE_ACPI_RESUME void *resume_backup_memory; #endif val = agesawrapper_amdinitmmio(); if (!cpu_init_detectedx && boot_cpu()) { /* enable SIO LPC decode */ dev = PCI_DEV(0, 0x14, 3); byte = pci_read_config8(dev, 0x48); byte |= 3; /* 2e, 2f */ pci_write_config8(dev, 0x48, byte); /* enable serial decode */ byte = pci_read_config8(dev, 0x44); byte |= (1 << 6); /* 0x3f8 */ pci_write_config8(dev, 0x44, byte); post_code(0x30); /* enable SB MMIO space */ outb(0x24, 0xcd6); outb(0x1, 0xcd7); /* enable SIO clock */ sbxxx_enable_48mhzout(); ite_kill_watchdog(GPIO_DEV); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); ite_enable_3vsbsw(GPIO_DEV); console_init(); /* turn on secondary smbus at b20 */ outb(0x28, 0xcd6); byte = inb(0xcd7); byte |= 1; outb(byte, 0xcd7); /* set DDR3 voltage */ byte = CONFIG_BOARD_ASUS_F2A85_M_DDR3_VOLT_VAL; /* default is byte = 0x0, so no need to set it in this case */ if (byte) do_smbus_write_byte(0xb20, 0x15, 0x3, byte); } /* Halt if there was a built in self test failure */ post_code(0x34); report_bist_failure(bist); /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); post_code(0x37); printk(BIOS_DEBUG, "agesawrapper_amdinitreset "); val = agesawrapper_amdinitreset(); if(val) { printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val); } post_code(0x39); val = agesawrapper_amdinitearly (); if(val) { printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val); } printk(BIOS_DEBUG, "Got past agesawrapper_amdinitearly\n"); #if CONFIG_HAVE_ACPI_RESUME if (!acpi_is_wakeup_early()) { /* Check for S3 resume */ #endif post_code(0x40); val = agesawrapper_amdinitpost (); if(val) { printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val); } printk(BIOS_DEBUG, "Got past agesawrapper_amdinitpost\n"); post_code(0x41); val = agesawrapper_amdinitenv (); if(val) { printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val); } printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n"); disable_cache_as_ram(); #if CONFIG_HAVE_ACPI_RESUME } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); printk(BIOS_DEBUG, "agesawrapper_amdinitresume "); val = agesawrapper_amdinitresume(); if (val) printk(BIOS_DEBUG, "error level: %x \n", val); else printk(BIOS_DEBUG, "passed.\n"); printk(BIOS_DEBUG, "agesawrapper_amds3laterestore "); val = agesawrapper_amds3laterestore (); if (val) printk(BIOS_DEBUG, "error level: %x \n", val); else printk(BIOS_DEBUG, "passed.\n"); post_code(0x61); printk(BIOS_DEBUG, "Find resume memory location\n"); resume_backup_memory = (void *)backup_resume(); post_code(0x62); printk(BIOS_DEBUG, "Move CAR stack.\n"); move_stack_high_mem(); printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE)); post_code(0x63); disable_cache_as_ram(); printk(BIOS_DEBUG, "CAR disabled.\n"); set_resume_cache(); /* * Copy the system memory that is in the ramstage area to the * reserved area. */ if (resume_backup_memory) memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE); printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n"); } #endif post_code(0x50); copy_and_run(); post_code(0x54); /* Should never see this post code. */ }