static int show_stmt_assign_sig_darray(ivl_statement_t net) { int errors = 0; ivl_lval_t lval = ivl_stmt_lval(net, 0); ivl_expr_t rval = ivl_stmt_rval(net); ivl_expr_t part = ivl_lval_part_off(lval); ivl_signal_t var= ivl_lval_sig(lval); ivl_type_t var_type= ivl_signal_net_type(var); assert(ivl_type_base(var_type) == IVL_VT_DARRAY); ivl_type_t element_type = ivl_type_element(var_type); ivl_expr_t mux = ivl_lval_idx(lval); assert(ivl_stmt_lvals(net) == 1); assert(ivl_stmt_opcode(net) == 0); assert(ivl_lval_mux(lval) == 0); assert(part == 0); if (mux && (ivl_type_base(element_type)==IVL_VT_REAL)) { draw_eval_real(rval); /* The %set/dar expects the array index to be in index register 3. Calculate the index in place. */ draw_eval_expr_into_integer(mux, 3); fprintf(vvp_out, " %%store/dar/r v%p_0;\n", var); } else if (mux && ivl_type_base(element_type)==IVL_VT_STRING) { /* Evaluate the rval into the top of the string stack. */ draw_eval_string(rval); /* The %store/dar/s expects the array index to me in index register 3. Calculate the index in place. */ draw_eval_expr_into_integer(mux, 3); fprintf(vvp_out, " %%store/dar/str v%p_0;\n", var); } else if (mux) { struct vector_info rvec = draw_eval_expr_wid(rval, ivl_lval_width(lval), STUFF_OK_XZ); /* The %set/dar expects the array index to be in index register 3. Calculate the index in place. */ draw_eval_expr_into_integer(mux, 3); fprintf(vvp_out, " %%set/dar v%p_0, %u, %u;\n", var, rvec.base, rvec.wid); if (rvec.base >= 4) clr_vector(rvec); } else { /* There is no l-value mux, so this must be an assignment to the array as a whole. Evaluate the "object", and store the evaluated result. */ errors += draw_eval_object(rval); fprintf(vvp_out, " %%store/obj v%p_0;\n", var); } return errors; }
static int show_stmt_cassign(ivl_statement_t net) { ivl_lval_t lval; ivl_signal_t lsig; unsigned idx; char*tmp_label; assert(ivl_stmt_lvals(net) == 1); lval = ivl_stmt_lval(net, 0); lsig = ivl_lval_sig(lval); assert(lsig != 0); assert(ivl_lval_mux(lval) == 0); assert(ivl_signal_pins(lsig) == ivl_stmt_nexus_count(net)); assert(ivl_lval_part_off(lval) == 0); tmp_label = strdup(vvp_signal_label(lsig)); for (idx = 0 ; idx < ivl_stmt_nexus_count(net) ; idx += 1) { fprintf(vvp_out, " %%cassign V_%s[%u], %s;\n", tmp_label, idx, draw_net_input(ivl_stmt_nexus(net, idx))); } free(tmp_label); return 0; }
static int show_stmt_release(ivl_statement_t net) { ivl_lval_t lval; ivl_signal_t lsig; unsigned idx; /* If there are no l-vals (the target signal has been elided) then turn the release into a no-op. In other words, we are done before we start. */ if (ivl_stmt_lvals(net) == 0) return 0; assert(ivl_stmt_lvals(net) == 1); lval = ivl_stmt_lval(net, 0); lsig = ivl_lval_sig(lval); assert(lsig != 0); assert(ivl_lval_mux(lval) == 0); assert(ivl_lval_part_off(lval) == 0); /* On release, reg variables hold the value that was forced on to them. */ for (idx = 0 ; idx < ivl_lval_pins(lval) ; idx += 1) { if (ivl_signal_type(lsig) == IVL_SIT_REG) { fprintf(vvp_out, " %%load 4, V_%s[%u];\n", vvp_signal_label(lsig), idx); fprintf(vvp_out, " %%set V_%s[%u], 4;\n", vvp_signal_label(lsig), idx); } fprintf(vvp_out, " %%release V_%s[%u];\n", vvp_signal_label(lsig), idx); } return 0; }
static void set_to_lvariable(ivl_lval_t lval, unsigned idx, unsigned bit, unsigned wid) { ivl_signal_t sig = ivl_lval_sig(lval); unsigned part_off = ivl_lval_part_off(lval); if (ivl_lval_mux(lval)) { assert(wid == 1); if ((ivl_signal_pins(sig)-1) <= 0xffffU) { fprintf(vvp_out, " %%set/x0 V_%s, %u, %u;\n", vvp_signal_label(sig), bit, ivl_signal_pins(sig)-1); } else { /* If the target bound is too big for the %set/x0 instruction, then use the %set/x0/x instruction instead. */ fprintf(vvp_out, " %%ix/load 3, %u;\n", ivl_signal_pins(sig)-1); fprintf(vvp_out, " %%set/x0/x V_%s, %u, 3;\n", vvp_signal_label(sig), bit); } } else if (wid == 1) { fprintf(vvp_out, " %%set V_%s[%u], %u;\n", vvp_signal_label(sig), idx+part_off, bit); } else { fprintf(vvp_out, " %%set/v V_%s[%u], %u, %u;\n", vvp_signal_label(sig), idx+part_off, bit, wid); } }
static int show_stmt_force(ivl_statement_t net) { ivl_lval_t lval; ivl_signal_t lsig; unsigned idx; static unsigned force_functor_label = 0; char*tmp_label; assert(ivl_stmt_lvals(net) == 1); lval = ivl_stmt_lval(net, 0); lsig = ivl_lval_sig(lval); assert(lsig != 0); assert(ivl_lval_mux(lval) == 0); assert(ivl_lval_part_off(lval) == 0); force_functor_label += 1; tmp_label = strdup(vvp_signal_label(lsig)); for (idx = 0 ; idx < ivl_lval_pins(lval) ; idx += 1) { fprintf(vvp_out, "f_%u.%u .force V_%s[%u], %s;\n", force_functor_label, idx, tmp_label, idx, draw_net_input(ivl_stmt_nexus(net, idx))); } free(tmp_label); for (idx = 0 ; idx < ivl_lval_pins(lval) ; idx += 1) { fprintf(vvp_out, " %%force f_%u.%u, 1;\n", force_functor_label, idx); } return 0; }
static void assign_to_lvector(ivl_lval_t lval, unsigned idx, unsigned bit, unsigned delay, unsigned width) { ivl_signal_t sig = ivl_lval_sig(lval); unsigned part_off = ivl_lval_part_off(lval); assert(ivl_lval_mux(lval) == 0); fprintf(vvp_out, " %%ix/load 0, %u;\n", width); fprintf(vvp_out, " %%assign/v0 V_%s[%u], %u, %u;\n", vvp_signal_label(sig), part_off+idx, delay, bit); }
static int show_stmt_assign_sig_string(ivl_statement_t net) { ivl_lval_t lval = ivl_stmt_lval(net, 0); ivl_expr_t rval = ivl_stmt_rval(net); ivl_expr_t part = ivl_lval_part_off(lval); ivl_expr_t aidx = ivl_lval_idx(lval); ivl_signal_t var= ivl_lval_sig(lval); assert(ivl_stmt_lvals(net) == 1); assert(ivl_stmt_opcode(net) == 0); assert(ivl_lval_mux(lval) == 0); /* Simplest case: no mux. Evaluate the r-value as a string and store the result into the variable. Note that the %store/str opcode pops the string result. */ if (part == 0 && aidx == 0) { draw_eval_string(rval); fprintf(vvp_out, " %%store/str v%p_0;\n", var); return 0; } /* Assign to array. The l-value has an index expression expression so we are assigning to an array word. */ if (aidx != 0) { unsigned ix; assert(part == 0); draw_eval_string(rval); draw_eval_expr_into_integer(aidx, (ix = allocate_word())); fprintf(vvp_out, " %%store/stra v%p, %u;\n", var, ix); clr_word(ix); return 0; } /* Calculate the character select for the word. */ int mux_word = allocate_word(); draw_eval_expr_into_integer(part, mux_word); /* Evaluate the r-value as a vector. */ struct vector_info rvec = draw_eval_expr_wid(rval, 8, STUFF_OK_XZ); assert(rvec.wid == 8); fprintf(vvp_out, " %%putc/str/v v%p_0, %d, %u;\n", var, mux_word, rvec.base); clr_vector(rvec); clr_word(mux_word); return 0; }
/* * This generates an assign to a single bit of an lvalue variable. If * the bit is a part select, then index the label to set the right * bit. If there is an lvalue mux, then use the indexed assign to make * a calculated assign. */ static void assign_to_lvariable(ivl_lval_t lval, unsigned idx, unsigned bit, unsigned delay, int delay_in_index_flag) { ivl_signal_t sig = ivl_lval_sig(lval); unsigned part_off = ivl_lval_part_off(lval); char *delay_suffix = delay_in_index_flag? "/d" : ""; if (ivl_lval_mux(lval)) fprintf(vvp_out, " %%assign/x0%s V_%s, %u, %u;\n", delay_suffix, vvp_signal_label(sig), delay, bit); else fprintf(vvp_out, " %%assign%s V_%s[%u], %u, %u;\n", delay_suffix, vvp_signal_label(sig), idx+part_off, delay, bit); }
/* * An assignment is one of a possible list of l-values to a behavioral * assignment. Each l-value is either a part select of a signal or a * non-constant bit select. */ static void show_assign_lval(ivl_lval_t lval) { ivl_nexus_t nex; ivl_signal_t sig=NULL; unsigned idx; unsigned lsb=0; assert(ivl_lval_mux(lval) == 0); assert(ivl_lval_mem(lval) == 0); nex = ivl_lval_pin(lval, 0); for (idx = 0 ; idx < ivl_nexus_ptrs(nex) ; idx += 1) { unsigned pin; ivl_nexus_ptr_t ptr; ptr = ivl_nexus_ptr(nex, idx); sig = ivl_nexus_ptr_sig(ptr); if (sig == 0) continue; lsb = ivl_nexus_ptr_pin(ptr); for (pin = 1 ; pin < ivl_lval_pins(lval) ; pin += 1) { if (ivl_signal_pin(sig, lsb+pin) != ivl_lval_pin(lval,pin)) break; } if (pin < ivl_lval_pins(lval)) continue; break; } assert(sig); if ((lsb > 0) || (lsb + ivl_lval_pins(lval)) < ivl_signal_pins(sig)) { fprintf(out, "%s[%u:%u]", ivl_signal_name(sig), lsb+ivl_lval_pins(lval)-1, lsb); } else { fprintf(out, "%s", ivl_signal_name(sig)); } }
static int show_stmt_deassign(ivl_statement_t net) { ivl_lval_t lval; ivl_signal_t lsig; unsigned idx; assert(ivl_stmt_lvals(net) == 1); lval = ivl_stmt_lval(net, 0); lsig = ivl_lval_sig(lval); assert(lsig != 0); assert(ivl_lval_mux(lval) == 0); assert(ivl_lval_part_off(lval) == 0); for (idx = 0 ; idx < ivl_lval_pins(lval) ; idx += 1) { fprintf(vvp_out, " %%deassign V_%s[%u], 1;\n", vvp_signal_label(lsig), idx); } return 0; }
static void get_vec_from_lval_slice(ivl_lval_t lval, struct vec_slice_info*slice, unsigned bit, unsigned wid) { ivl_signal_t sig = ivl_lval_sig(lval); ivl_expr_t part_off_ex = ivl_lval_part_off(lval); unsigned long part_off = 0; /* Although Verilog doesn't support it, we'll handle here the case of an l-value part select of an array word if the address is constant. */ ivl_expr_t word_ix = ivl_lval_idx(lval); unsigned long use_word = 0; if (part_off_ex == 0) { part_off = 0; } else if (number_is_immediate(part_off_ex, IMM_WID, 0) && !number_is_unknown(part_off_ex)) { part_off = get_number_immediate(part_off_ex); part_off_ex = 0; } /* If the word index is a constant expression, then evaluate it to select the word, and pay no further heed to the expression itself. */ if (word_ix && number_is_immediate(word_ix, IMM_WID, 0)) { assert(! number_is_unknown(word_ix)); use_word = get_number_immediate(word_ix); word_ix = 0; } if (ivl_lval_mux(lval)) part_off_ex = ivl_lval_mux(lval); if (ivl_signal_dimensions(sig)==0 && part_off_ex==0 && word_ix==0 && part_off==0 && wid==ivl_signal_width(sig)) { slice->type = SLICE_SIMPLE_VECTOR; slice->u_.simple_vector.use_word = use_word; fprintf(vvp_out, " %%load/v %u, v%p_%lu, %u;\n", bit, sig, use_word, wid); } else if (ivl_signal_dimensions(sig)==0 && part_off_ex==0 && word_ix==0) { assert(use_word == 0); slice->type = SLICE_PART_SELECT_STATIC; slice->u_.part_select_static.part_off = part_off; fprintf(vvp_out, " %%ix/load 1, %lu, 0;\n", part_off); fprintf(vvp_out, " %%load/x1p %u, v%p_0, %u;\n", bit, sig, wid); } else if (ivl_signal_dimensions(sig)==0 && part_off_ex!=0 && word_ix==0) { unsigned skip_set = transient_id++; unsigned out_set = transient_id++; assert(use_word == 0); assert(part_off == 0); slice->type = SLICE_PART_SELECT_DYNAMIC; draw_eval_expr_into_integer(part_off_ex, 1); slice->u_.part_select_dynamic.word_idx_reg = allocate_word(); slice->u_.part_select_dynamic.x_flag = allocate_vector(1); fprintf(vvp_out, " %%mov %u, %u, 1;\n", slice->u_.part_select_dynamic.x_flag, 4); fprintf(vvp_out, " %%mov/wu %d, %d;\n", slice->u_.part_select_dynamic.word_idx_reg, 1); fprintf(vvp_out, " %%jmp/1 t_%u, 4;\n", skip_set); fprintf(vvp_out, " %%load/x1p %u, v%p_0, %u;\n", bit, sig, wid); fprintf(vvp_out, " %%jmp t_%u;\n", out_set); fprintf(vvp_out, "t_%u ;\n", skip_set); fprintf(vvp_out, " %%mov %u, 2, %u;\n", bit, wid); fprintf(vvp_out, "t_%u ;\n", out_set); } else if (ivl_signal_dimensions(sig) > 0 && word_ix == 0) { slice->type = SLICE_MEMORY_WORD_STATIC; slice->u_.memory_word_static.use_word = use_word; if (use_word < ivl_signal_array_count(sig)) { fprintf(vvp_out, " %%ix/load 3, %lu, 0;\n", use_word); fprintf(vvp_out, " %%load/av %u, v%p, %u;\n", bit, sig, wid); } else { fprintf(vvp_out, " %%mov %u, 2, %u; OUT OF BOUNDS\n", bit, wid); } } else if (ivl_signal_dimensions(sig) > 0 && word_ix != 0) { unsigned skip_set = transient_id++; unsigned out_set = transient_id++; slice->type = SLICE_MEMORY_WORD_DYNAMIC; draw_eval_expr_into_integer(word_ix, 3); slice->u_.memory_word_dynamic.word_idx_reg = allocate_word(); slice->u_.memory_word_dynamic.x_flag = allocate_vector(1); fprintf(vvp_out, " %%mov/wu %d, 3;\n", slice->u_.memory_word_dynamic.word_idx_reg); fprintf(vvp_out, " %%mov %u, 4, 1;\n", slice->u_.memory_word_dynamic.x_flag); fprintf(vvp_out, " %%jmp/1 t_%u, 4;\n", skip_set); fprintf(vvp_out, " %%ix/load 1, 0, 0;\n"); fprintf(vvp_out, " %%load/av %u, v%p, %u;\n", bit, sig, wid); fprintf(vvp_out, " %%jmp t_%u;\n", out_set); fprintf(vvp_out, "t_%u ;\n", skip_set); fprintf(vvp_out, " %%mov %u, 2, %u;\n", bit, wid); fprintf(vvp_out, "t_%u ;\n", out_set); } else { assert(0); } }
static void set_vec_to_lval_slice(ivl_lval_t lval, unsigned bit, unsigned wid) { ivl_signal_t sig = ivl_lval_sig(lval); ivl_expr_t part_off_ex = ivl_lval_part_off(lval); unsigned long part_off = 0; /* Although Verilog doesn't support it, we'll handle here the case of an l-value part select of an array word if the address is constant. */ ivl_expr_t word_ix = ivl_lval_idx(lval); unsigned long use_word = 0; if (part_off_ex == 0) { part_off = 0; } else if (number_is_immediate(part_off_ex, IMM_WID, 0) && !number_is_unknown(part_off_ex)) { part_off = get_number_immediate(part_off_ex); part_off_ex = 0; } /* If the word index is a constant expression, then evaluate it to select the word, and pay no further heed to the expression itself. Out-of-bounds and undefined indices are converted to a canonical index of 'bx during elaboration, and we don't try to optimise that case. */ if (word_ix && number_is_immediate(word_ix, IMM_WID, 0) && !number_is_unknown(word_ix)) { use_word = get_number_immediate(word_ix); assert(use_word < ivl_signal_array_count(sig)); word_ix = 0; } if (ivl_lval_mux(lval)) part_off_ex = ivl_lval_mux(lval); if (part_off_ex && ivl_signal_dimensions(sig) == 0) { unsigned skip_set = transient_id++; /* There is a mux expression, so this must be a write to a bit-select l-val. Presumably, the x0 index register has been loaded wit the result of the evaluated part select base expression. */ assert(!word_ix); draw_eval_expr_into_integer(part_off_ex, 0); fprintf(vvp_out, " %%jmp/1 t_%u, 4;\n", skip_set); fprintf(vvp_out, " %%set/x0 v%p_%lu, %u, %u;\n", sig, use_word, bit, wid); fprintf(vvp_out, "t_%u ;\n", skip_set); /* save_signal width of 0 CLEARS the signal from the lookaside. */ save_signal_lookaside(bit, sig, use_word, 0); } else if (part_off_ex && ivl_signal_dimensions(sig) > 0) { /* Here we have a part select write into an array word. */ unsigned skip_set = transient_id++; if (word_ix) { draw_eval_expr_into_integer(word_ix, 3); fprintf(vvp_out, " %%jmp/1 t_%u, 4;\n", skip_set); } else { fprintf(vvp_out, " %%ix/load 3, %lu, 0;\n", use_word); } draw_eval_expr_into_integer(part_off_ex, 1); fprintf(vvp_out, " %%jmp/1 t_%u, 4;\n", skip_set); fprintf(vvp_out, " %%set/av v%p, %u, %u;\n", sig, bit, wid); fprintf(vvp_out, "t_%u ;\n", skip_set); } else if ((part_off>0 || ivl_lval_width(lval)!=ivl_signal_width(sig)) && ivl_signal_dimensions(sig) > 0) { /* Here we have a part select write into an array word. */ unsigned skip_set = transient_id++; if (word_ix) { draw_eval_expr_into_integer(word_ix, 3); fprintf(vvp_out, " %%jmp/1 t_%u, 4;\n", skip_set); } else { fprintf(vvp_out, " %%ix/load 3, %lu, 0;\n", use_word); } fprintf(vvp_out, " %%ix/load 1, %lu, 0;\n", part_off); fprintf(vvp_out, " %%set/av v%p, %u, %u;\n", sig, bit, wid); if (word_ix) /* Only need this label if word_ix is set. */ fprintf(vvp_out, "t_%u ;\n", skip_set); } else if (part_off>0 || ivl_lval_width(lval)!=ivl_signal_width(sig)) { /* There is no mux expression, but a constant part offset. Load that into index x0 and generate a vector set instruction. */ assert(ivl_lval_width(lval) == wid); /* If the word index is a constant, then we can write directly to the word and save the index calculation. */ if (word_ix == 0) { fprintf(vvp_out, " %%ix/load 0, %lu, 0;\n", part_off); fprintf(vvp_out, " %%set/x0 v%p_%lu, %u, %u;\n", sig, use_word, bit, wid); } else { unsigned skip_set = transient_id++; unsigned index_reg = 3; draw_eval_expr_into_integer(word_ix, index_reg); fprintf(vvp_out, " %%jmp/1 t_%u, 4;\n", skip_set); fprintf(vvp_out, " %%ix/load 1, %lu, 0;\n", part_off); fprintf(vvp_out, " %%set/av v%p, %u, %u;\n", sig, bit, wid); fprintf(vvp_out, "t_%u ;\n", skip_set); } /* save_signal width of 0 CLEARS the signal from the lookaside. */ save_signal_lookaside(bit, sig, use_word, 0); } else if (ivl_signal_dimensions(sig) > 0) { /* If the word index is a constant, then we can write directly to the word and save the index calculation. */ if (word_ix == 0) { fprintf(vvp_out, " %%ix/load 1, 0, 0;\n"); fprintf(vvp_out, " %%ix/load 3, %lu, 0;\n", use_word); fprintf(vvp_out, " %%set/av v%p, %u, %u;\n", sig, bit, wid); } else { unsigned skip_set = transient_id++; unsigned index_reg = 3; draw_eval_expr_into_integer(word_ix, index_reg); fprintf(vvp_out, " %%jmp/1 t_%u, 4;\n", skip_set); fprintf(vvp_out, " %%ix/load 1, 0, 0;\n"); fprintf(vvp_out, " %%set/av v%p, %u, %u;\n", sig, bit, wid); fprintf(vvp_out, "t_%u ;\n", skip_set); } /* save_signal width of 0 CLEARS the signal from the lookaside. */ save_signal_lookaside(bit, sig, use_word, 0); } else { fprintf(vvp_out, " %%set/v v%p_%lu, %u, %u;\n", sig, use_word, bit, wid); /* save_signal width of 0 CLEARS the signal from the lookaside. */ save_signal_lookaside(bit, sig, use_word, 0); } }
static int show_stmt_assign_nb(ivl_statement_t net) { ivl_lval_t lval; ivl_expr_t rval = ivl_stmt_rval(net); ivl_expr_t del = ivl_stmt_delay_expr(net); ivl_memory_t mem; unsigned long delay = 0; /* Catch the case we are assigning to a real/word l-value. Handle that elsewhere. */ if (ivl_lval_var(ivl_stmt_lval(net, 0))) { return show_stmt_assign_nb_var(net); } if (del && (ivl_expr_type(del) == IVL_EX_ULONG)) { delay = ivl_expr_uvalue(del); del = 0; } /* Handle the special case that the r-value is a constant. We can generate the %set statement directly, without any worry about generating code to evaluate the r-value expressions. */ if (ivl_expr_type(rval) == IVL_EX_NUMBER) { unsigned lidx; const char*bits = ivl_expr_bits(rval); unsigned wid = ivl_expr_width(rval); unsigned cur_rbit = 0; if (del != 0) calculate_into_x1(del); for (lidx = 0 ; lidx < ivl_stmt_lvals(net) ; lidx += 1) { unsigned skip_set = transient_id++; unsigned skip_set_flag = 0; unsigned idx; unsigned bit_limit = wid - cur_rbit; lval = ivl_stmt_lval(net, lidx); /* If there is a mux for the lval, calculate the value and write it into index0. */ if (ivl_lval_mux(lval)) { calculate_into_x0(ivl_lval_mux(lval)); fprintf(vvp_out, " %%jmp/1 t_%u, 4;\n", skip_set); skip_set_flag = 1; } mem = ivl_lval_mem(lval); if (mem) { draw_memory_index_expr(mem, ivl_lval_idx(lval)); fprintf(vvp_out, " %%jmp/1 t_%u, 4;\n", skip_set); skip_set_flag = 1; } if (bit_limit > ivl_lval_pins(lval)) bit_limit = ivl_lval_pins(lval); if (mem) { for (idx = 0 ; idx < bit_limit ; idx += 1) { assign_to_memory(mem, idx, bitchar_to_idx(bits[cur_rbit]), delay); cur_rbit += 1; } for (idx = bit_limit ; idx < ivl_lval_pins(lval) ; idx += 1) { assign_to_memory(mem, idx, 0, delay); } } else if ((del == 0) && (bit_limit > 2)) { /* We have a vector, but no runtime calculated delays, to try to use vector assign instructions. */ idx = 0; while (idx < bit_limit) { unsigned wid = 0; do { wid += 1; if ((idx + wid) == bit_limit) break; } while (bits[cur_rbit] == bits[cur_rbit+wid]); switch (wid) { case 1: assign_to_lvariable(lval, idx, bitchar_to_idx(bits[cur_rbit]), delay, 0); break; case 2: assign_to_lvariable(lval, idx, bitchar_to_idx(bits[cur_rbit]), delay, 0); assign_to_lvariable(lval, idx+1, bitchar_to_idx(bits[cur_rbit]), delay, 0); break; default: assign_to_lvector(lval, idx, bitchar_to_idx(bits[cur_rbit]), delay, wid); break; } idx += wid; cur_rbit += wid; } if (bit_limit < ivl_lval_pins(lval)) { unsigned wid = ivl_lval_pins(lval) - bit_limit; assign_to_lvector(lval, bit_limit, 0, delay, wid); } } else { for (idx = 0 ; idx < bit_limit ; idx += 1) { if (del != 0) assign_to_lvariable(lval, idx, bitchar_to_idx(bits[cur_rbit]), 1, 1); else assign_to_lvariable(lval, idx, bitchar_to_idx(bits[cur_rbit]), delay, 0); cur_rbit += 1; } for (idx = bit_limit ; idx < ivl_lval_pins(lval) ; idx += 1) { if (del != 0) assign_to_lvariable(lval, idx, 0, 1, 1); else assign_to_lvariable(lval, idx, 0, delay, 0); } } if (skip_set_flag) { fprintf(vvp_out, "t_%u ;\n", skip_set); clear_expression_lookaside(); } } return 0; } { struct vector_info res = draw_eval_expr(rval, 0); unsigned wid = res.wid; unsigned lidx; unsigned cur_rbit = 0; if (del != 0) calculate_into_x1(del); for (lidx = 0 ; lidx < ivl_stmt_lvals(net) ; lidx += 1) { unsigned skip_set = transient_id++; unsigned skip_set_flag = 0; unsigned idx; unsigned bit_limit = wid - cur_rbit; lval = ivl_stmt_lval(net, lidx); /* If there is a mux for the lval, calculate the value and write it into index0. */ if (ivl_lval_mux(lval)) { calculate_into_x0(ivl_lval_mux(lval)); fprintf(vvp_out, " %%jmp/1 t_%u, 4;\n", skip_set); skip_set_flag = 1; } mem = ivl_lval_mem(lval); if (mem) { draw_memory_index_expr(mem, ivl_lval_idx(lval)); fprintf(vvp_out, " %%jmp/1 t_%u, 4;\n", skip_set); skip_set_flag = 1; } if (bit_limit > ivl_lval_pins(lval)) bit_limit = ivl_lval_pins(lval); if ((bit_limit > 2) && (mem == 0) && (del == 0)) { unsigned bidx = res.base < 4 ? res.base : (res.base+cur_rbit); assign_to_lvector(lval, 0, bidx, delay, bit_limit); cur_rbit += bit_limit; } else { for (idx = 0 ; idx < bit_limit ; idx += 1) { unsigned bidx = res.base < 4 ? res.base : (res.base+cur_rbit); if (mem) assign_to_memory(mem, idx, bidx, delay); else if (del != 0) assign_to_lvariable(lval, idx, bidx, 1, 1); else assign_to_lvariable(lval, idx, bidx, delay, 0); cur_rbit += 1; } } for (idx = bit_limit; idx < ivl_lval_pins(lval); idx += 1) if (mem) assign_to_memory(mem, idx, 0, delay); else if (del != 0) assign_to_lvariable(lval, idx, 0, 1, 1); else assign_to_lvariable(lval, idx, 0, delay, 0); if (skip_set_flag) { fprintf(vvp_out, "t_%u ;\n", skip_set); clear_expression_lookaside(); } } if (res.base > 3) clr_vector(res); } return 0; }
static int show_stmt_assign_vector(ivl_statement_t net) { ivl_lval_t lval; ivl_expr_t rval = ivl_stmt_rval(net); ivl_memory_t mem; /* Handle the special case that the expression is a real value. Evaluate the real expression, then convert the result to a vector. Then store that vector into the l-value. */ if (ivl_expr_value(rval) == IVL_VT_REAL) { int word = draw_eval_real(rval); /* This is the accumulated with of the l-value of the assignment. */ unsigned wid = ivl_stmt_lwidth(net); struct vector_info vec; vec.base = allocate_vector(wid); vec.wid = wid; fprintf(vvp_out, " %%cvt/vr %u, %d, %u;\n", vec.base, word, vec.wid); clr_word(word); set_vec_to_lval(net, vec); clr_vector(vec); return 0; } /* Handle the special case that the r-value is a constant. We can generate the %set statement directly, without any worry about generating code to evaluate the r-value expressions. */ if (ivl_expr_type(rval) == IVL_EX_NUMBER) { unsigned lidx; const char*bits = ivl_expr_bits(rval); unsigned wid = ivl_expr_width(rval); unsigned cur_rbit = 0; for (lidx = 0 ; lidx < ivl_stmt_lvals(net) ; lidx += 1) { unsigned skip_set = transient_id++; unsigned skip_set_flag = 0; unsigned idx; unsigned bit_limit = wid - cur_rbit; lval = ivl_stmt_lval(net, lidx); /* If there is a mux for the lval, calculate the value and write it into index0. */ if (ivl_lval_mux(lval)) { calculate_into_x0(ivl_lval_mux(lval)); /* Generate code to skip around the set if the index has X values. */ fprintf(vvp_out, " %%jmp/1 t_%u, 4;\n", skip_set); skip_set_flag = 1; } mem = ivl_lval_mem(lval); if (mem) { draw_memory_index_expr(mem, ivl_lval_idx(lval)); /* Generate code to skip around the set if the index has X values. */ fprintf(vvp_out, " %%jmp/1 t_%u, 4;\n", skip_set); skip_set_flag = 1; } if (bit_limit > ivl_lval_pins(lval)) bit_limit = ivl_lval_pins(lval); if (mem) { for (idx = 0 ; idx < bit_limit ; idx += 1) { set_to_memory(mem, idx, bitchar_to_idx(bits[cur_rbit])); cur_rbit += 1; } for (idx = bit_limit ; idx < ivl_lval_pins(lval) ; idx += 1) set_to_memory(mem, idx, 0); } else { idx = 0; while (idx < bit_limit) { unsigned cnt = 1; while (((idx + cnt) < bit_limit) && (bits[cur_rbit] == bits[cur_rbit+cnt])) cnt += 1; set_to_lvariable(lval, idx, bitchar_to_idx(bits[cur_rbit]), cnt); cur_rbit += cnt; idx += cnt; } if (bit_limit < ivl_lval_pins(lval)) { unsigned cnt = ivl_lval_pins(lval) - bit_limit; set_to_lvariable(lval, bit_limit, 0, cnt); } } if (skip_set_flag) { fprintf(vvp_out, "t_%u ;\n", skip_set); clear_expression_lookaside(); } } return 0; } { struct vector_info res = draw_eval_expr(rval, 0); set_vec_to_lval(net, res); if (res.base > 3) clr_vector(res); } return 0; }
/* * This is a private function to generate %set code for the * statement. At this point, the r-value is evaluated and stored in * the res vector, I just need to generate the %set statements for the * l-values of the assignment. */ static void set_vec_to_lval(ivl_statement_t net, struct vector_info res) { ivl_lval_t lval; ivl_memory_t mem; unsigned wid = res.wid; unsigned lidx; unsigned cur_rbit = 0; for (lidx = 0 ; lidx < ivl_stmt_lvals(net) ; lidx += 1) { unsigned skip_set = transient_id++; unsigned skip_set_flag = 0; unsigned idx; unsigned bit_limit = wid - cur_rbit; lval = ivl_stmt_lval(net, lidx); /* If there is a mux for the lval, calculate the value and write it into index0. */ if (ivl_lval_mux(lval)) { calculate_into_x0(ivl_lval_mux(lval)); fprintf(vvp_out, " %%jmp/1 t_%u, 4;\n", skip_set); skip_set_flag = 1; } mem = ivl_lval_mem(lval); if (mem) { draw_memory_index_expr(mem, ivl_lval_idx(lval)); fprintf(vvp_out, " %%jmp/1 t_%u, 4;\n", skip_set); skip_set_flag = 1; } if (bit_limit > ivl_lval_pins(lval)) bit_limit = ivl_lval_pins(lval); if (mem) { for (idx = 0 ; idx < bit_limit ; idx += 1) { unsigned bidx = res.base < 4 ? res.base : (res.base+cur_rbit); set_to_memory(mem, idx, bidx); cur_rbit += 1; } for (idx = bit_limit; idx < ivl_lval_pins(lval); idx += 1) set_to_memory(mem, idx, 0); } else { unsigned bidx = res.base < 4 ? res.base : (res.base+cur_rbit); set_to_lvariable(lval, 0, bidx, bit_limit); cur_rbit += bit_limit; if (bit_limit < ivl_lval_pins(lval)) { unsigned cnt = ivl_lval_pins(lval) - bit_limit; set_to_lvariable(lval, bit_limit, 0, cnt); } } if (skip_set_flag) { fprintf(vvp_out, "t_%u ;\n", skip_set); clear_expression_lookaside(); } } }