Esempio n. 1
0
static void show_root_ports_edif(ivl_scope_t root)
{
      char jbuf[1024];
      unsigned cnt = ivl_scope_sigs(root);
      unsigned idx;

      for (idx = 0 ;  idx < cnt ;  idx += 1) {
	    ivl_signal_t sig = ivl_scope_sig(root, idx);
	    const char*use_name;
	    const char*dir = 0;

	    if (ivl_signal_attr(sig, "PAD") != 0)
		  continue;

	    switch (ivl_signal_port(sig)) {
		case IVL_SIP_NONE:
		  continue;

		case IVL_SIP_INPUT:
		  dir = "INPUT";
		  break;

		case IVL_SIP_OUTPUT:
		  dir = "OUTPUT";
		  break;

		case IVL_SIP_INOUT:
		  dir = "INOUT";
		  break;
	    }

	    use_name = ivl_signal_basename(sig);
	    if (ivl_signal_pins(sig) == 1) {
		  fprintf(xnf, "            (port %s (direction %s))\n",
			  use_name, dir);

		  sprintf(jbuf, "(portRef %s)", use_name);
		  edif_set_nexus_joint(ivl_signal_pin(sig, 0), jbuf);

	    } else {
		  unsigned pin;

		  for (pin = 0 ; pin < ivl_signal_pins(sig); pin += 1) {
			fprintf(xnf, "            (port (rename %s_%u "
				"\"%s[%u]\") (direction %s))\n", use_name,
				pin, use_name, pin, dir);
			sprintf(jbuf, "(portRef %s_%u)", use_name, pin);
			edif_set_nexus_joint(ivl_signal_pin(sig, pin), jbuf);
		  }
	    }
      }
}
Esempio n. 2
0
File: pads.c Progetto: AmkG/iverilog
/*
 * This function scans the netlist for all the pin assignments that
 * are fixed by a PAD attribute. Search the scopes recursively,
 * looking for signals that may have PAD attributes.
 */
int get_pad_bindings(ivl_scope_t net, void*x)
{
      unsigned idx;

      int rc = ivl_scope_children(net, get_pad_bindings, 0);
      if (rc)
	    return rc;

      for (idx = 0 ;  idx < ivl_scope_sigs(net) ;  idx += 1) {

	    ivl_signal_t sig;
	    const char*pad;
	    int pin;

	    sig = ivl_scope_sig(net, idx);
	    pad = ivl_signal_attr(sig, "PAD");
	    if (pad == 0)
		  continue;

	    pin = strtol(pad+1, 0, 10);
	    if ((pin == 0) || (pin > pins)) {
		  printf("%s: Invalid PAD assignment: %s\n",
			 ivl_signal_name(sig), pad);
		  error_count += 1;
		  continue;
	    }

	    assert(ivl_signal_pins(sig) == 1);

	    if (bind_pin[pin-1].nexus) {

		  if (bind_pin[pin-1].nexus != ivl_signal_pin(sig, 0)) {

			printf("%s: Unconnected signals share pin %d\n",
			       ivl_signal_name(sig), pin);
			error_count += 1;
		  }

		  continue;
	    }

	    bind_pin[pin-1].nexus = ivl_signal_pin(sig, 0);
      }

      return 0;
}
Esempio n. 3
0
File: fpga.c Progetto: AmkG/iverilog
static void show_pads(ivl_scope_t scope)
{
      unsigned idx;

      if (device->show_pad == 0)
	    return;

      for (idx = 0 ;  idx < ivl_scope_sigs(scope) ;  idx += 1) {
	    ivl_signal_t sig = ivl_scope_sig(scope, idx);
	    const char*pad;

	    if (ivl_signal_port(sig) == IVL_SIP_NONE)
		  continue;

	    pad = ivl_signal_attr(sig, "PAD");
	    if (pad == 0)
		  continue;

	    assert(device->show_pad);
	    device->show_pad(sig, pad);
      }
}
Esempio n. 4
0
static void lpm_show_header(ivl_design_t des)
{
      unsigned idx;
      ivl_scope_t root = ivl_design_root(des);
      unsigned sig_cnt = ivl_scope_sigs(root);
      unsigned nports = 0, pidx;

	/* Count the ports I'm going to use. */
      for (idx = 0 ;  idx < sig_cnt ;  idx += 1) {
	    ivl_signal_t sig = ivl_scope_sig(root, idx);

	    if (ivl_signal_port(sig) == IVL_SIP_NONE)
		  continue;

	    if (ivl_signal_attr(sig, "PAD") != 0)
		  continue;

	    nports += ivl_signal_pins(sig);
      }

	/* Create the base edf object. */
      edf = edif_create(ivl_scope_basename(root), nports);


      pidx = 0;
      for (idx = 0 ;  idx < sig_cnt ;  idx += 1) {
	    edif_joint_t jnt;
	    ivl_signal_t sig = ivl_scope_sig(root, idx);

	    if (ivl_signal_port(sig) == IVL_SIP_NONE)
		  continue;

	    if (ivl_signal_attr(sig, "PAD") != 0)
		  continue;

	    if (ivl_signal_pins(sig) == 1) {
		  edif_portconfig(edf, pidx, ivl_signal_basename(sig),
				  ivl_signal_port(sig));

		  assert(ivl_signal_pins(sig) == 1);
		  jnt = edif_joint_of_nexus(edf, ivl_signal_pin(sig, 0));
		  edif_port_to_joint(jnt, edf, pidx);

	    } else {
		  const char*name = ivl_signal_basename(sig);
		  ivl_signal_port_t dir = ivl_signal_port(sig);
		  char buf[128];
		  unsigned bit;
		  for (bit = 0 ;  bit < ivl_signal_pins(sig) ; bit += 1) {
			const char*tmp;
			sprintf(buf, "%s[%u]", name, bit);
			tmp = strdup(buf);
			edif_portconfig(edf, pidx+bit, tmp, dir);

			jnt = edif_joint_of_nexus(edf,ivl_signal_pin(sig,bit));
			edif_port_to_joint(jnt, edf, pidx+bit);
		  }
	    }

	    pidx += ivl_signal_pins(sig);
      }

      assert(pidx == nports);

      xlib = edif_xlibrary_create(edf, "LPM_LIBRARY");
}