int main(void)
{
adc_core ad9625_core;
ad9625_setup(SPI_DEVICE_ID, 0);
jesd204b_setup(AD9625_JESD_BASEADDR, jesd204b_st);
jesd204b_gt_setup(gt_link);
jesd204b_gt_en_sync_sysref(gt_link);
ad9625_spi_write(0, AD9625_REG_TEST_CNTRL, 0x0F);
ad9625_spi_write(0, AD9625_REG_OUTPUT_MODE, 0x00);
ad9625_spi_write(0, AD9625_REG_TRANSFER, 0x01);
ad9625_core.adc_baseaddr = AD9625_CORE_BASEADDR;
ad9625_core.dmac_baseaddr = AD9625_DMA_BASEADDR;
ad9625_core.no_of_channels = 1;
ad9625_core.resolution = 12;
adc_setup(ad9625_core);
xil_printf("Start capturing data...\n\r");
adc_capture(ad9625_core, 16384, ADC_DDR_BASEADDR);
xil_printf("Done.\n\r");
return 0;
}
/***************************************************************************//**
* @brief main
*******************************************************************************/
int main(void)
{
jesd204b_gt_state jesd204b_gt_st;
jesd204b_state jesd204b_st;
daq2_gpio_ctl(GPIO_BASEADDR);
ad9523_setup(SPI_DEVICE_ID, 0, ad9523_pdata_lpc);
ad9144_setup(SPI_DEVICE_ID, 1, default_ad9144_init_param);
jesd204b_st.lanesync_enable = 1;
jesd204b_st.scramble_enable = 1;
jesd204b_st.sysref_always_enable = 0;
jesd204b_st.frames_per_multiframe = 32;
jesd204b_st.bytes_per_frame = 1;
jesd204b_st.subclass = 1;
jesd204b_setup(AD9144_JESD_BASEADDR, jesd204b_st);
ad9680_setup(SPI_DEVICE_ID, 2);
jesd204b_st.lanesync_enable = 1;
jesd204b_st.scramble_enable = 1;
jesd204b_st.sysref_always_enable = 0;
jesd204b_st.frames_per_multiframe = 32;
jesd204b_st.bytes_per_frame = 1;
jesd204b_st.subclass = 1;
jesd204b_setup(AD9680_JESD_BASEADDR, jesd204b_st);
jesd204b_gt_st.use_cpll = 0;
jesd204b_gt_st.rx_sys_clk_sel = 3;
jesd204b_gt_st.rx_out_clk_sel = 4;
jesd204b_gt_st.tx_sys_clk_sel = 3;
jesd204b_gt_st.tx_out_clk_sel = 4;
jesd204b_gt_setup(DAQ2_GT_BASEADDR, jesd204b_gt_st);
jesd204b_gt_clk_enable(JESD204B_GT_TX);
jesd204b_gt_clk_enable(JESD204B_GT_RX);
jesd204b_gt_clk_synchronize(JESD204B_GT_TX);
jesd204b_gt_clk_synchronize(JESD204B_GT_RX);
dac_setup(AD9144_CORE_BASEADDR);
dds_set_frequency(0, 5000000);
dds_set_phase(0, 0);
dds_set_scale(0, 500000);
dds_set_frequency(1, 5000000);
dds_set_phase(1, 0);
dds_set_scale(1, 500000);
dds_set_frequency(2, 5000000);
dds_set_phase(2, 90000);
dds_set_scale(2, 500000);
dds_set_frequency(3, 5000000);
dds_set_phase(3, 90000);
dds_set_scale(3, 500000);
adc_setup(AD9680_CORE_BASEADDR, AD9680_DMA_BASEADDR, 2);
xil_printf("Done.\n\r");
return 0;
}
