/* execute instructions on this CPU until icount expires */
static int hd6309_execute(int cycles) /* NS 970908 */
{
hd6309_ICount = cycles - hd6309.extra_cycles;
hd6309.extra_cycles = 0;
if (hd6309.int_state & (HD6309_CWAI | HD6309_SYNC))
{
CALL_MAME_DEBUG;
hd6309_ICount = 0;
}
else
{
do
{
pPPC = pPC;
CALL_MAME_DEBUG;
hd6309.ireg = ROP(PCD);
PC++;
#ifdef BIG_SWITCH
switch( hd6309.ireg )
{
case 0x00: neg_di(); break;
case 0x01: oim_di(); break;
case 0x02: aim_di(); break;
case 0x03: com_di(); break;
case 0x04: lsr_di(); break;
case 0x05: eim_di(); break;
case 0x06: ror_di(); break;
case 0x07: asr_di(); break;
case 0x08: asl_di(); break;
case 0x09: rol_di(); break;
case 0x0a: dec_di(); break;
case 0x0b: tim_di(); break;
case 0x0c: inc_di(); break;
case 0x0d: tst_di(); break;
case 0x0e: jmp_di(); break;
case 0x0f: clr_di(); break;
case 0x10: pref10(); break;
case 0x11: pref11(); break;
case 0x12: nop(); break;
case 0x13: sync(); break;
case 0x14: sexw(); break;
case 0x15: IIError(); break;
case 0x16: lbra(); break;
case 0x17: lbsr(); break;
case 0x18: IIError(); break;
case 0x19: daa(); break;
case 0x1a: orcc(); break;
case 0x1b: IIError(); break;
case 0x1c: andcc(); break;
case 0x1d: sex(); break;
case 0x1e: exg(); break;
case 0x1f: tfr(); break;
case 0x20: bra(); break;
case 0x21: brn(); break;
case 0x22: bhi(); break;
case 0x23: bls(); break;
case 0x24: bcc(); break;
case 0x25: bcs(); break;
case 0x26: bne(); break;
case 0x27: beq(); break;
case 0x28: bvc(); break;
case 0x29: bvs(); break;
case 0x2a: bpl(); break;
case 0x2b: bmi(); break;
case 0x2c: bge(); break;
case 0x2d: blt(); break;
case 0x2e: bgt(); break;
case 0x2f: ble(); break;
case 0x30: leax(); break;
case 0x31: leay(); break;
case 0x32: leas(); break;
case 0x33: leau(); break;
case 0x34: pshs(); break;
case 0x35: puls(); break;
case 0x36: pshu(); break;
case 0x37: pulu(); break;
case 0x38: IIError(); break;
case 0x39: rts(); break;
case 0x3a: abx(); break;
case 0x3b: rti(); break;
case 0x3c: cwai(); break;
case 0x3d: mul(); break;
case 0x3e: IIError(); break;
case 0x3f: swi(); break;
case 0x40: nega(); break;
case 0x41: IIError(); break;
case 0x42: IIError(); break;
case 0x43: coma(); break;
case 0x44: lsra(); break;
case 0x45: IIError(); break;
case 0x46: rora(); break;
case 0x47: asra(); break;
case 0x48: asla(); break;
case 0x49: rola(); break;
case 0x4a: deca(); break;
case 0x4b: IIError(); break;
case 0x4c: inca(); break;
case 0x4d: tsta(); break;
case 0x4e: IIError(); break;
case 0x4f: clra(); break;
case 0x50: negb(); break;
case 0x51: IIError(); break;
case 0x52: IIError(); break;
case 0x53: comb(); break;
case 0x54: lsrb(); break;
case 0x55: IIError(); break;
case 0x56: rorb(); break;
case 0x57: asrb(); break;
case 0x58: aslb(); break;
case 0x59: rolb(); break;
case 0x5a: decb(); break;
case 0x5b: IIError(); break;
case 0x5c: incb(); break;
case 0x5d: tstb(); break;
case 0x5e: IIError(); break;
case 0x5f: clrb(); break;
case 0x60: neg_ix(); break;
case 0x61: oim_ix(); break;
case 0x62: aim_ix(); break;
case 0x63: com_ix(); break;
case 0x64: lsr_ix(); break;
case 0x65: eim_ix(); break;
case 0x66: ror_ix(); break;
case 0x67: asr_ix(); break;
case 0x68: asl_ix(); break;
case 0x69: rol_ix(); break;
case 0x6a: dec_ix(); break;
case 0x6b: tim_ix(); break;
case 0x6c: inc_ix(); break;
case 0x6d: tst_ix(); break;
case 0x6e: jmp_ix(); break;
case 0x6f: clr_ix(); break;
case 0x70: neg_ex(); break;
case 0x71: oim_ex(); break;
case 0x72: aim_ex(); break;
case 0x73: com_ex(); break;
case 0x74: lsr_ex(); break;
case 0x75: eim_ex(); break;
case 0x76: ror_ex(); break;
case 0x77: asr_ex(); break;
case 0x78: asl_ex(); break;
case 0x79: rol_ex(); break;
case 0x7a: dec_ex(); break;
case 0x7b: tim_ex(); break;
case 0x7c: inc_ex(); break;
case 0x7d: tst_ex(); break;
case 0x7e: jmp_ex(); break;
case 0x7f: clr_ex(); break;
case 0x80: suba_im(); break;
case 0x81: cmpa_im(); break;
case 0x82: sbca_im(); break;
case 0x83: subd_im(); break;
case 0x84: anda_im(); break;
case 0x85: bita_im(); break;
case 0x86: lda_im(); break;
case 0x87: IIError(); break;
case 0x88: eora_im(); break;
case 0x89: adca_im(); break;
case 0x8a: ora_im(); break;
case 0x8b: adda_im(); break;
case 0x8c: cmpx_im(); break;
case 0x8d: bsr(); break;
case 0x8e: ldx_im(); break;
case 0x8f: IIError(); break;
case 0x90: suba_di(); break;
case 0x91: cmpa_di(); break;
case 0x92: sbca_di(); break;
case 0x93: subd_di(); break;
case 0x94: anda_di(); break;
case 0x95: bita_di(); break;
case 0x96: lda_di(); break;
case 0x97: sta_di(); break;
case 0x98: eora_di(); break;
case 0x99: adca_di(); break;
case 0x9a: ora_di(); break;
case 0x9b: adda_di(); break;
case 0x9c: cmpx_di(); break;
case 0x9d: jsr_di(); break;
case 0x9e: ldx_di(); break;
case 0x9f: stx_di(); break;
case 0xa0: suba_ix(); break;
case 0xa1: cmpa_ix(); break;
case 0xa2: sbca_ix(); break;
case 0xa3: subd_ix(); break;
case 0xa4: anda_ix(); break;
case 0xa5: bita_ix(); break;
case 0xa6: lda_ix(); break;
case 0xa7: sta_ix(); break;
case 0xa8: eora_ix(); break;
case 0xa9: adca_ix(); break;
case 0xaa: ora_ix(); break;
case 0xab: adda_ix(); break;
case 0xac: cmpx_ix(); break;
case 0xad: jsr_ix(); break;
case 0xae: ldx_ix(); break;
case 0xaf: stx_ix(); break;
case 0xb0: suba_ex(); break;
case 0xb1: cmpa_ex(); break;
case 0xb2: sbca_ex(); break;
case 0xb3: subd_ex(); break;
case 0xb4: anda_ex(); break;
case 0xb5: bita_ex(); break;
case 0xb6: lda_ex(); break;
case 0xb7: sta_ex(); break;
case 0xb8: eora_ex(); break;
case 0xb9: adca_ex(); break;
case 0xba: ora_ex(); break;
case 0xbb: adda_ex(); break;
case 0xbc: cmpx_ex(); break;
case 0xbd: jsr_ex(); break;
case 0xbe: ldx_ex(); break;
case 0xbf: stx_ex(); break;
case 0xc0: subb_im(); break;
case 0xc1: cmpb_im(); break;
case 0xc2: sbcb_im(); break;
case 0xc3: addd_im(); break;
case 0xc4: andb_im(); break;
case 0xc5: bitb_im(); break;
case 0xc6: ldb_im(); break;
case 0xc7: IIError(); break;
case 0xc8: eorb_im(); break;
case 0xc9: adcb_im(); break;
case 0xca: orb_im(); break;
case 0xcb: addb_im(); break;
case 0xcc: ldd_im(); break;
case 0xcd: ldq_im(); break; /* in m6809 was std_im */
case 0xce: ldu_im(); break;
case 0xcf: IIError(); break;
case 0xd0: subb_di(); break;
case 0xd1: cmpb_di(); break;
case 0xd2: sbcb_di(); break;
case 0xd3: addd_di(); break;
case 0xd4: andb_di(); break;
case 0xd5: bitb_di(); break;
case 0xd6: ldb_di(); break;
case 0xd7: stb_di(); break;
case 0xd8: eorb_di(); break;
case 0xd9: adcb_di(); break;
case 0xda: orb_di(); break;
case 0xdb: addb_di(); break;
case 0xdc: ldd_di(); break;
case 0xdd: std_di(); break;
case 0xde: ldu_di(); break;
case 0xdf: stu_di(); break;
case 0xe0: subb_ix(); break;
case 0xe1: cmpb_ix(); break;
case 0xe2: sbcb_ix(); break;
case 0xe3: addd_ix(); break;
case 0xe4: andb_ix(); break;
case 0xe5: bitb_ix(); break;
case 0xe6: ldb_ix(); break;
case 0xe7: stb_ix(); break;
case 0xe8: eorb_ix(); break;
case 0xe9: adcb_ix(); break;
case 0xea: orb_ix(); break;
case 0xeb: addb_ix(); break;
case 0xec: ldd_ix(); break;
case 0xed: std_ix(); break;
case 0xee: ldu_ix(); break;
case 0xef: stu_ix(); break;
case 0xf0: subb_ex(); break;
case 0xf1: cmpb_ex(); break;
case 0xf2: sbcb_ex(); break;
case 0xf3: addd_ex(); break;
case 0xf4: andb_ex(); break;
case 0xf5: bitb_ex(); break;
case 0xf6: ldb_ex(); break;
case 0xf7: stb_ex(); break;
case 0xf8: eorb_ex(); break;
case 0xf9: adcb_ex(); break;
case 0xfa: orb_ex(); break;
case 0xfb: addb_ex(); break;
case 0xfc: ldd_ex(); break;
case 0xfd: std_ex(); break;
case 0xfe: ldu_ex(); break;
case 0xff: stu_ex(); break;
}
#else
(*hd6309_main[hd6309.ireg])();
#endif /* BIG_SWITCH */
hd6309_ICount -= cycle_counts_page0[hd6309.ireg];
} while( hd6309_ICount > 0 );
hd6309_ICount -= hd6309.extra_cycles;
hd6309.extra_cycles = 0;
}
return cycles - hd6309_ICount; /* NS 970908 */
}
/* Generate interrupts */
static void Interrupt(void)
{
/* the 6805 latches interrupt requests internally, so we don't clear */
/* pending_interrupts until the interrupt is taken, no matter what the */
/* external IRQ pin does. */
#if (1) //HAS_HD63705)
if( (m6805.pending_interrupts & (1<<HD63705_INT_NMI)) != 0)
{
PUSHWORD(m6805.pc);
PUSHBYTE(m6805.x);
PUSHBYTE(m6805.a);
PUSHBYTE(m6805.cc);
SEI;
/* no vectors supported, just do the callback to clear irq_state if needed */
if (m6805.irq_callback)
(*m6805.irq_callback)(0);
RM16( 0x1ffc, &pPC);
change_pc(PC);
m6805.pending_interrupts &= ~(1<<HD63705_INT_NMI);
m6805_ICount -= 11;
}
else if( (m6805.pending_interrupts & ((1<<M6805_IRQ_LINE)|HD63705_INT_MASK)) != 0 ) {
if ( (CC & IFLAG) == 0 ) {
#else
if( (m6805.pending_interrupts & (1<<M6805_IRQ_LINE)) != 0 ) {
if ( (CC & IFLAG) == 0 ) {
#endif
{
/* standard IRQ */
//#if (HAS_HD63705)
// if(SUBTYPE!=SUBTYPE_HD63705)
//#endif
// PC |= ~AMASK;
PUSHWORD(m6805.pc);
PUSHBYTE(m6805.x);
PUSHBYTE(m6805.a);
PUSHBYTE(m6805.cc);
SEI;
/* no vectors supported, just do the callback to clear irq_state if needed */
if (m6805.irq_callback)
(*m6805.irq_callback)(0);
//#if (HAS_HD63705)
if(SUBTYPE==SUBTYPE_HD63705)
{
/* Need to add emulation of other interrupt sources here KW-2/4/99 */
/* This is just a quick patch for Namco System 2 operation */
if((m6805.pending_interrupts&(1<<HD63705_INT_IRQ1))!=0)
{
m6805.pending_interrupts &= ~(1<<HD63705_INT_IRQ1);
RM16( 0x1ff8, &pPC);
change_pc(PC);
}
else if((m6805.pending_interrupts&(1<<HD63705_INT_IRQ2))!=0)
{
m6805.pending_interrupts &= ~(1<<HD63705_INT_IRQ2);
RM16( 0x1fec, &pPC);
change_pc(PC);
}
else if((m6805.pending_interrupts&(1<<HD63705_INT_ADCONV))!=0)
{
m6805.pending_interrupts &= ~(1<<HD63705_INT_ADCONV);
RM16( 0x1fea, &pPC);
change_pc(PC);
}
else if((m6805.pending_interrupts&(1<<HD63705_INT_TIMER1))!=0)
{
m6805.pending_interrupts &= ~(1<<HD63705_INT_TIMER1);
RM16( 0x1ff6, &pPC);
change_pc(PC);
}
else if((m6805.pending_interrupts&(1<<HD63705_INT_TIMER2))!=0)
{
m6805.pending_interrupts &= ~(1<<HD63705_INT_TIMER2);
RM16( 0x1ff4, &pPC);
change_pc(PC);
}
else if((m6805.pending_interrupts&(1<<HD63705_INT_TIMER3))!=0)
{
m6805.pending_interrupts &= ~(1<<HD63705_INT_TIMER3);
RM16( 0x1ff2, &pPC);
change_pc(PC);
}
else if((m6805.pending_interrupts&(1<<HD63705_INT_PCI))!=0)
{
m6805.pending_interrupts &= ~(1<<HD63705_INT_PCI);
RM16( 0x1ff0, &pPC);
change_pc(PC);
}
else if((m6805.pending_interrupts&(1<<HD63705_INT_SCI))!=0)
{
m6805.pending_interrupts &= ~(1<<HD63705_INT_SCI);
RM16( 0x1fee, &pPC);
change_pc(PC);
}
}
else
//#endif
{
RM16( 0xffff - 5, &pPC );
change_pc(PC);
}
} // CC & IFLAG
m6805.pending_interrupts &= ~(1<<M6805_IRQ_LINE);
}
m6805_ICount -= 11;
}
}
static void m6805_reset()
{
int (*save_irqcallback)(int) = m6805.irq_callback;
memset(&m6805, 0, sizeof(m6805));
m6805.irq_callback = save_irqcallback;
/* Force CPU sub-type and relevant masks */
m6805.subtype = SUBTYPE_M6805;
SP_MASK = 0x07f;
SP_LOW = 0x060;
/* Initial stack pointer */
S = SP_MASK;
/* IRQ disabled */
SEI;
RM16( 0xfffe , &pPC );
change_pc(PC);
}
void m6805Reset() {
m6805_reset();
}
//static void m6805_init(int ) //int (*irqcallback)(int))
//{
// m6805.irq_callback = irqcallback;
//}
//static void m6805_exit(void)
//{
// /* nothing to do */
//}
void m6805SetIrqLine(int , int state)
{
/* Basic 6805 only has one IRQ line */
/* See HD63705 specific version */
if (m6805.irq_state[0] == state) return;
m6805.irq_state[0] = state;
if (state != CLEAR_LINE)
m6805.pending_interrupts |= 1<<M6805_IRQ_LINE;
}
#include "6805ops.c"
/* execute instructions on this CPU until icount expires */
int m6805Run(int cycles)
{
UINT8 ireg;
m6805_ICount = cycles;
do
{
if (m6805.pending_interrupts != 0)
{
if (SUBTYPE==SUBTYPE_M68705)
{
m68705_Interrupt();
}
else
{
Interrupt();
}
}
ireg=M_RDOP(PC++);
switch( ireg )
{
case 0x00: brset(0x01); break;
case 0x01: brclr(0x01); break;
case 0x02: brset(0x02); break;
case 0x03: brclr(0x02); break;
case 0x04: brset(0x04); break;
case 0x05: brclr(0x04); break;
case 0x06: brset(0x08); break;
case 0x07: brclr(0x08); break;
case 0x08: brset(0x10); break;
case 0x09: brclr(0x10); break;
case 0x0A: brset(0x20); break;
case 0x0B: brclr(0x20); break;
case 0x0C: brset(0x40); break;
case 0x0D: brclr(0x40); break;
case 0x0E: brset(0x80); break;
case 0x0F: brclr(0x80); break;
case 0x10: bset(0x01); break;
case 0x11: bclr(0x01); break;
case 0x12: bset(0x02); break;
case 0x13: bclr(0x02); break;
case 0x14: bset(0x04); break;
case 0x15: bclr(0x04); break;
case 0x16: bset(0x08); break;
case 0x17: bclr(0x08); break;
case 0x18: bset(0x10); break;
case 0x19: bclr(0x10); break;
case 0x1a: bset(0x20); break;
case 0x1b: bclr(0x20); break;
case 0x1c: bset(0x40); break;
case 0x1d: bclr(0x40); break;
case 0x1e: bset(0x80); break;
case 0x1f: bclr(0x80); break;
case 0x20: bra(); break;
case 0x21: brn(); break;
case 0x22: bhi(); break;
case 0x23: bls(); break;
case 0x24: bcc(); break;
case 0x25: bcs(); break;
case 0x26: bne(); break;
case 0x27: beq(); break;
case 0x28: bhcc(); break;
case 0x29: bhcs(); break;
case 0x2a: bpl(); break;
case 0x2b: bmi(); break;
case 0x2c: bmc(); break;
case 0x2d: bms(); break;
case 0x2e: bil(); break;
case 0x2f: bih(); break;
case 0x30: neg_di(); break;
case 0x31: illegal(); break;
case 0x32: illegal(); break;
case 0x33: com_di(); break;
case 0x34: lsr_di(); break;
case 0x35: illegal(); break;
case 0x36: ror_di(); break;
case 0x37: asr_di(); break;
case 0x38: lsl_di(); break;
case 0x39: rol_di(); break;
case 0x3a: dec_di(); break;
case 0x3b: illegal(); break;
case 0x3c: inc_di(); break;
case 0x3d: tst_di(); break;
case 0x3e: illegal(); break;
case 0x3f: clr_di(); break;
case 0x40: nega(); break;
case 0x41: illegal(); break;
case 0x42: illegal(); break;
case 0x43: coma(); break;
case 0x44: lsra(); break;
case 0x45: illegal(); break;
case 0x46: rora(); break;
case 0x47: asra(); break;
case 0x48: lsla(); break;
case 0x49: rola(); break;
case 0x4a: deca(); break;
case 0x4b: illegal(); break;
case 0x4c: inca(); break;
case 0x4d: tsta(); break;
case 0x4e: illegal(); break;
case 0x4f: clra(); break;
case 0x50: negx(); break;
case 0x51: illegal(); break;
case 0x52: illegal(); break;
case 0x53: comx(); break;
case 0x54: lsrx(); break;
case 0x55: illegal(); break;
case 0x56: rorx(); break;
case 0x57: asrx(); break;
case 0x58: aslx(); break;
case 0x59: rolx(); break;
case 0x5a: decx(); break;
case 0x5b: illegal(); break;
case 0x5c: incx(); break;
case 0x5d: tstx(); break;
case 0x5e: illegal(); break;
case 0x5f: clrx(); break;
case 0x60: neg_ix1(); break;
case 0x61: illegal(); break;
case 0x62: illegal(); break;
case 0x63: com_ix1(); break;
case 0x64: lsr_ix1(); break;
case 0x65: illegal(); break;
case 0x66: ror_ix1(); break;
case 0x67: asr_ix1(); break;
case 0x68: lsl_ix1(); break;
case 0x69: rol_ix1(); break;
case 0x6a: dec_ix1(); break;
case 0x6b: illegal(); break;
case 0x6c: inc_ix1(); break;
case 0x6d: tst_ix1(); break;
case 0x6e: illegal(); break;
case 0x6f: clr_ix1(); break;
case 0x70: neg_ix(); break;
case 0x71: illegal(); break;
case 0x72: illegal(); break;
case 0x73: com_ix(); break;
case 0x74: lsr_ix(); break;
case 0x75: illegal(); break;
case 0x76: ror_ix(); break;
case 0x77: asr_ix(); break;
case 0x78: lsl_ix(); break;
case 0x79: rol_ix(); break;
case 0x7a: dec_ix(); break;
case 0x7b: illegal(); break;
case 0x7c: inc_ix(); break;
case 0x7d: tst_ix(); break;
case 0x7e: illegal(); break;
case 0x7f: clr_ix(); break;
case 0x80: rti(); break;
case 0x81: rts(); break;
case 0x82: illegal(); break;
case 0x83: swi(); break;
case 0x84: illegal(); break;
case 0x85: illegal(); break;
case 0x86: illegal(); break;
case 0x87: illegal(); break;
case 0x88: illegal(); break;
case 0x89: illegal(); break;
case 0x8a: illegal(); break;
case 0x8b: illegal(); break;
case 0x8c: illegal(); break;
case 0x8d: illegal(); break;
case 0x8e: illegal(); break;
case 0x8f: illegal(); break;
case 0x90: illegal(); break;
case 0x91: illegal(); break;
case 0x92: illegal(); break;
case 0x93: illegal(); break;
case 0x94: illegal(); break;
case 0x95: illegal(); break;
case 0x96: illegal(); break;
case 0x97: tax(); break;
case 0x98: CLC; break;
case 0x99: SEC; break;
#if IRQ_LEVEL_DETECT
case 0x9a: CLI; if (m6805.irq_state != CLEAR_LINE) m6805.pending_interrupts |= 1<<M6805_IRQ_LINE; break;
#else
case 0x9a: CLI; break;
#endif
case 0x9b: SEI; break;
case 0x9c: rsp(); break;
case 0x9d: nop(); break;
case 0x9e: illegal(); break;
case 0x9f: txa(); break;
case 0xa0: suba_im(); break;
case 0xa1: cmpa_im(); break;
case 0xa2: sbca_im(); break;
case 0xa3: cpx_im(); break;
case 0xa4: anda_im(); break;
case 0xa5: bita_im(); break;
case 0xa6: lda_im(); break;
case 0xa7: illegal(); break;
case 0xa8: eora_im(); break;
case 0xa9: adca_im(); break;
case 0xaa: ora_im(); break;
case 0xab: adda_im(); break;
case 0xac: illegal(); break;
case 0xad: bsr(); break;
case 0xae: ldx_im(); break;
case 0xaf: illegal(); break;
case 0xb0: suba_di(); break;
case 0xb1: cmpa_di(); break;
case 0xb2: sbca_di(); break;
case 0xb3: cpx_di(); break;
case 0xb4: anda_di(); break;
case 0xb5: bita_di(); break;
case 0xb6: lda_di(); break;
case 0xb7: sta_di(); break;
case 0xb8: eora_di(); break;
case 0xb9: adca_di(); break;
case 0xba: ora_di(); break;
case 0xbb: adda_di(); break;
case 0xbc: jmp_di(); break;
case 0xbd: jsr_di(); break;
case 0xbe: ldx_di(); break;
case 0xbf: stx_di(); break;
case 0xc0: suba_ex(); break;
case 0xc1: cmpa_ex(); break;
case 0xc2: sbca_ex(); break;
case 0xc3: cpx_ex(); break;
case 0xc4: anda_ex(); break;
case 0xc5: bita_ex(); break;
case 0xc6: lda_ex(); break;
case 0xc7: sta_ex(); break;
case 0xc8: eora_ex(); break;
case 0xc9: adca_ex(); break;
case 0xca: ora_ex(); break;
case 0xcb: adda_ex(); break;
case 0xcc: jmp_ex(); break;
case 0xcd: jsr_ex(); break;
case 0xce: ldx_ex(); break;
case 0xcf: stx_ex(); break;
case 0xd0: suba_ix2(); break;
case 0xd1: cmpa_ix2(); break;
case 0xd2: sbca_ix2(); break;
case 0xd3: cpx_ix2(); break;
case 0xd4: anda_ix2(); break;
case 0xd5: bita_ix2(); break;
case 0xd6: lda_ix2(); break;
case 0xd7: sta_ix2(); break;
case 0xd8: eora_ix2(); break;
case 0xd9: adca_ix2(); break;
case 0xda: ora_ix2(); break;
case 0xdb: adda_ix2(); break;
case 0xdc: jmp_ix2(); break;
case 0xdd: jsr_ix2(); break;
case 0xde: ldx_ix2(); break;
case 0xdf: stx_ix2(); break;
case 0xe0: suba_ix1(); break;
case 0xe1: cmpa_ix1(); break;
case 0xe2: sbca_ix1(); break;
case 0xe3: cpx_ix1(); break;
case 0xe4: anda_ix1(); break;
case 0xe5: bita_ix1(); break;
case 0xe6: lda_ix1(); break;
case 0xe7: sta_ix1(); break;
case 0xe8: eora_ix1(); break;
case 0xe9: adca_ix1(); break;
case 0xea: ora_ix1(); break;
case 0xeb: adda_ix1(); break;
case 0xec: jmp_ix1(); break;
case 0xed: jsr_ix1(); break;
case 0xee: ldx_ix1(); break;
case 0xef: stx_ix1(); break;
case 0xf0: suba_ix(); break;
case 0xf1: cmpa_ix(); break;
case 0xf2: sbca_ix(); break;
case 0xf3: cpx_ix(); break;
case 0xf4: anda_ix(); break;
case 0xf5: bita_ix(); break;
case 0xf6: lda_ix(); break;
case 0xf7: sta_ix(); break;
case 0xf8: eora_ix(); break;
case 0xf9: adca_ix(); break;
case 0xfa: ora_ix(); break;
case 0xfb: adda_ix(); break;
case 0xfc: jmp_ix(); break;
case 0xfd: jsr_ix(); break;
case 0xfe: ldx_ix(); break;
case 0xff: stx_ix(); break;
}
m6805_ICount -= cycles1[ireg];
m6805.nTotalCycles += cycles1[ireg];
} while( m6805_ICount > 0 );
return cycles - m6805_ICount;
}
/* execute instructions on this CPU until icount expires */
void m6805_base_device::execute_run()
{
UINT8 ireg;
S = SP_ADJUST( S ); /* Taken from CPU_SET_CONTEXT when pointer'afying */
do
{
if (m_pending_interrupts != 0)
{
interrupt();
}
debugger_instruction_hook(this, PC);
ireg=M_RDOP(PC++);
switch( ireg )
{
case 0x00: brset(0x01); break;
case 0x01: brclr(0x01); break;
case 0x02: brset(0x02); break;
case 0x03: brclr(0x02); break;
case 0x04: brset(0x04); break;
case 0x05: brclr(0x04); break;
case 0x06: brset(0x08); break;
case 0x07: brclr(0x08); break;
case 0x08: brset(0x10); break;
case 0x09: brclr(0x10); break;
case 0x0A: brset(0x20); break;
case 0x0B: brclr(0x20); break;
case 0x0C: brset(0x40); break;
case 0x0D: brclr(0x40); break;
case 0x0E: brset(0x80); break;
case 0x0F: brclr(0x80); break;
case 0x10: bset(0x01); break;
case 0x11: bclr(0x01); break;
case 0x12: bset(0x02); break;
case 0x13: bclr(0x02); break;
case 0x14: bset(0x04); break;
case 0x15: bclr(0x04); break;
case 0x16: bset(0x08); break;
case 0x17: bclr(0x08); break;
case 0x18: bset(0x10); break;
case 0x19: bclr(0x10); break;
case 0x1a: bset(0x20); break;
case 0x1b: bclr(0x20); break;
case 0x1c: bset(0x40); break;
case 0x1d: bclr(0x40); break;
case 0x1e: bset(0x80); break;
case 0x1f: bclr(0x80); break;
case 0x20: bra(); break;
case 0x21: brn(); break;
case 0x22: bhi(); break;
case 0x23: bls(); break;
case 0x24: bcc(); break;
case 0x25: bcs(); break;
case 0x26: bne(); break;
case 0x27: beq(); break;
case 0x28: bhcc(); break;
case 0x29: bhcs(); break;
case 0x2a: bpl(); break;
case 0x2b: bmi(); break;
case 0x2c: bmc(); break;
case 0x2d: bms(); break;
case 0x2e: bil(); break;
case 0x2f: bih(); break;
case 0x30: neg_di(); break;
case 0x31: illegal(); break;
case 0x32: illegal(); break;
case 0x33: com_di(); break;
case 0x34: lsr_di(); break;
case 0x35: illegal(); break;
case 0x36: ror_di(); break;
case 0x37: asr_di(); break;
case 0x38: lsl_di(); break;
case 0x39: rol_di(); break;
case 0x3a: dec_di(); break;
case 0x3b: illegal(); break;
case 0x3c: inc_di(); break;
case 0x3d: tst_di(); break;
case 0x3e: illegal(); break;
case 0x3f: clr_di(); break;
case 0x40: nega(); break;
case 0x41: illegal(); break;
case 0x42: illegal(); break;
case 0x43: coma(); break;
case 0x44: lsra(); break;
case 0x45: illegal(); break;
case 0x46: rora(); break;
case 0x47: asra(); break;
case 0x48: lsla(); break;
case 0x49: rola(); break;
case 0x4a: deca(); break;
case 0x4b: illegal(); break;
case 0x4c: inca(); break;
case 0x4d: tsta(); break;
case 0x4e: illegal(); break;
case 0x4f: clra(); break;
case 0x50: negx(); break;
case 0x51: illegal(); break;
case 0x52: illegal(); break;
case 0x53: comx(); break;
case 0x54: lsrx(); break;
case 0x55: illegal(); break;
case 0x56: rorx(); break;
case 0x57: asrx(); break;
case 0x58: aslx(); break;
case 0x59: rolx(); break;
case 0x5a: decx(); break;
case 0x5b: illegal(); break;
case 0x5c: incx(); break;
case 0x5d: tstx(); break;
case 0x5e: illegal(); break;
case 0x5f: clrx(); break;
case 0x60: neg_ix1(); break;
case 0x61: illegal(); break;
case 0x62: illegal(); break;
case 0x63: com_ix1(); break;
case 0x64: lsr_ix1(); break;
case 0x65: illegal(); break;
case 0x66: ror_ix1(); break;
case 0x67: asr_ix1(); break;
case 0x68: lsl_ix1(); break;
case 0x69: rol_ix1(); break;
case 0x6a: dec_ix1(); break;
case 0x6b: illegal(); break;
case 0x6c: inc_ix1(); break;
case 0x6d: tst_ix1(); break;
case 0x6e: illegal(); break;
case 0x6f: clr_ix1(); break;
case 0x70: neg_ix(); break;
case 0x71: illegal(); break;
case 0x72: illegal(); break;
case 0x73: com_ix(); break;
case 0x74: lsr_ix(); break;
case 0x75: illegal(); break;
case 0x76: ror_ix(); break;
case 0x77: asr_ix(); break;
case 0x78: lsl_ix(); break;
case 0x79: rol_ix(); break;
case 0x7a: dec_ix(); break;
case 0x7b: illegal(); break;
case 0x7c: inc_ix(); break;
case 0x7d: tst_ix(); break;
case 0x7e: illegal(); break;
case 0x7f: clr_ix(); break;
case 0x80: rti(); break;
case 0x81: rts(); break;
case 0x82: illegal(); break;
case 0x83: swi(); break;
case 0x84: illegal(); break;
case 0x85: illegal(); break;
case 0x86: illegal(); break;
case 0x87: illegal(); break;
case 0x88: illegal(); break;
case 0x89: illegal(); break;
case 0x8a: illegal(); break;
case 0x8b: illegal(); break;
case 0x8c: illegal(); break;
case 0x8d: illegal(); break;
case 0x8e: illegal(); break;
case 0x8f: illegal(); break;
case 0x90: illegal(); break;
case 0x91: illegal(); break;
case 0x92: illegal(); break;
case 0x93: illegal(); break;
case 0x94: illegal(); break;
case 0x95: illegal(); break;
case 0x96: illegal(); break;
case 0x97: tax(); break;
case 0x98: CLC; break;
case 0x99: SEC; break;
#if IRQ_LEVEL_DETECT
case 0x9a: CLI; if (m_irq_state != CLEAR_LINE) m_pending_interrupts |= 1 << M6805_IRQ_LINE; break;
#else
case 0x9a: CLI; break;
#endif
case 0x9b: SEI; break;
case 0x9c: rsp(); break;
case 0x9d: nop(); break;
case 0x9e: illegal(); break;
case 0x9f: txa(); break;
case 0xa0: suba_im(); break;
case 0xa1: cmpa_im(); break;
case 0xa2: sbca_im(); break;
case 0xa3: cpx_im(); break;
case 0xa4: anda_im(); break;
case 0xa5: bita_im(); break;
case 0xa6: lda_im(); break;
case 0xa7: illegal(); break;
case 0xa8: eora_im(); break;
case 0xa9: adca_im(); break;
case 0xaa: ora_im(); break;
case 0xab: adda_im(); break;
case 0xac: illegal(); break;
case 0xad: bsr(); break;
case 0xae: ldx_im(); break;
case 0xaf: illegal(); break;
case 0xb0: suba_di(); break;
case 0xb1: cmpa_di(); break;
case 0xb2: sbca_di(); break;
case 0xb3: cpx_di(); break;
case 0xb4: anda_di(); break;
case 0xb5: bita_di(); break;
case 0xb6: lda_di(); break;
case 0xb7: sta_di(); break;
case 0xb8: eora_di(); break;
case 0xb9: adca_di(); break;
case 0xba: ora_di(); break;
case 0xbb: adda_di(); break;
case 0xbc: jmp_di(); break;
case 0xbd: jsr_di(); break;
case 0xbe: ldx_di(); break;
case 0xbf: stx_di(); break;
case 0xc0: suba_ex(); break;
case 0xc1: cmpa_ex(); break;
case 0xc2: sbca_ex(); break;
case 0xc3: cpx_ex(); break;
case 0xc4: anda_ex(); break;
case 0xc5: bita_ex(); break;
case 0xc6: lda_ex(); break;
case 0xc7: sta_ex(); break;
case 0xc8: eora_ex(); break;
case 0xc9: adca_ex(); break;
case 0xca: ora_ex(); break;
case 0xcb: adda_ex(); break;
case 0xcc: jmp_ex(); break;
case 0xcd: jsr_ex(); break;
case 0xce: ldx_ex(); break;
case 0xcf: stx_ex(); break;
case 0xd0: suba_ix2(); break;
case 0xd1: cmpa_ix2(); break;
case 0xd2: sbca_ix2(); break;
case 0xd3: cpx_ix2(); break;
case 0xd4: anda_ix2(); break;
case 0xd5: bita_ix2(); break;
case 0xd6: lda_ix2(); break;
case 0xd7: sta_ix2(); break;
case 0xd8: eora_ix2(); break;
case 0xd9: adca_ix2(); break;
case 0xda: ora_ix2(); break;
case 0xdb: adda_ix2(); break;
case 0xdc: jmp_ix2(); break;
case 0xdd: jsr_ix2(); break;
case 0xde: ldx_ix2(); break;
case 0xdf: stx_ix2(); break;
case 0xe0: suba_ix1(); break;
case 0xe1: cmpa_ix1(); break;
case 0xe2: sbca_ix1(); break;
case 0xe3: cpx_ix1(); break;
case 0xe4: anda_ix1(); break;
case 0xe5: bita_ix1(); break;
case 0xe6: lda_ix1(); break;
case 0xe7: sta_ix1(); break;
case 0xe8: eora_ix1(); break;
case 0xe9: adca_ix1(); break;
case 0xea: ora_ix1(); break;
case 0xeb: adda_ix1(); break;
case 0xec: jmp_ix1(); break;
case 0xed: jsr_ix1(); break;
case 0xee: ldx_ix1(); break;
case 0xef: stx_ix1(); break;
case 0xf0: suba_ix(); break;
case 0xf1: cmpa_ix(); break;
case 0xf2: sbca_ix(); break;
case 0xf3: cpx_ix(); break;
case 0xf4: anda_ix(); break;
case 0xf5: bita_ix(); break;
case 0xf6: lda_ix(); break;
case 0xf7: sta_ix(); break;
case 0xf8: eora_ix(); break;
case 0xf9: adca_ix(); break;
case 0xfa: ora_ix(); break;
case 0xfb: adda_ix(); break;
case 0xfc: jmp_ix(); break;
case 0xfd: jsr_ix(); break;
case 0xfe: ldx_ix(); break;
case 0xff: stx_ix(); break;
}
m_icount -= m_cycles1[ireg];
} while( m_icount > 0 );
}
/* execute instructions on this CPU until icount expires */
static CPU_EXECUTE( m6809 ) /* NS 970908 */
{
m68_state_t *m68_state = get_safe_token(device);
m68_state->icount = cycles - m68_state->extra_cycles;
m68_state->extra_cycles = 0;
check_irq_lines(m68_state);
if (m68_state->int_state & (M6809_CWAI | M6809_SYNC))
{
debugger_instruction_hook(device, PCD);
m68_state->icount = 0;
}
else
{
do
{
pPPC = pPC;
debugger_instruction_hook(device, PCD);
m68_state->ireg = ROP(PCD);
PC++;
#if BIG_SWITCH
switch( m68_state->ireg )
{
case 0x00: neg_di(m68_state); break;
case 0x01: neg_di(m68_state); break; /* undocumented */
case 0x02: IIError(m68_state); break;
case 0x03: com_di(m68_state); break;
case 0x04: lsr_di(m68_state); break;
case 0x05: IIError(m68_state); break;
case 0x06: ror_di(m68_state); break;
case 0x07: asr_di(m68_state); break;
case 0x08: asl_di(m68_state); break;
case 0x09: rol_di(m68_state); break;
case 0x0a: dec_di(m68_state); break;
case 0x0b: IIError(m68_state); break;
case 0x0c: inc_di(m68_state); break;
case 0x0d: tst_di(m68_state); break;
case 0x0e: jmp_di(m68_state); break;
case 0x0f: clr_di(m68_state); break;
case 0x10: pref10(m68_state); break;
case 0x11: pref11(m68_state); break;
case 0x12: nop(m68_state); break;
case 0x13: sync(m68_state); break;
case 0x14: IIError(m68_state); break;
case 0x15: IIError(m68_state); break;
case 0x16: lbra(m68_state); break;
case 0x17: lbsr(m68_state); break;
case 0x18: IIError(m68_state); break;
case 0x19: daa(m68_state); break;
case 0x1a: orcc(m68_state); break;
case 0x1b: IIError(m68_state); break;
case 0x1c: andcc(m68_state); break;
case 0x1d: sex(m68_state); break;
case 0x1e: exg(m68_state); break;
case 0x1f: tfr(m68_state); break;
case 0x20: bra(m68_state); break;
case 0x21: brn(m68_state); break;
case 0x22: bhi(m68_state); break;
case 0x23: bls(m68_state); break;
case 0x24: bcc(m68_state); break;
case 0x25: bcs(m68_state); break;
case 0x26: bne(m68_state); break;
case 0x27: beq(m68_state); break;
case 0x28: bvc(m68_state); break;
case 0x29: bvs(m68_state); break;
case 0x2a: bpl(m68_state); break;
case 0x2b: bmi(m68_state); break;
case 0x2c: bge(m68_state); break;
case 0x2d: blt(m68_state); break;
case 0x2e: bgt(m68_state); break;
case 0x2f: ble(m68_state); break;
case 0x30: leax(m68_state); break;
case 0x31: leay(m68_state); break;
case 0x32: leas(m68_state); break;
case 0x33: leau(m68_state); break;
case 0x34: pshs(m68_state); break;
case 0x35: puls(m68_state); break;
case 0x36: pshu(m68_state); break;
case 0x37: pulu(m68_state); break;
case 0x38: IIError(m68_state); break;
case 0x39: rts(m68_state); break;
case 0x3a: abx(m68_state); break;
case 0x3b: rti(m68_state); break;
case 0x3c: cwai(m68_state); break;
case 0x3d: mul(m68_state); break;
case 0x3e: IIError(m68_state); break;
case 0x3f: swi(m68_state); break;
case 0x40: nega(m68_state); break;
case 0x41: IIError(m68_state); break;
case 0x42: IIError(m68_state); break;
case 0x43: coma(m68_state); break;
case 0x44: lsra(m68_state); break;
case 0x45: IIError(m68_state); break;
case 0x46: rora(m68_state); break;
case 0x47: asra(m68_state); break;
case 0x48: asla(m68_state); break;
case 0x49: rola(m68_state); break;
case 0x4a: deca(m68_state); break;
case 0x4b: IIError(m68_state); break;
case 0x4c: inca(m68_state); break;
case 0x4d: tsta(m68_state); break;
case 0x4e: IIError(m68_state); break;
case 0x4f: clra(m68_state); break;
case 0x50: negb(m68_state); break;
case 0x51: IIError(m68_state); break;
case 0x52: IIError(m68_state); break;
case 0x53: comb(m68_state); break;
case 0x54: lsrb(m68_state); break;
case 0x55: IIError(m68_state); break;
case 0x56: rorb(m68_state); break;
case 0x57: asrb(m68_state); break;
case 0x58: aslb(m68_state); break;
case 0x59: rolb(m68_state); break;
case 0x5a: decb(m68_state); break;
case 0x5b: IIError(m68_state); break;
case 0x5c: incb(m68_state); break;
case 0x5d: tstb(m68_state); break;
case 0x5e: IIError(m68_state); break;
case 0x5f: clrb(m68_state); break;
case 0x60: neg_ix(m68_state); break;
case 0x61: IIError(m68_state); break;
case 0x62: IIError(m68_state); break;
case 0x63: com_ix(m68_state); break;
case 0x64: lsr_ix(m68_state); break;
case 0x65: IIError(m68_state); break;
case 0x66: ror_ix(m68_state); break;
case 0x67: asr_ix(m68_state); break;
case 0x68: asl_ix(m68_state); break;
case 0x69: rol_ix(m68_state); break;
case 0x6a: dec_ix(m68_state); break;
case 0x6b: IIError(m68_state); break;
case 0x6c: inc_ix(m68_state); break;
case 0x6d: tst_ix(m68_state); break;
case 0x6e: jmp_ix(m68_state); break;
case 0x6f: clr_ix(m68_state); break;
case 0x70: neg_ex(m68_state); break;
case 0x71: IIError(m68_state); break;
case 0x72: IIError(m68_state); break;
case 0x73: com_ex(m68_state); break;
case 0x74: lsr_ex(m68_state); break;
case 0x75: IIError(m68_state); break;
case 0x76: ror_ex(m68_state); break;
case 0x77: asr_ex(m68_state); break;
case 0x78: asl_ex(m68_state); break;
case 0x79: rol_ex(m68_state); break;
case 0x7a: dec_ex(m68_state); break;
case 0x7b: IIError(m68_state); break;
case 0x7c: inc_ex(m68_state); break;
case 0x7d: tst_ex(m68_state); break;
case 0x7e: jmp_ex(m68_state); break;
case 0x7f: clr_ex(m68_state); break;
case 0x80: suba_im(m68_state); break;
case 0x81: cmpa_im(m68_state); break;
case 0x82: sbca_im(m68_state); break;
case 0x83: subd_im(m68_state); break;
case 0x84: anda_im(m68_state); break;
case 0x85: bita_im(m68_state); break;
case 0x86: lda_im(m68_state); break;
case 0x87: sta_im(m68_state); break;
case 0x88: eora_im(m68_state); break;
case 0x89: adca_im(m68_state); break;
case 0x8a: ora_im(m68_state); break;
case 0x8b: adda_im(m68_state); break;
case 0x8c: cmpx_im(m68_state); break;
case 0x8d: bsr(m68_state); break;
case 0x8e: ldx_im(m68_state); break;
case 0x8f: stx_im(m68_state); break;
case 0x90: suba_di(m68_state); break;
case 0x91: cmpa_di(m68_state); break;
case 0x92: sbca_di(m68_state); break;
case 0x93: subd_di(m68_state); break;
case 0x94: anda_di(m68_state); break;
case 0x95: bita_di(m68_state); break;
case 0x96: lda_di(m68_state); break;
case 0x97: sta_di(m68_state); break;
case 0x98: eora_di(m68_state); break;
case 0x99: adca_di(m68_state); break;
case 0x9a: ora_di(m68_state); break;
case 0x9b: adda_di(m68_state); break;
case 0x9c: cmpx_di(m68_state); break;
case 0x9d: jsr_di(m68_state); break;
case 0x9e: ldx_di(m68_state); break;
case 0x9f: stx_di(m68_state); break;
case 0xa0: suba_ix(m68_state); break;
case 0xa1: cmpa_ix(m68_state); break;
case 0xa2: sbca_ix(m68_state); break;
case 0xa3: subd_ix(m68_state); break;
case 0xa4: anda_ix(m68_state); break;
case 0xa5: bita_ix(m68_state); break;
case 0xa6: lda_ix(m68_state); break;
case 0xa7: sta_ix(m68_state); break;
case 0xa8: eora_ix(m68_state); break;
case 0xa9: adca_ix(m68_state); break;
case 0xaa: ora_ix(m68_state); break;
case 0xab: adda_ix(m68_state); break;
case 0xac: cmpx_ix(m68_state); break;
case 0xad: jsr_ix(m68_state); break;
case 0xae: ldx_ix(m68_state); break;
case 0xaf: stx_ix(m68_state); break;
case 0xb0: suba_ex(m68_state); break;
case 0xb1: cmpa_ex(m68_state); break;
case 0xb2: sbca_ex(m68_state); break;
case 0xb3: subd_ex(m68_state); break;
case 0xb4: anda_ex(m68_state); break;
case 0xb5: bita_ex(m68_state); break;
case 0xb6: lda_ex(m68_state); break;
case 0xb7: sta_ex(m68_state); break;
case 0xb8: eora_ex(m68_state); break;
case 0xb9: adca_ex(m68_state); break;
case 0xba: ora_ex(m68_state); break;
case 0xbb: adda_ex(m68_state); break;
case 0xbc: cmpx_ex(m68_state); break;
case 0xbd: jsr_ex(m68_state); break;
case 0xbe: ldx_ex(m68_state); break;
case 0xbf: stx_ex(m68_state); break;
case 0xc0: subb_im(m68_state); break;
case 0xc1: cmpb_im(m68_state); break;
case 0xc2: sbcb_im(m68_state); break;
case 0xc3: addd_im(m68_state); break;
case 0xc4: andb_im(m68_state); break;
case 0xc5: bitb_im(m68_state); break;
case 0xc6: ldb_im(m68_state); break;
case 0xc7: stb_im(m68_state); break;
case 0xc8: eorb_im(m68_state); break;
case 0xc9: adcb_im(m68_state); break;
case 0xca: orb_im(m68_state); break;
case 0xcb: addb_im(m68_state); break;
case 0xcc: ldd_im(m68_state); break;
case 0xcd: std_im(m68_state); break;
case 0xce: ldu_im(m68_state); break;
case 0xcf: stu_im(m68_state); break;
case 0xd0: subb_di(m68_state); break;
case 0xd1: cmpb_di(m68_state); break;
case 0xd2: sbcb_di(m68_state); break;
case 0xd3: addd_di(m68_state); break;
case 0xd4: andb_di(m68_state); break;
case 0xd5: bitb_di(m68_state); break;
case 0xd6: ldb_di(m68_state); break;
case 0xd7: stb_di(m68_state); break;
case 0xd8: eorb_di(m68_state); break;
case 0xd9: adcb_di(m68_state); break;
case 0xda: orb_di(m68_state); break;
case 0xdb: addb_di(m68_state); break;
case 0xdc: ldd_di(m68_state); break;
case 0xdd: std_di(m68_state); break;
case 0xde: ldu_di(m68_state); break;
case 0xdf: stu_di(m68_state); break;
case 0xe0: subb_ix(m68_state); break;
case 0xe1: cmpb_ix(m68_state); break;
case 0xe2: sbcb_ix(m68_state); break;
case 0xe3: addd_ix(m68_state); break;
case 0xe4: andb_ix(m68_state); break;
case 0xe5: bitb_ix(m68_state); break;
case 0xe6: ldb_ix(m68_state); break;
case 0xe7: stb_ix(m68_state); break;
case 0xe8: eorb_ix(m68_state); break;
case 0xe9: adcb_ix(m68_state); break;
case 0xea: orb_ix(m68_state); break;
case 0xeb: addb_ix(m68_state); break;
case 0xec: ldd_ix(m68_state); break;
case 0xed: std_ix(m68_state); break;
case 0xee: ldu_ix(m68_state); break;
case 0xef: stu_ix(m68_state); break;
case 0xf0: subb_ex(m68_state); break;
case 0xf1: cmpb_ex(m68_state); break;
case 0xf2: sbcb_ex(m68_state); break;
case 0xf3: addd_ex(m68_state); break;
case 0xf4: andb_ex(m68_state); break;
case 0xf5: bitb_ex(m68_state); break;
case 0xf6: ldb_ex(m68_state); break;
case 0xf7: stb_ex(m68_state); break;
case 0xf8: eorb_ex(m68_state); break;
case 0xf9: adcb_ex(m68_state); break;
case 0xfa: orb_ex(m68_state); break;
case 0xfb: addb_ex(m68_state); break;
case 0xfc: ldd_ex(m68_state); break;
case 0xfd: std_ex(m68_state); break;
case 0xfe: ldu_ex(m68_state); break;
case 0xff: stu_ex(m68_state); break;
}
#else
(*m6809_main[m68_state->ireg])(m68_state);
#endif /* BIG_SWITCH */
m68_state->icount -= cycles1[m68_state->ireg];
} while( m68_state->icount > 0 );
m68_state->icount -= m68_state->extra_cycles;
m68_state->extra_cycles = 0;
}
return cycles - m68_state->icount; /* NS 970908 */
}