void sys_cpu_en_timer(uint32_t counts, uint8_t ien) { /* Disable Counter by setting DC bit to 1 in CP0.Cause */ _CP0_BIS_CAUSE(_CP0_CAUSE_DC_MASK); _CP0_SET_COUNT(counts); if (ien) { jtvic_en_source(MEC14xx_GIRQ24_ID, 0, 0); } else { jtvic_dis_clr_source(MEC14xx_GIRQ24_ID, 0, 1); } /* Enable Counter */ _CP0_BIC_CAUSE(_CP0_CAUSE_DC_MASK); }
girq11_b8(void) { jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 8, JTVIC_CLR_SRC); }
girq25_b8(void) { jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 8); }
girq25_b27(void) { jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 27); }
girq25_b19(void) { jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 19); }
girq12_b2(void) { jtvic_dis_clr_source(MEC14xx_GIRQ12_ID, 2); }
girq14_b5(void) { jtvic_dis_clr_source(MEC14xx_GIRQ14_ID, 5); }
girq08_b6(void) { jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 6); }
girq08_b22(void) { jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 22); }
girq08_b19(void) { jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 19); }
girq23_b13(void) { jtvic_dis_clr_source(MEC14xx_GIRQ23_ID, 13, TRUE); }
girq23_b9(void) { jtvic_dis_clr_source(MEC14xx_GIRQ23_ID, 9, TRUE); }