void uart_mcumgr_free_rx_buf(struct uart_mcumgr_rx_buf *rx_buf)
{
void *block;
block = rx_buf;
k_mem_slab_free(&uart_mcumgr_slab, &block);
}
static void rx_queue_drop(struct stream *stream)
{
size_t size;
void *mem_block;
while (queue_get(&stream->mem_block_queue, &mem_block, &size) == 0) {
k_mem_slab_free(stream->cfg.mem_slab, &mem_block);
}
k_sem_reset(&stream->sem);
}
static void tx_queue_drop(struct stream *stream)
{
size_t size;
void *mem_block;
unsigned int n = 0U;
while (queue_get(&stream->mem_block_queue, &mem_block, &size) == 0) {
k_mem_slab_free(stream->cfg.mem_slab, &mem_block);
n++;
}
for (; n > 0; n--) {
k_sem_give(&stream->sem);
}
}
static void tx_stream_disable(struct stream *stream, struct device *dev)
{
const struct i2s_stm32_cfg *cfg = DEV_CFG(dev);
struct i2s_stm32_data *const dev_data = DEV_DATA(dev);
struct device *dev_dma = dev_data->dev_dma;
LL_I2S_DisableDMAReq_TX(cfg->i2s);
LL_I2S_DisableIT_ERR(cfg->i2s);
dma_stop(dev_dma, stream->dma_channel);
if (stream->mem_block != NULL) {
k_mem_slab_free(stream->cfg.mem_slab, &stream->mem_block);
stream->mem_block = NULL;
}
LL_I2S_Disable(cfg->i2s);
active_dma_tx_channel[stream->dma_channel] = NULL;
}
/* thread entry simply invoke the APIs*/
static void tmslab_api(void *p1, void *p2, void *p3)
{
void *block[BLK_NUM];
struct k_mem_slab *slab = slabs[atomic_inc(&slab_id) % SLAB_NUM];
int i = LOOP;
while (i--) {
memset(block, 0, sizeof(block));
for (int i = 0; i < BLK_NUM; i++) {
k_mem_slab_alloc(slab, &block[i], TIMEOUT);
}
for (int i = 0; i < BLK_NUM; i++) {
if (block[i]) {
k_mem_slab_free(slab, &block[i]);
block[i] = NULL;
}
}
}
k_sem_give(&sync_sema);
}
static void dma_tx_callback(void *arg, u32_t channel, int status)
{
struct device *dev = get_dev_from_tx_dma_channel(channel);
const struct i2s_stm32_cfg *cfg = DEV_CFG(dev);
struct i2s_stm32_data *const dev_data = DEV_DATA(dev);
struct stream *stream = &dev_data->tx;
size_t mem_block_size;
int ret;
if (status != 0) {
ret = -EIO;
stream->state = I2S_STATE_ERROR;
goto tx_disable;
}
__ASSERT_NO_MSG(stream->mem_block != NULL);
/* All block data sent */
k_mem_slab_free(stream->cfg.mem_slab, &stream->mem_block);
stream->mem_block = NULL;
/* Stop transmission if there was an error */
if (stream->state == I2S_STATE_ERROR) {
LOG_ERR("TX error detected");
goto tx_disable;
}
/* Stop transmission if we were requested */
if (stream->last_block) {
stream->state = I2S_STATE_READY;
goto tx_disable;
}
/* Prepare to send the next data block */
ret = queue_get(&stream->mem_block_queue, &stream->mem_block,
&mem_block_size);
if (ret < 0) {
if (stream->state == I2S_STATE_STOPPING) {
stream->state = I2S_STATE_READY;
} else {
stream->state = I2S_STATE_ERROR;
}
goto tx_disable;
}
k_sem_give(&stream->sem);
/* Assure cache coherency before DMA read operation */
DCACHE_CLEAN(stream->mem_block, mem_block_size);
ret = reload_dma(dev_data->dev_dma, stream->dma_channel,
&stream->dma_cfg,
stream->mem_block,
(void *)LL_SPI_DMA_GetRegAddr(cfg->i2s),
stream->cfg.block_size);
if (ret < 0) {
LOG_DBG("Failed to start TX DMA transfer: %d", ret);
goto tx_disable;
}
return;
tx_disable:
tx_stream_disable(stream, dev);
}