void
mv64x60_board_init(void __iomem *old_base, void __iomem *new_base)
{
mv64x60_console_baud = KATANA_DEFAULT_BAUD;
mv64x60_mpsc_clk_src = KATANA_MPSC_CLK_SRC;
mv64x60_mpsc_clk_freq =
min(katana_bus_freq((void __iomem *)KATANA_CPLD_BASE),
MV64x60_TCLK_FREQ_MAX);
}
static void __init
katana_setup_arch(void)
{
if (ppc_md.progress)
ppc_md.progress("katana_setup_arch: enter", 0);
set_tb(0, 0);
#ifdef CONFIG_BLK_DEV_INITRD
if (initrd_start)
ROOT_DEV = Root_RAM0;
else
#endif
#ifdef CONFIG_ROOT_NFS
ROOT_DEV = Root_NFS;
#else
ROOT_DEV = Root_SDA2;
#endif
/*
* Set up the L2CR register.
*
* 750FX has only L2E, L2PE (bits 2-8 are reserved)
* DD2.0 has bug that requires the L2 to be in WRT mode
* avoid dirty data in cache
*/
if (PVR_REV(mfspr(SPRN_PVR)) == 0x0200) {
printk(KERN_INFO "DD2.0 detected. Setting L2 cache"
"to Writethrough mode\n");
_set_L2CR(L2CR_L2E | L2CR_L2PE | L2CR_L2WT);
} else
_set_L2CR(L2CR_L2E | L2CR_L2PE);
if (ppc_md.progress)
ppc_md.progress("katana_setup_arch: calling setup_bridge", 0);
katana_setup_bridge();
katana_setup_peripherals();
katana_enable_ipmi();
katana_bus_frequency = katana_bus_freq(cpld_base);
printk(KERN_INFO "Artesyn Communication Products, LLC - Katana(TM)\n");
if (ppc_md.progress)
ppc_md.progress("katana_setup_arch: exit", 0);
}
