static int disable_lcd_reset(void)
{
if (l4vbus_gpio_write(vbus, gpio_handle, GPIO_NUM_RESB, 0))
return -1;
l4_usleep(100);
return 0;
}
static void issue_go_lcd(void)
{
l4_umword_t val = read_dss_reg(Reg_dispc_control);
// printf("Reg_dispc_control %x.\n",val);
val |= Dispc_control_golcd;
write_dss_reg(Reg_dispc_control, val);
l4_usleep(1000);
// if (read_dss_reg(Reg_dispc_control) & Dispc_control_golcd)
int err_cnt = 10;
while (read_dss_reg(Reg_dispc_control) & Dispc_control_golcd)
{
printf("[LCD] Info: Update DISPC timeout %x.\n",val);
l4_usleep(500);
if (err_cnt-- == 0)
while(1) ;
}
}
/* UDELAY */
void udelay(unsigned long usecs)
{
#ifdef ARCH_arm
l4_sleep(usecs/1000); // XXX
#elif defined(ARCH_mips)
#warning KYMA ARCH_mips l4_busy_wait_us() not implemented, using l4_usleep instead.
// this gives up control of cpu; it's not always what's wanted...
l4_usleep(usecs);
#else
l4_busy_wait_us(usecs);
#endif
}
static int disable_dss(void)
{
l4_umword_t val = read_dss_reg(Reg_dispc_control);
/* check if digital output or the lcd output are enabled */
if (val & (Dispc_control_digitalenable | Dispc_control_lcdenable))
{
/*Disable the lcd output and digital output*/
val &= ~(Dispc_control_digitalenable | Dispc_control_lcdenable);
write_dss_reg(Reg_dispc_control, val);
val = read_dss_reg(Reg_dispc_control);
write_dss_reg(Reg_dispc_irqstatus, Dispc_irqstatus_framedone);
l4_usleep(100);
if (!((val=read_dss_reg(Reg_dispc_irqstatus)) & Dispc_irqstatus_framedone))
while (!((val=read_dss_reg(Reg_dispc_irqstatus)) & Dispc_irqstatus_framedone))
{
printf("OMAP LCD: Disable DSS timeout.\n");
l4_usleep(100);
// write_dss_reg(Reg_dispc_irqstatus, Dispc_irqstatus_framedone);
}
}
return 0;
}
static void reset_display_controller(void)
{
disable_dss();
/* Reset the display controller. */
write_dss_reg(Reg_dispc_sysconfig, Dispc_sysconfig_softreset);
/* Wait until reset completes OR timeout occurs. */
l4_usleep(100);
if (!(read_dss_reg(Reg_dispc_sysstatus) & Dispc_sysstatus_resetdone))
{
printf("[LCD]: Warning: Reset DISPC timeout.\n");
}
l4_uint32_t reg_val = read_dss_reg(Reg_dispc_sysconfig);
reg_val &= ~Dispc_sysconfig_softreset;
write_dss_reg(Reg_dispc_sysconfig, reg_val);
}
int usleep(useconds_t usec)
{
l4_usleep(usec);
return 0;
}
