void viking_cache_enable(void) { u_int pcr; pcr = lda(SRMMU_PCR, ASI_SRMMU); if ((pcr & VIKING_PCR_ICE) == 0) { /* I-cache not on; "flash-clear" it now. */ sta(0x80000000, ASI_ICACHECLR, 0); /* Unlock */ sta(0, ASI_ICACHECLR, 0); /* clear */ } if ((pcr & VIKING_PCR_DCE) == 0) { /* D-cache not on: "flash-clear" it. */ sta(0x80000000, ASI_DCACHECLR, 0); sta(0, ASI_DCACHECLR, 0); } /* Turn on caches via MMU */ sta(SRMMU_PCR, ASI_SRMMU, pcr | VIKING_PCR_DCE | VIKING_PCR_ICE); CACHEINFO.c_enabled = CACHEINFO.dc_enabled = 1; /* Now turn on MultiCache if it exists */ if (cpuinfo.mxcc && CACHEINFO.ec_totalsize > 0) { /* Set external cache enable bit in MXCC control register */ stda(MXCC_CTRLREG, ASI_CONTROL, ldda(MXCC_CTRLREG, ASI_CONTROL) | MXCC_CTRLREG_CE); cpuinfo.flags |= CPUFLG_CACHEPAGETABLES; /* Ok to cache PTEs */ CACHEINFO.ec_enabled = 1; } }
void viking_cache_enable() { u_int pcr; cache_alias_dist = max( CACHEINFO.ic_totalsize / CACHEINFO.ic_associativity, CACHEINFO.dc_totalsize / CACHEINFO.dc_associativity); cache_alias_bits = (cache_alias_dist - 1) & ~PGOFSET; pcr = lda(SRMMU_PCR, ASI_SRMMU); if ((pcr & VIKING_PCR_ICE) == 0) { /* I-cache not on; "flash-clear" it now. */ sta(0x80000000, ASI_ICACHECLR, 0); /* Unlock */ sta(0, ASI_ICACHECLR, 0); /* clear */ } if ((pcr & VIKING_PCR_DCE) == 0) { /* D-cache not on: "flash-clear" it. */ sta(0x80000000, ASI_DCACHECLR, 0); sta(0, ASI_DCACHECLR, 0); } /* Turn on caches via MMU */ sta(SRMMU_PCR, ASI_SRMMU, pcr | VIKING_PCR_DCE | VIKING_PCR_ICE); CACHEINFO.c_enabled = CACHEINFO.dc_enabled = 1; /* Now turn on MultiCache if it exists */ if (cpuinfo.mxcc && CACHEINFO.ec_totalsize > 0) { /* Multicache controller */ stda(MXCC_ENABLE_ADDR, ASI_CONTROL, ldda(MXCC_ENABLE_ADDR, ASI_CONTROL) | (u_int64_t)MXCC_ENABLE_BIT); cpuinfo.flags |= CPUFLG_CACHEPAGETABLES; /* Ok to cache PTEs */ CACHEINFO.ec_enabled = 1; } printf("cache enabled\n"); }