int mainboard_io_trap_handler(int smif) { static int smm_initialized; if (!smm_initialized) { mainboard_smm_init(); smm_initialized = 1; } switch (smif) { case SMI_DOCK_CONNECT: /* If there's an legacy I/O module present, we're not * allowed to connect the Docking LPC Bus, as both Super I/O * chips are using 0x2e as base address. */ if (legacy_io_present()) break; if (!dock_connect()) { /* set dock LED to indicate status */ ec_write(0x0c, 0x08); ec_write(0x0c, 0x89); } else { /* blink dock LED to indicate failure */ ec_write(0x0c, 0xc8); ec_write(0x0c, 0x09); } break; case SMI_DOCK_DISCONNECT: dock_disconnect(); ec_write(0x0c, 0x09); ec_write(0x0c, 0x08); break; case SMI_BRIGHTNESS_UP: mainboard_smi_brightness_up(); break; case SMI_BRIGHTNESS_DOWN: mainboard_smi_brightness_down(); break; default: return 0; } /* On success, the IO Trap Handler returns 1 * On failure, the IO Trap Handler returns a value != 1 */ return 1; }
void main(unsigned long bist) { int s3resume = 0; int dock_err; const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0x52, 0x51, 0x53 }; timestamp_init(get_initial_timestamp()); timestamp_add_now(TS_START_ROMSTAGE); if (bist == 0) enable_lapic(); /* Force PCIRST# */ pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR); udelay(200 * 1000); pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0); ich7_enable_lpc(); /* We want early GPIO setup, to be able to detect legacy I/O module */ pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1); /* Enable GPIOs */ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c /* GC */ , 0x10); setup_ich7_gpios(); dock_err = dlpc_init(); /* We prefer Legacy I/O module over docking */ if (legacy_io_present()) { legacy_io_init(); early_superio_config(); } else if (!dock_err && dock_present()) { dock_connect(); early_superio_config(); } /* Setup the console */ console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); outb(0x6, 0xcf9); halt(); } /* Perform some early chipset initialization required * before RAM initialization can work */ i945_early_initialization(); s3resume = southbridge_detect_s3_resume(); /* Enable SPD ROMs and DDR-II DRAM */ enable_smbus(); #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 dump_spd_registers(); #endif timestamp_add_now(TS_BEFORE_INITRAM); sdram_initialize(s3resume ? 2 : 0, spd_addrmap); timestamp_add_now(TS_AFTER_INITRAM); /* Perform some initialization that must run before stage2 */ early_ich7_init(); /* This should probably go away. Until now it is required * and mainboard specific */ rcba_config(); /* Chipset Errata! */ fixup_i945_errata(); /* Initialize the internal PCIe links before we go into stage2 */ i945_late_initialization(s3resume); timestamp_add_now(TS_END_ROMSTAGE); }