void intel_mid_hsu_resume(int port, struct device *dev)
{
struct hsu_port_pin_cfg *info = hsu_port_gpio_mux + port;
if (info->wake_gpio)
free_irq(gpio_to_irq(info->wake_gpio), info->dev);
if(info->btwake_gpio)
{
/* Broadcom,tell bt chip to wake up now*/
gpio_direction_output(info->btwake_gpio,1);
}
if (info->rx_gpio) {
lnw_gpio_set_alt(info->rx_gpio, info->rx_alt);
gpio_direction_input(info->rx_gpio);
}
if (info->tx_gpio) {
gpio_direction_output(info->tx_gpio, 1);
lnw_gpio_set_alt(info->tx_gpio, info->tx_alt);
usleep_range(10, 10);
gpio_direction_output(info->tx_gpio, 0);
}
if (info->cts_gpio) {
lnw_gpio_set_alt(info->cts_gpio, info->cts_alt);
gpio_direction_input(info->cts_gpio);
}
}
void intel_mid_hsu_resume(int port, struct device *dev)
{
struct hsu_port_pin_cfg *info = hsu_port_gpio_mux + port;
if (info->rts_fixed)
return;
if (info->wake_gpio)
free_irq(gpio_to_irq(info->wake_gpio), info->dev);
if (info->rx_gpio) {
lnw_gpio_set_alt(info->rx_gpio, info->rx_alt);
gpio_direction_input(info->rx_gpio);
}
if (info->tx_gpio) {
gpio_direction_output(info->tx_gpio, 1);
lnw_gpio_set_alt(info->tx_gpio, info->tx_alt);
usleep_range(10, 10);
gpio_direction_output(info->tx_gpio, 0);
}
if (info->cts_gpio) {
lnw_gpio_set_alt(info->cts_gpio, info->cts_alt);
gpio_direction_input(info->cts_gpio);
}
}
void intel_mid_hsu_rts_fixed(int port, bool enable)
{
struct hsu_port_pin_cfg *info = hsu_port_gpio_mux + port;
if (enable) {
if (info->tx_gpio) {
lnw_gpio_set_alt(info->tx_gpio, LNW_GPIO);
gpio_direction_input(info->tx_gpio);
}
if (info->rts_gpio) {
lnw_gpio_set_alt(info->rts_gpio, LNW_GPIO);
gpio_direction_input(info->rts_gpio);
}
} else {
if (info->tx_gpio) {
gpio_direction_output(info->tx_gpio, 1);
lnw_gpio_set_alt(info->tx_gpio, info->tx_alt);
udelay(10);
gpio_direction_output(info->tx_gpio, 0);
}
if (info->rts_gpio) {
gpio_direction_output(info->rts_gpio, 0);
lnw_gpio_set_alt(info->rts_gpio, info->rts_alt);
}
}
info->rts_fixed = enable;
}
void max17042_i2c_reset_workaround(void)
{
/* toggle clock pin of I2C to recover devices from abnormal status.
* currently, only max17042 on I2C needs such workaround */
#if defined(CONFIG_BATTERY_INTEL_MDF)
#define I2C_GPIO_PIN 27
#elif defined(CONFIG_BOARD_CTP)
#define I2C_GPIO_PIN 29
#elif defined(CONFIG_X86_MRFLD)
#define I2C_GPIO_PIN 21
#else
#define I2C_GPIO_PIN 27
#endif
#define I2C0_GPIO_PIN_BYT_CR_V2 79
int i2c_gpio_pin = I2C_GPIO_PIN;
if (INTEL_MID_BOARD(3, TABLET, BYT, BLK, PRO, CRV2) ||
INTEL_MID_BOARD(3, TABLET, BYT, BLK, ENG, CRV2))
i2c_gpio_pin = I2C0_GPIO_PIN_BYT_CR_V2;
lnw_gpio_set_alt(i2c_gpio_pin, LNW_GPIO);
gpio_direction_output(i2c_gpio_pin, 0);
gpio_set_value(i2c_gpio_pin, 1);
udelay(10);
gpio_set_value(i2c_gpio_pin, 0);
udelay(10);
lnw_gpio_set_alt(i2c_gpio_pin, LNW_ALT_1);
}
/*
* MFLD PR2 secondary camera sensor - gc2155 platform data
*/
static int gc2155_gpio_ctrl(struct v4l2_subdev *sd, int flag)
{
int ret;
pr_info("%s - E, flag: %d\n", __func__, flag);
if (gpio_cam_pwdn < 0) {
ret = camera_sensor_gpio(-1, "SUB_CAM_PWDN",
GPIOF_DIR_OUT, 0);
if (ret < 0)
return ret;
gpio_cam_pwdn = GP_CORE_064;
/* set camera pwdn pin mode to gpio */
lnw_gpio_set_alt(gpio_cam_pwdn, LNW_GPIO);
}
if (camera_reset < 0) {
ret = camera_sensor_gpio(-1, "SUB_CAM_RST#_R",
GPIOF_DIR_OUT, 0);
if (ret < 0)
return ret;
camera_reset = GP_CORE_080;
/* set camera reset pin mode to gpio */
lnw_gpio_set_alt(camera_reset, LNW_GPIO);
}
if (flag) {
//gc2155 Power up:
pr_info("%s(%d): pwdn(0)\n", __func__, __LINE__);
gpio_set_value(gpio_cam_pwdn, 0);
msleep(2);
pr_info("%s(%d): reset(1)\n", __func__, __LINE__);
gpio_set_value(camera_reset, 1);
} else {
// gc2155 Power down:
pr_info("%s(%d): pwdn(1)\n", __func__, __LINE__);
gpio_set_value(gpio_cam_pwdn, 1);
gpio_free(gpio_cam_pwdn);
gpio_cam_pwdn = -1;
msleep(2);
pr_info("%s(%d): reset(0)\n", __func__, __LINE__);
gpio_set_value(camera_reset, 0);
gpio_free(camera_reset);
camera_reset = -1;
}
return 0;
}
void intel_mid_hsu_rts(int port, int value)
{
struct hsu_port_pin_cfg *info = hsu_port_gpio_mux + port;
if (!info->rts_gpio)
return;
if (value) {
gpio_direction_output(info->rts_gpio, 1);
lnw_gpio_set_alt(info->rts_gpio, LNW_GPIO);
} else
lnw_gpio_set_alt(info->rts_gpio, info->rts_alt);
}
static int hdmi_i2c_workaround(void)
{
struct platform_device *pdev;
struct i2c_gpio_platform_data *pdata;
/*
* Hard code a gpio controller platform device to take over
* the two gpio pins used to be controlled by i2c bus 3.
* This is to support HDMI EDID extension block read, which
* is not supported by the current i2c controller, so we use
* GPIO pin the simulate an i2c bus.
*/
/* On Merrifield, bus number 8 is used for battery charger.
* use 10 across medfield/ctp/merrifield platforms.
*/
pdev = platform_device_alloc(DEVICE_NAME, 10);
if (!pdev) {
pr_err("i2c-gpio: failed to alloc platform device\n");
return -ENOMEM;
}
pdata = kzalloc(sizeof(struct i2c_gpio_platform_data), GFP_KERNEL);
if (!pdata) {
pr_err("i2c-gpio: failed to alloc platform data\n");
kfree(pdev);
return -ENOMEM;
}
if (INTEL_MID_BOARD(1, PHONE, MRFL) ||
INTEL_MID_BOARD(1, TABLET, MRFL)) {
/* Pins 17 and 18 are used in Merrifield for HDMI i2c (bus3) */
pdata->scl_pin = 17;
pdata->sda_pin = 18;
} else {
pdata->scl_pin = 35 + 96;
pdata->sda_pin = 36 + 96;
}
pdata->sda_is_open_drain = 0;
pdata->scl_is_open_drain = 0;
pdev->dev.platform_data = pdata;
platform_device_add(pdev);
lnw_gpio_set_alt(pdata->sda_pin, LNW_GPIO);
lnw_gpio_set_alt(pdata->scl_pin, LNW_GPIO);
return 0;
}
static int otm1284a_vid_set_brightness(struct mdfld_dsi_config *dsi_config,
int level)
{
u32 reg_level;
union pwmctrl_reg pwmctrl;
#ifdef CONFIG_BACKLIGHT_RT4532
rt4532_brightness_set(level);
#else
// /* Re-assign the minimum brightness value to 15 */
// if (level > 0 && level <= 15)
// level = 15;
//
reg_level = ~level & 0xFF;
pwmctrl.part.pwmswupdate = 0x1;
pwmctrl.part.pwmbu = PWM_BASE_UNIT;
pwmctrl.part.pwmtd = reg_level;
if (!pwmctrl_mmio)
pwmctrl_mmio = ioremap_nocache(PWMCTRL_REG, 4);
if (pwmctrl_mmio) {
if (level) {
if (!gpio_get_value(backlight_en_gpio)) {
pmu_set_pwm(PCI_D0);
lnw_gpio_set_alt(backlight_pwm_gpio, 1);
gpio_set_value_cansleep(backlight_en_gpio, 1);
}
pwmctrl.part.pwmenable = 1;
writel(pwmctrl.full, pwmctrl_mmio);
} else if (gpio_get_value(backlight_en_gpio)) {
pwmctrl.part.pwmenable = 0;
writel(pwmctrl.full, pwmctrl_mmio);
gpio_set_value_cansleep(backlight_pwm_gpio, 0);
lnw_gpio_set_alt(backlight_pwm_gpio, 0);
usleep_range(10000, 10100);
gpio_set_value_cansleep(backlight_en_gpio, 0);
pmu_set_pwm(PCI_D3hot);
}
} else {
DRM_ERROR("Cannot map pwmctrl\n");
}
printk("[DISP] brightness level = %d\n", level);
#endif
return 0;
}
static void dc_xpwr_pwrsrc_pdata(void)
{
static struct dc_xpwr_pwrsrc_pdata pdata;
#if defined(CONFIG_MRD8) || defined(CONFIG_MRD7P05)
int ret;
pdata.mux_gpio = 131; /* GPIO_S5[1] */
ret = gpio_request(pdata.mux_gpio, "otg_gpio");
if (ret) {
pr_err("unable to request GPIO pin\n");
pdata.mux_gpio = -1;
} else {
lnw_gpio_set_alt(pdata.mux_gpio, 0);
}
/*
* set en_chrg_det to true if the
* D+/D- lines are connected to
* PMIC itself.
*/
pdata.en_chrg_det = true;
#else
pdata.en_chrg_det = false;
#endif
intel_mid_pmic_set_pdata("dollar_cove_pwrsrc",
(void *)&pdata, sizeof(pdata), 0);
}
static void dc_xpwr_chrg_pdata(void)
{
static struct dollarcove_chrg_pdata pdata;
int ret;
pdata.max_cc = 2000;
pdata.max_cv = 4350;
pdata.def_cc = 500;
pdata.def_cv = 4350;
pdata.def_ilim = 900;
pdata.def_iterm = 300;
pdata.def_max_temp = 55;
pdata.def_min_temp = 0;
pdata.otg_gpio = 117; /* GPIONC_15 */
/* configure output */
ret = gpio_request(pdata.otg_gpio, "otg_gpio");
if (ret) {
pr_err("unable to request GPIO pin\n");
pdata.otg_gpio = -1;
} else {
lnw_gpio_set_alt(pdata.otg_gpio, 0);
}
platform_init_chrg_params(&pdata);
intel_mid_pmic_set_pdata("dollar_cove_charger",
(void *)&pdata, sizeof(pdata), 0);
}
/* Board specific setup related to SD goes here */
static int mrfl_sd_setup(struct sdhci_pci_data *data)
{
u8 vldocnt = 0;
int err;
/*
* Change necessary GPIO pin mode for SD card working.
* This is something should be done in IA firmware.
* But, anyway, just do it here in case IA firmware
* forget to do so.
*/
lnw_gpio_set_alt(MRFLD_GPIO_SDIO_0_CD, 0);
err = intel_scu_ipc_ioread8(MRFLD_PMIC_VLDOCNT, &vldocnt);
if (err) {
pr_err("PMIC vldocnt IPC read error: %d\n", err);
return err;
}
vldocnt |= MRFLD_PMIC_VLDOCNT_VSWITCH_BIT;
err = intel_scu_ipc_iowrite8(MRFLD_PMIC_VLDOCNT, vldocnt);
if (err) {
pr_err("PMIC vldocnt IPC write error: %d\n", err);
return err;
}
msleep(20);
return 0;
}
static int hsic_wakeup_irq_init(void)
{
int retval;
dev_dbg(&pci_dev->dev,
"%s---->\n", __func__);
if (hsic.hsic_wakeup_irq_enable) {
dev_dbg(&pci_dev->dev,
"%s<----Wakeup IRQ is enabled\n", __func__);
return 0;
}
hsic.hsic_wakeup_irq_enable = 1;
gpio_direction_input(hsic.wakeup_gpio);
retval = request_irq(gpio_to_irq(hsic.wakeup_gpio),
hsic_wakeup_gpio_irq,
IRQF_SHARED | IRQF_TRIGGER_RISING | IRQF_NO_SUSPEND,
"hsic_remote_wakeup_request", &pci_dev->dev);
if (retval) {
dev_err(&pci_dev->dev,
"unable to request irq %i, err: %d\n",
gpio_to_irq(hsic.wakeup_gpio), retval);
goto err;
}
lnw_gpio_set_alt(hsic.wakeup_gpio, 0);
dev_dbg(&pci_dev->dev,
"%s<----\n", __func__);
return retval;
err:
hsic.hsic_wakeup_irq_enable = 0;
free_irq(gpio_to_irq(hsic.wakeup_gpio), &pci_dev->dev);
return retval;
}
static int hsic_aux_irq_init(int pin)
{
int retval;
dev_dbg(&pci_dev->dev, "%s---->%d\n", __func__, pin);
if (hsic.hsic_aux_irq_enable) {
dev_dbg(&pci_dev->dev,
"%s<----AUX IRQ is enabled\n", __func__);
return 0;
}
hsic.hsic_aux_irq_enable = 1;
gpio_direction_input(pin);
retval = request_irq(gpio_to_irq(pin),
hsic_aux_gpio_irq,
IRQF_NO_SUSPEND | IRQF_TRIGGER_RISING,
"hsic_disconnect_request", &pci_dev->dev);
if (retval) {
dev_err(&pci_dev->dev,
"unable to request irq %i, err: %d\n",
gpio_to_irq(pin), retval);
goto err;
}
lnw_gpio_set_alt(pin, 0);
dev_dbg(&pci_dev->dev, "%s<----\n", __func__);
return retval;
err:
hsic.hsic_aux_irq_enable = 0;
free_irq(gpio_to_irq(pin), &pci_dev->dev);
return retval;
}
static void *get_platform_data(void)
{
int ret;
pdata.max_cc = 2000;
pdata.max_cv = 4350;
pdata.def_cc = 500;
pdata.def_cv = 4350;
pdata.def_ilim = 900;
pdata.def_iterm = 300;
pdata.def_max_temp = 55;
pdata.def_min_temp = 0;
pdata.otg_gpio = 3; /* GPIOC_03 */
/* configure output */
ret = gpio_request(pdata.otg_gpio, "otg_gpio");
if (ret) {
pr_err("unable to request GPIO pin\n");
pdata.otg_gpio = -1;
} else {
lnw_gpio_set_alt(pdata.otg_gpio, 0);
}
platform_init_chrg_params(&pdata);
return &pdata;
}
static int otm1901a_vid_set_brightness(struct mdfld_dsi_config *dsi_config,
int level)
{
u32 reg_level = ~level & 0xFF;
union pwmctrl_reg pwmctrl;
static void __iomem *bl_en_mmio;
#ifdef CONFIG_BACKLIGHT_RT4532
rt4532_brightness_set(level);
#endif
pwmctrl.part.pwmswupdate = 0x1;
pwmctrl.part.pwmbu = PWM_BASE_UNIT;
pwmctrl.part.pwmtd = reg_level;
if (!pwmctrl_mmio)
pwmctrl_mmio = ioremap_nocache(PWMCTRL_REG, 4);
if (!bl_en_mmio)
bl_en_mmio = ioremap_nocache(BL_EN_REG, 4);
if (pwmctrl_mmio) {
if (level) {
if (!gpio_get_value(backlight_en_gpio)) {
writel((readl(bl_en_mmio) | PULL_UP_EN) & (~PULL_DOWN_EN), bl_en_mmio);
pmu_set_pwm(PCI_D0);
lnw_gpio_set_alt(backlight_pwm_gpio, 1);
gpio_set_value_cansleep(backlight_en_gpio, 1);
}
pwmctrl.part.pwmenable = 1;
writel(pwmctrl.full, pwmctrl_mmio);
} else if (gpio_get_value(backlight_en_gpio)) {
writel(pwmctrl.full, pwmctrl_mmio);
pwmctrl.part.pwmenable = 0;
gpio_set_value_cansleep(backlight_en_gpio, 0);
lnw_gpio_set_alt(backlight_pwm_gpio, 0);
writel((readl(bl_en_mmio) | PULL_DOWN_EN) & (~PULL_UP_EN), bl_en_mmio);
pmu_set_pwm(PCI_D3hot);
}
} else {
DRM_ERROR("Cannot map pwmctrl\n");
}
printk("[DISP] brightness level = %d\n", level);
return 0;
}
void intel_mid_hsu_rts(int port, int value)
{
struct hsu_port_pin_cfg *info = hsu_port_gpio_mux + port;
if (!info->rts_gpio)
return;
/*ASUS-BBSP Skip configure in charger mode+++*/
if (!g_Main_mode)
return;
/*ASUS-BBSP Skip configure in charger mode---*/
if (value) {
gpio_direction_output(info->rts_gpio, 1);
lnw_gpio_set_alt(info->rts_gpio, LNW_GPIO);
} else
lnw_gpio_set_alt(info->rts_gpio, info->rts_alt);
}
static int intel_vibra_runtime_resume(struct device *dev)
{
struct vibra_info *info = dev_get_drvdata(dev);
pr_debug("In %s\n", __func__);
lnw_gpio_set_alt(INTEL_PWM_ENABLE_GPIO, LNW_ALT_2);
vibra_pwm_configure(info, true);
return 0;
}
void max17042_i2c_reset_workaround(void)
{
/* toggle clock pin of I2C to recover devices from abnormal status.
* currently, only max17042 on I2C needs such workaround */
#if defined(CONFIG_BOARD_CTP)
#define I2C_GPIO_PIN 29
#elif defined(CONFIG_X86_MRFLD)
#define I2C_GPIO_PIN 21
#else
#define I2C_GPIO_PIN 27
#endif
lnw_gpio_set_alt(I2C_GPIO_PIN, LNW_GPIO);
gpio_direction_output(I2C_GPIO_PIN, 0);
gpio_set_value(I2C_GPIO_PIN, 1);
udelay(10);
gpio_set_value(I2C_GPIO_PIN, 0);
udelay(10);
lnw_gpio_set_alt(I2C_GPIO_PIN, LNW_ALT_1);
}
void intel_mid_hsu_suspend_post(int port)
{
struct hsu_port_pin_cfg *info = hsu_port_gpio_mux + port;
if (info->rts_gpio && info->wake_gpio
&& info->wake_gpio == info->rx_gpio) {
gpio_direction_output(info->rts_gpio, 0);
lnw_gpio_set_alt(info->rts_gpio, LNW_GPIO);
}
}
static int config_alt(int gpio)
{
int ret;
ret = gpio_request(gpio, "xmm2230");
if(ret)
{
pr_err("xmm2230 gpio_request %d failed. status=%d\n", gpio, ret);
return ret;
}
gpio_direction_input(gpio);
lnw_gpio_set_alt(gpio, 1);
gpio_free(gpio);
return 0;
}
static void hsu_port_disable(int port)
{
struct hsu_port_pin_cfg *info = hsu_port_gpio_mux + port;
if (info->rx_gpio) {
lnw_gpio_set_alt(info->rx_gpio, LNW_GPIO);
gpio_direction_input(info->rx_gpio);
}
if (info->tx_gpio) {
gpio_direction_output(info->tx_gpio, 1);
lnw_gpio_set_alt(info->tx_gpio, LNW_GPIO);
usleep_range(10, 10);
gpio_direction_input(info->tx_gpio);
}
if (info->cts_gpio) {
lnw_gpio_set_alt(info->cts_gpio, LNW_GPIO);
gpio_direction_input(info->cts_gpio);
}
if (info->rts_gpio) {
lnw_gpio_set_alt(info->rts_gpio, LNW_GPIO);
gpio_direction_input(info->rts_gpio);
}
}
static int config_output_low(int gpio)
{
int ret;
ret = gpio_request(gpio, "xmm2230");
if(ret)
{
pr_err("xmm2230 gpio_request %d failed. status=%d\n", gpio, ret);
return ret;
}
lnw_gpio_set_alt(gpio, LNW_GPIO);
gpio_direction_output(gpio, 0);
gpio_free(gpio);
return 0;
}
static void spi_hw_resources_setup(struct m10mo_atomisp_spi_platform_data *pdata)
{
/* Setup SPI interface */
if (gpio_request(pdata->spi_cs_gpio, "m10mo_spi_cs")) {
pr_err("Can't allocate gpio for m10mo spi chip select.\n");
pr_err("Disabling FW update over the SPI\n");
pdata->spi_enabled = false;
return;
}
cs_chip_select = pdata->spi_cs_gpio;
lnw_gpio_set_alt(cs_chip_select, LNW_GPIO);
gpio_direction_output(cs_chip_select, 0);
lnw_gpio_set_alt(116, LNW_ALT_1);
lnw_gpio_set_alt(118, LNW_ALT_1);
lnw_gpio_set_alt(119, LNW_ALT_1);
#ifdef CONFIG_INTEL_SCU_FLIS
/* Setup flis configuration if requested to do so */
if (pdata->spi_clock_flis != -1)
config_pin_flis(pdata->spi_clock_flis, MUX,
MUX_EN_OUTPUT_EN | OUTPUT_EN);
if (pdata->spi_dataout_flis != -1)
config_pin_flis(pdata->spi_dataout_flis, MUX,
MUX_EN_OUTPUT_EN | OUTPUT_EN);
if (pdata->spi_datain_flis != -1)
config_pin_flis(pdata->spi_datain_flis,
MUX, MUX_EN_INPUT_EN | INPUT_EN);
if (pdata->spi_cs_flis != -1)
config_pin_flis(pdata->spi_cs_flis,
MUX, MUX_EN_OUTPUT_EN | OUTPUT_EN);
#endif
}
void *fsa9285_platform_data(void)
{
int ret = 0;
fsa_pdata.enable_vbus = crystal_cove_enable_vbus;
fsa_pdata.disable_vbus = crystal_cove_disable_vbus;
if (INTEL_MID_BOARD(3, TABLET, BYT, BLK, PRO, 8PR0) ||
INTEL_MID_BOARD(3, TABLET, BYT, BLK, ENG, 8PR0) ||
INTEL_MID_BOARD(3, TABLET, BYT, BLK, PRO, 8PR1) ||
INTEL_MID_BOARD(3, TABLET, BYT, BLK, ENG, 8PR1)) {
/* Get SMB347 platform data for BYT-FFRD8 PR0/PR1 targets */
fsa_pdata.sdp_pre_setup = smb347_disable_charger;
fsa_pdata.sdp_post_setup = smb347_enable_charger;
} else {
/* Else consider dummy data */
fsa_pdata.sdp_pre_setup = fsa_dummy_sdp_pre_setup;
fsa_pdata.sdp_post_setup = fsa_dummy_sdp_post_setup;
}
ret = gpio_request(OTG_MUX_GPIO, "fsa-otg-mux");
if (ret) {
pr_err("unable to request GPIO pin\n");
/* WA for FFRD8 as USB3 mux not available */
fsa_pdata.mux_gpio = -1;
} else {
fsa_pdata.mux_gpio = OTG_MUX_GPIO;
}
if (INTEL_MID_BOARD(3, TABLET, BYT, BLK, PRO, 10PR11) ||
INTEL_MID_BOARD(3, TABLET, BYT, BLK, ENG, 10PR11)) {
ret = gpio_request(OTG_XSD_GPIO, "fsa-otg-xsd");
if (ret) {
pr_err("unable to request GPIO pin\n");
fsa_pdata.xsd_gpio = -1;
} else {
/* configure pin number for FFRD10 */
fsa_pdata.xsd_gpio = OTG_XSD_GPIO;
/* workaround for pin setting */
lnw_gpio_set_alt(OTG_XSD_GPIO, 0);
}
} else {
/* FFRD8 doesn't need this pin */
fsa_pdata.xsd_gpio = -1;
}
return &fsa_pdata;
}
static int intel_sst_runtime_resume(struct device *dev)
{
u32 csr;
pr_debug("runtime_resume called\n");
if (sst_drv_ctx->sst_state != SST_SUSPENDED) {
pr_err("SST is not in suspended state\n");
return 0;
}
csr = sst_shim_read(sst_drv_ctx->shim, SST_CSR);
/*
* To restore the csr_value after S0ix and S3 states.
* The value 0x30000 is to enable LPE dram high and low addresses.
* Reference:
* Penwell Audio Voice Module HAS 1.61 Section - 13.12.1 -
* CSR - Configuration and Status Register.
*/
csr |= (sst_drv_ctx->csr_value | 0x30000);
sst_shim_write(sst_drv_ctx->shim, SST_CSR, csr);
/* GPIO_PIN 12,13,74,75 needs to be configured in
* ALT_FUNC_2 mode for SSP3 IOs
*/
if (sst_drv_ctx->pci_id == SST_CLV_PCI_ID) {
lnw_gpio_set_alt(CLV_I2S_3_CLK_GPIO_PIN, LNW_ALT_2);
lnw_gpio_set_alt(CLV_I2S_3_FS_GPIO_PIN, LNW_ALT_2);
lnw_gpio_set_alt(CLV_I2S_3_TXD_GPIO_PIN, LNW_ALT_2);
lnw_gpio_set_alt(CLV_I2S_3_RXD_GPIO_PIN, LNW_ALT_2);
lnw_gpio_set_alt(CLV_VIBRA_PWM_GPIO_PIN, LNW_ALT_2);
vibra_pwm_configure(true);
}
sst_set_fw_state_locked(sst_drv_ctx, SST_UN_INIT);
return 0;
}
void intel_mid_hsu_suspend(int port, struct device *dev, irq_handler_t wake_isr)
{
int ret;
struct hsu_port_pin_cfg *info = hsu_port_gpio_mux + port;
info->dev = dev;
info->wake_isr = wake_isr;
if (info->wake_gpio) {
lnw_gpio_set_alt(info->wake_gpio, LNW_GPIO);
gpio_direction_input(info->wake_gpio);
udelay(10);
ret = request_irq(gpio_to_irq(info->wake_gpio), info->wake_isr,
IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING,
info->name, info->dev);
if (ret)
dev_err(info->dev, "failed to register wakeup irq\n");
}
}
static int otm1284a_vid_detect(struct mdfld_dsi_config *dsi_config)
{
printk("[DISP] %s\n", __func__);
panel_reset_gpio = get_gpio_by_name("DISP_RST_N");
if (panel_reset_gpio < 0) {
DRM_ERROR("Faild to get panel reset gpio\n");
return -EINVAL;
}
if (gpio_request(panel_reset_gpio, "panel_reset")) {
DRM_ERROR("Faild to request panel reset gpio\n");
return -EINVAL;
}
#ifndef CONFIG_BACKLIGHT_RT4532
backlight_en_gpio = OTM1284A_BL_EN_GPIO;
if (gpio_request(backlight_en_gpio, "backlight_en")) {
DRM_ERROR("Faild to request backlight enable gpio\n");
return -EINVAL;
}
backlight_pwm_gpio = OTM1284A_BL_PWM_GPIO;
if (gpio_request(backlight_pwm_gpio, "backlight_pwm")) {
DRM_ERROR("Faild to request backlight PWM gpio\n");
return -EINVAL;
}
/* Initializing pwm for being able to adjust backlight when just opening the phone. */
pmu_set_pwm(PCI_D0);
lnw_gpio_set_alt(backlight_pwm_gpio, 1);
#endif
dsi_config->dsi_hw_context.panel_on = true;
return MDFLD_DSI_PANEL_CONNECTED;
}
void intel_mid_hsu_suspend(int port, struct device *dev, irq_handler_t wake_isr)
{
int ret;
struct hsu_port_pin_cfg *info = hsu_port_gpio_mux + port;
info->dev = dev;
info->wake_isr = wake_isr;
if (info->wake_gpio) {
lnw_gpio_set_alt(info->wake_gpio, LNW_GPIO);
gpio_direction_input(info->wake_gpio);
udelay(10);
ret = request_irq(gpio_to_irq(info->wake_gpio), info->wake_isr,
IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING |IRQF_NO_SUSPEND,
info->name, info->dev);
if(info->btwake_gpio){
/* Broadcom,tell bt chip to go to sleep now*/
printk("%s, pull down gpio=%d to tell bt sleep\n",__func__, info->btwake_gpio);
gpio_direction_output(info->btwake_gpio,0);
}
if (ret)
dev_err(info->dev, "failed to register wakeup irq\n");
}
}
static int __devinit intel_mid_vibra_probe(struct pci_dev *pci,
const struct pci_device_id *pci_id)
{
struct vibra_info *info;
int ret = 0;
pr_debug("Probe for DID %x\n", pci->device);
info = devm_kzalloc(&pci->dev, sizeof(*info), GFP_KERNEL);
if (!info)
return -ENOMEM;
ret = gpio_request_one(INTEL_VIBRA_ENABLE_GPIO, GPIOF_DIR_OUT,
"VIBRA ENABLE");
if (ret != 0) {
pr_err("gpio_request(%d) fails:%d\n",
INTEL_VIBRA_ENABLE_GPIO, ret);
goto out;
}
ret = gpio_request_one(INTEL_PWM_ENABLE_GPIO, GPIOF_DIR_OUT,
"PWM ENABLE");
if (ret != 0) {
pr_err("gpio_request(%d) fails:%d\n",
INTEL_PWM_ENABLE_GPIO, ret);
goto do_freegpio_vibra_enable;
}
/* Init the device */
ret = pci_enable_device(pci);
if (ret) {
pr_err("device can't be enabled\n");
goto do_freegpio_pwm;
}
ret = pci_request_regions(pci, INTEL_VIBRA_DRV_NAME);
if (ret)
goto do_disable_device;
info->pci = pci_dev_get(pci);
/* vibra Shim */
info->shim = pci_ioremap_bar(pci, 0);
if (!info->shim) {
pr_err("ioremap failed for vibra driver\n");
goto do_release_regions;
}
/*set default value to Max */
info->pwm.part.pwmbu = INTEL_VIBRA_MAX_BASEUNIT;
info->pwm.part.pwmtd = INTEL_VIBRA_MAX_TIMEDIVISOR;
info->dev = &pci->dev;
info->name = "intel_mid:vibrator";
mutex_init(&info->lock);
if (vibra_register_sysfs(info) < 0) {
pr_err("could not register sysfs files\n");
goto do_unmap_shim;
}
lnw_gpio_set_alt(INTEL_PWM_ENABLE_GPIO, LNW_ALT_2);
vibra_pwm_configure(info, true);
pci_set_drvdata(pci, info);
pm_runtime_allow(&pci->dev);
pm_runtime_put_noidle(&pci->dev);
return ret;
do_unmap_shim:
iounmap(info->shim);
do_release_regions:
pci_release_regions(pci);
do_disable_device:
pci_disable_device(pci);
do_freegpio_pwm:
gpio_free(INTEL_PWM_ENABLE_GPIO);
do_freegpio_vibra_enable:
gpio_free(INTEL_VIBRA_ENABLE_GPIO);
out:
return ret;
}
static int m10mo_power_ctrl(struct v4l2_subdev *sd, int flag)
{
int ret = 0;
pr_info("M10MO power control. flag=%d\n", flag);
if(Read_PROJ_ID() != PROJ_ID_ZX550ML){
pr_err("M10MO, this is not ZX550ML, break! \n");
return -1;
}
set_flis_value(0x3221, 0x2D18);
#ifdef CONFIG_CRYSTAL_COVE
if (flag) {
ret = intel_mid_pmic_writeb(VPROG_2P8V, VPROG_ENABLE);
if (ret) {
pr_err("Failed to power on V2P8SX.\n");
return ret;
}
ret = intel_mid_pmic_writeb(VPROG_1P2V, VPROG_ENABLE);
if (ret) {
pr_err("Failed to power on V1P2SX.\n");
/* Turn all powers off if one is failed. */
intel_mid_pmic_writeb(VPROG_2P8V, VPROG_DISABLE);
return ret;
}
/* Wait for 8ms to make all the power supplies to be stable. */
usleep_range(8000, 8000);
} else {
/* Turn all powers off even when some are failed. */
if (intel_mid_pmic_writeb(VPROG_2P8V, VPROG_DISABLE))
pr_err("Failed to power off V2P8SX.\n");
if (intel_mid_pmic_writeb(VPROG_1P2V, VPROG_DISABLE))
pr_err("Failed to power off V1P2SX.\n");
}
#else
if (camera_1p2_en < 0) {
lnw_gpio_set_alt(55, LNW_GPIO);
ret = camera_sensor_gpio(55,"INT_CAM_1V2_EN", GPIOF_DIR_OUT, 0);
if (ret < 0){
printk("camera_1p2_en is not available.\n");
return ret;
}
camera_1p2_en = ret;
printk(KERN_INFO "M10MO, gpio number, camera_1p2_en is %d\n", camera_1p2_en);
}
switch (Read_HW_ID()) {
case HW_ID_EVB:
case HW_ID_SR1:
case HW_ID_SR2:
case HW_ID_ER:
case HW_ID_ER1_1:
case HW_ID_ER1_2:
case HW_ID_PR:
case HW_ID_pre_PR:
case HW_ID_MP:
if (camera_3p3_en2 < 0) {
gpio_free(58);/////// temp WA.
lnw_gpio_set_alt(58, LNW_GPIO);
ret = camera_sensor_gpio(58, "3X_I2C_LED", GPIOF_DIR_OUT, 0);
if (ret < 0){
printk("GPIO58 is not available.\n");
}else{
camera_3p3_en2 = ret;
printk(KERN_INFO "M10MO, gpio number, camera_3p3_en2 is %d\n", camera_3p3_en2);
}
}
break;
default:
if (camera_3p3_en2 < 0) {
gpio_free(54);/////// temp WA.
lnw_gpio_set_alt(54, LNW_GPIO);
ret = camera_sensor_gpio(54, "3X_I2C_LED", GPIOF_DIR_OUT, 0);
if (ret < 0){
printk("GPIO54 is not available.\n");
}else{
camera_3p3_en2 = ret;
printk(KERN_INFO "M10MO, gpio number, camera_3p3_en2 is %d\n", camera_3p3_en2);
}
}
break;
}//switch
if (camera_2p8_en < 0) {
lnw_gpio_set_alt(56, LNW_GPIO);
ret = camera_sensor_gpio(56,"INT_CAM_2V8_EN", GPIOF_DIR_OUT, 0);
if (ret < 0){
printk("camera_2p8_en not available.\n");
return ret;
}
camera_2p8_en = ret;
printk(KERN_INFO "M10MO, gpio number, camera_2p8_en is %d\n", camera_2p8_en);
}
if (flag) {
/*
static int camera_1p2_en = -1;
static int camera_2p8_en = -1;
static int camera_isp_1p2_en = -1;
*/
if(camera_1p2_en > 0){
printk("@%s %d, project zx550ml pull up GPIO%d\n", __func__, __LINE__, camera_1p2_en);
gpio_set_value(camera_1p2_en, 1);
}
#if 0
ret = intel_scu_ipc_iowrite8(MSIC_VPROG2_MRFLD_CTRL, MSIC_VPROG2_ON_1P8);
if (ret) {
pr_err("Failed to power on M10MO MSIC_VPROG2_ON_1P8.\n");
return ret;
}
#endif
if(camera_3p3_en2 > 0){
mdelay(1);
printk("@%s %d, project zx550ml pull up GPIO%d\n", __func__, __LINE__, camera_3p3_en2);
gpio_set_value(camera_3p3_en2, 1);
}
mdelay(1);
ret = intel_scu_ipc_iowrite8(MSIC_VPROG1_MRFLD_CTRL, MSIC_VPROG1_ON_1P8);
if (ret) {
pr_err("Failed to power on M10MO MSIC_VPROG1_ON_1P8.\n");
return ret;
}else{
printk("@%s %d, project zx550ml pull up Vprog1, 1.8V \n", __func__, __LINE__);
}
if(camera_2p8_en > 0){
printk("@%s %d, project zx550ml pull up GPIO%d\n", __func__, __LINE__, camera_2p8_en);
gpio_set_value(camera_2p8_en, 1);
}
/* Wait for 8ms to make all the power supplies to be stable. */
usleep_range(8000, 8000);
} else {
/*
static int camera_1p2_en = -1;
static int camera_2p8_en = -1;
static int camera_isp_1p2_en = -1;
*/
ret = intel_scu_ipc_iowrite8(MSIC_VPROG1_MRFLD_CTRL, MSIC_VPROG1_OFF);
if (ret) {
pr_err("Failed to power off M10MO MSIC_VPROG1_ON_2P8.\n");
return ret;
}
gpio_set_value(camera_2p8_en, 0);
camera_sensor_gpio_free(camera_2p8_en);
camera_2p8_en = -1;
gpio_set_value(camera_1p2_en, 0);
camera_sensor_gpio_free(camera_1p2_en);
camera_1p2_en = -1;
gpio_set_value(camera_3p3_en2, 0);
camera_sensor_gpio_free(camera_3p3_en2);
camera_3p3_en2 = -1;
camera_sensor_gpio_free(camera_reset);
camera_reset = -1;
}
#endif
return ret;
}
