void lm32_cpu_do_interrupt(CPUState *cs) { LM32CPU *cpu = LM32_CPU(cs); CPULM32State *env = &cpu->env; qemu_log_mask(CPU_LOG_INT, "exception at pc=%x type=%x\n", env->pc, env->exception_index); switch (env->exception_index) { case EXCP_INSN_BUS_ERROR: case EXCP_DATA_BUS_ERROR: case EXCP_DIVIDE_BY_ZERO: case EXCP_IRQ: case EXCP_SYSTEMCALL: /* non-debug exceptions */ env->regs[R_EA] = env->pc; env->ie |= (env->ie & IE_IE) ? IE_EIE : 0; env->ie &= ~IE_IE; if (env->dc & DC_RE) { env->pc = env->deba + (env->exception_index * 32); } else { env->pc = env->eba + (env->exception_index * 32); } log_cpu_state_mask(CPU_LOG_INT, env, 0); break; case EXCP_BREAKPOINT: case EXCP_WATCHPOINT: /* debug exceptions */ env->regs[R_BA] = env->pc; env->ie |= (env->ie & IE_IE) ? IE_BIE : 0; env->ie &= ~IE_IE; env->pc = env->deba + (env->exception_index * 32); log_cpu_state_mask(CPU_LOG_INT, env, 0); break; default: cpu_abort(env, "unhandled exception type=%d\n", env->exception_index); break; } }
void do_interrupt(CPUMBState *env) { uint32_t t; /* IMM flag cannot propagate across a branch and into the dslot. */ assert(!((env->iflags & D_FLAG) && (env->iflags & IMM_FLAG))); assert(!(env->iflags & (DRTI_FLAG | DRTE_FLAG | DRTB_FLAG))); /* assert(env->sregs[SR_MSR] & (MSR_EE)); Only for HW exceptions. */ env->res_addr = RES_ADDR_NONE; switch (env->exception_index) { case EXCP_HW_EXCP: if (!(env->pvr.regs[0] & PVR0_USE_EXC_MASK)) { qemu_log("Exception raised on system without exceptions!\n"); return; } env->regs[17] = env->sregs[SR_PC] + 4; env->sregs[SR_ESR] &= ~(1 << 12); /* Exception breaks branch + dslot sequence? */ if (env->iflags & D_FLAG) { env->sregs[SR_ESR] |= 1 << 12 ; env->sregs[SR_BTR] = env->btarget; } /* Disable the MMU. */ t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1; env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); env->sregs[SR_MSR] |= t; /* Exception in progress. */ env->sregs[SR_MSR] |= MSR_EIP; qemu_log_mask(CPU_LOG_INT, "hw exception at pc=%x ear=%x esr=%x iflags=%x\n", env->sregs[SR_PC], env->sregs[SR_EAR], env->sregs[SR_ESR], env->iflags); log_cpu_state_mask(CPU_LOG_INT, env, 0); env->iflags &= ~(IMM_FLAG | D_FLAG); env->sregs[SR_PC] = 0x20; break; case EXCP_MMU: env->regs[17] = env->sregs[SR_PC]; env->sregs[SR_ESR] &= ~(1 << 12); /* Exception breaks branch + dslot sequence? */ if (env->iflags & D_FLAG) { D(qemu_log("D_FLAG set at exception bimm=%d\n", env->bimm)); env->sregs[SR_ESR] |= 1 << 12 ; env->sregs[SR_BTR] = env->btarget; /* Reexecute the branch. */ env->regs[17] -= 4; /* was the branch immprefixed?. */ if (env->bimm) { qemu_log_mask(CPU_LOG_INT, "bimm exception at pc=%x iflags=%x\n", env->sregs[SR_PC], env->iflags); env->regs[17] -= 4; log_cpu_state_mask(CPU_LOG_INT, env, 0); } } else if (env->iflags & IMM_FLAG) { D(qemu_log("IMM_FLAG set at exception\n")); env->regs[17] -= 4; } /* Disable the MMU. */ t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1; env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); env->sregs[SR_MSR] |= t; /* Exception in progress. */ env->sregs[SR_MSR] |= MSR_EIP; qemu_log_mask(CPU_LOG_INT, "exception at pc=%x ear=%x iflags=%x\n", env->sregs[SR_PC], env->sregs[SR_EAR], env->iflags); log_cpu_state_mask(CPU_LOG_INT, env, 0); env->iflags &= ~(IMM_FLAG | D_FLAG); env->sregs[SR_PC] = 0x20; break; case EXCP_IRQ: assert(!(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP))); assert(env->sregs[SR_MSR] & MSR_IE); assert(!(env->iflags & D_FLAG)); t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1; #if 0 #include "disas.h" /* Useful instrumentation when debugging interrupt issues in either the models or in sw. */ { const char *sym; sym = lookup_symbol(env->sregs[SR_PC]); if (sym && (!strcmp("netif_rx", sym) || !strcmp("process_backlog", sym))) { qemu_log( "interrupt at pc=%x msr=%x %x iflags=%x sym=%s\n", env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags, sym); log_cpu_state(env, 0); } } #endif qemu_log_mask(CPU_LOG_INT, "interrupt at pc=%x msr=%x %x iflags=%x\n", env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags); env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM \ | MSR_UM | MSR_IE); env->sregs[SR_MSR] |= t; env->regs[14] = env->sregs[SR_PC]; env->sregs[SR_PC] = 0x10; //log_cpu_state_mask(CPU_LOG_INT, env, 0); break; case EXCP_BREAK: case EXCP_HW_BREAK: assert(!(env->iflags & IMM_FLAG)); assert(!(env->iflags & D_FLAG)); t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1; qemu_log_mask(CPU_LOG_INT, "break at pc=%x msr=%x %x iflags=%x\n", env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags); log_cpu_state_mask(CPU_LOG_INT, env, 0); env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); env->sregs[SR_MSR] |= t; env->sregs[SR_MSR] |= MSR_BIP; if (env->exception_index == EXCP_HW_BREAK) { env->regs[16] = env->sregs[SR_PC]; env->sregs[SR_MSR] |= MSR_BIP; env->sregs[SR_PC] = 0x18; } else env->sregs[SR_PC] = env->btarget; break; default: cpu_abort(env, "unhandled exception type=%d\n", env->exception_index); break; } }
void do_smm_enter(X86CPU *cpu) { CPUX86State *env = &cpu->env; CPUState *cs = CPU(cpu); target_ulong sm_state; SegmentCache *dt; int i, offset; qemu_log_mask(CPU_LOG_INT, "SMM: enter\n"); log_cpu_state_mask(CPU_LOG_INT, CPU(cpu), CPU_DUMP_CCOP); env->hflags |= HF_SMM_MASK; if (env->hflags2 & HF2_NMI_MASK) { env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK; } else { env->hflags2 |= HF2_NMI_MASK; } cpu_smm_update(cpu); sm_state = env->smbase + 0x8000; #ifdef TARGET_X86_64 for (i = 0; i < 6; i++) { dt = &env->segs[i]; offset = 0x7e00 + i * 16; x86_stw_phys(cs, sm_state + offset, dt->selector); x86_stw_phys(cs, sm_state + offset + 2, (dt->flags >> 8) & 0xf0ff); x86_stl_phys(cs, sm_state + offset + 4, dt->limit); x86_stq_phys(cs, sm_state + offset + 8, dt->base); } x86_stq_phys(cs, sm_state + 0x7e68, env->gdt.base); x86_stl_phys(cs, sm_state + 0x7e64, env->gdt.limit); x86_stw_phys(cs, sm_state + 0x7e70, env->ldt.selector); x86_stq_phys(cs, sm_state + 0x7e78, env->ldt.base); x86_stl_phys(cs, sm_state + 0x7e74, env->ldt.limit); x86_stw_phys(cs, sm_state + 0x7e72, (env->ldt.flags >> 8) & 0xf0ff); x86_stq_phys(cs, sm_state + 0x7e88, env->idt.base); x86_stl_phys(cs, sm_state + 0x7e84, env->idt.limit); x86_stw_phys(cs, sm_state + 0x7e90, env->tr.selector); x86_stq_phys(cs, sm_state + 0x7e98, env->tr.base); x86_stl_phys(cs, sm_state + 0x7e94, env->tr.limit); x86_stw_phys(cs, sm_state + 0x7e92, (env->tr.flags >> 8) & 0xf0ff); /* ??? Vol 1, 16.5.6 Intel MPX and SMM says that IA32_BNDCFGS is saved at offset 7ED0. Vol 3, 34.4.1.1, Table 32-2, has 7EA0-7ED7 as "reserved". What's this, and what's really supposed to happen? */ x86_stq_phys(cs, sm_state + 0x7ed0, env->efer); x86_stq_phys(cs, sm_state + 0x7ff8, env->regs[R_EAX]); x86_stq_phys(cs, sm_state + 0x7ff0, env->regs[R_ECX]); x86_stq_phys(cs, sm_state + 0x7fe8, env->regs[R_EDX]); x86_stq_phys(cs, sm_state + 0x7fe0, env->regs[R_EBX]); x86_stq_phys(cs, sm_state + 0x7fd8, env->regs[R_ESP]); x86_stq_phys(cs, sm_state + 0x7fd0, env->regs[R_EBP]); x86_stq_phys(cs, sm_state + 0x7fc8, env->regs[R_ESI]); x86_stq_phys(cs, sm_state + 0x7fc0, env->regs[R_EDI]); for (i = 8; i < 16; i++) { x86_stq_phys(cs, sm_state + 0x7ff8 - i * 8, env->regs[i]); } x86_stq_phys(cs, sm_state + 0x7f78, env->eip); x86_stl_phys(cs, sm_state + 0x7f70, cpu_compute_eflags(env)); x86_stl_phys(cs, sm_state + 0x7f68, env->dr[6]); x86_stl_phys(cs, sm_state + 0x7f60, env->dr[7]); x86_stl_phys(cs, sm_state + 0x7f48, env->cr[4]); x86_stq_phys(cs, sm_state + 0x7f50, env->cr[3]); x86_stl_phys(cs, sm_state + 0x7f58, env->cr[0]); x86_stl_phys(cs, sm_state + 0x7efc, SMM_REVISION_ID); x86_stl_phys(cs, sm_state + 0x7f00, env->smbase); #else x86_stl_phys(cs, sm_state + 0x7ffc, env->cr[0]); x86_stl_phys(cs, sm_state + 0x7ff8, env->cr[3]); x86_stl_phys(cs, sm_state + 0x7ff4, cpu_compute_eflags(env)); x86_stl_phys(cs, sm_state + 0x7ff0, env->eip); x86_stl_phys(cs, sm_state + 0x7fec, env->regs[R_EDI]); x86_stl_phys(cs, sm_state + 0x7fe8, env->regs[R_ESI]); x86_stl_phys(cs, sm_state + 0x7fe4, env->regs[R_EBP]); x86_stl_phys(cs, sm_state + 0x7fe0, env->regs[R_ESP]); x86_stl_phys(cs, sm_state + 0x7fdc, env->regs[R_EBX]); x86_stl_phys(cs, sm_state + 0x7fd8, env->regs[R_EDX]); x86_stl_phys(cs, sm_state + 0x7fd4, env->regs[R_ECX]); x86_stl_phys(cs, sm_state + 0x7fd0, env->regs[R_EAX]); x86_stl_phys(cs, sm_state + 0x7fcc, env->dr[6]); x86_stl_phys(cs, sm_state + 0x7fc8, env->dr[7]); x86_stl_phys(cs, sm_state + 0x7fc4, env->tr.selector); x86_stl_phys(cs, sm_state + 0x7f64, env->tr.base); x86_stl_phys(cs, sm_state + 0x7f60, env->tr.limit); x86_stl_phys(cs, sm_state + 0x7f5c, (env->tr.flags >> 8) & 0xf0ff); x86_stl_phys(cs, sm_state + 0x7fc0, env->ldt.selector); x86_stl_phys(cs, sm_state + 0x7f80, env->ldt.base); x86_stl_phys(cs, sm_state + 0x7f7c, env->ldt.limit); x86_stl_phys(cs, sm_state + 0x7f78, (env->ldt.flags >> 8) & 0xf0ff); x86_stl_phys(cs, sm_state + 0x7f74, env->gdt.base); x86_stl_phys(cs, sm_state + 0x7f70, env->gdt.limit); x86_stl_phys(cs, sm_state + 0x7f58, env->idt.base); x86_stl_phys(cs, sm_state + 0x7f54, env->idt.limit); for (i = 0; i < 6; i++) { dt = &env->segs[i]; if (i < 3) { offset = 0x7f84 + i * 12; } else { offset = 0x7f2c + (i - 3) * 12; } x86_stl_phys(cs, sm_state + 0x7fa8 + i * 4, dt->selector); x86_stl_phys(cs, sm_state + offset + 8, dt->base); x86_stl_phys(cs, sm_state + offset + 4, dt->limit); x86_stl_phys(cs, sm_state + offset, (dt->flags >> 8) & 0xf0ff); } x86_stl_phys(cs, sm_state + 0x7f14, env->cr[4]); x86_stl_phys(cs, sm_state + 0x7efc, SMM_REVISION_ID); x86_stl_phys(cs, sm_state + 0x7ef8, env->smbase); #endif /* init SMM cpu state */ #ifdef TARGET_X86_64 cpu_load_efer(env, 0); #endif cpu_load_eflags(env, 0, ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK)); env->eip = 0x00008000; cpu_x86_update_cr0(env, env->cr[0] & ~(CR0_PE_MASK | CR0_EM_MASK | CR0_TS_MASK | CR0_PG_MASK)); cpu_x86_update_cr4(env, 0); env->dr[7] = 0x00000400; cpu_x86_load_seg_cache(env, R_CS, (env->smbase >> 4) & 0xffff, env->smbase, 0xffffffff, DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | DESC_G_MASK | DESC_A_MASK); cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffffffff, DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | DESC_G_MASK | DESC_A_MASK); cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffffffff, DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | DESC_G_MASK | DESC_A_MASK); cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffffffff, DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | DESC_G_MASK | DESC_A_MASK); cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffffffff, DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | DESC_G_MASK | DESC_A_MASK); cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffffffff, DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | DESC_G_MASK | DESC_A_MASK); }
void helper_rsm(CPUX86State *env) { X86CPU *cpu = x86_env_get_cpu(env); CPUState *cs = CPU(cpu); target_ulong sm_state; int i, offset; uint32_t val; sm_state = env->smbase + 0x8000; #ifdef TARGET_X86_64 cpu_load_efer(env, x86_ldq_phys(cs, sm_state + 0x7ed0)); env->gdt.base = x86_ldq_phys(cs, sm_state + 0x7e68); env->gdt.limit = x86_ldl_phys(cs, sm_state + 0x7e64); env->ldt.selector = x86_lduw_phys(cs, sm_state + 0x7e70); env->ldt.base = x86_ldq_phys(cs, sm_state + 0x7e78); env->ldt.limit = x86_ldl_phys(cs, sm_state + 0x7e74); env->ldt.flags = (x86_lduw_phys(cs, sm_state + 0x7e72) & 0xf0ff) << 8; env->idt.base = x86_ldq_phys(cs, sm_state + 0x7e88); env->idt.limit = x86_ldl_phys(cs, sm_state + 0x7e84); env->tr.selector = x86_lduw_phys(cs, sm_state + 0x7e90); env->tr.base = x86_ldq_phys(cs, sm_state + 0x7e98); env->tr.limit = x86_ldl_phys(cs, sm_state + 0x7e94); env->tr.flags = (x86_lduw_phys(cs, sm_state + 0x7e92) & 0xf0ff) << 8; env->regs[R_EAX] = x86_ldq_phys(cs, sm_state + 0x7ff8); env->regs[R_ECX] = x86_ldq_phys(cs, sm_state + 0x7ff0); env->regs[R_EDX] = x86_ldq_phys(cs, sm_state + 0x7fe8); env->regs[R_EBX] = x86_ldq_phys(cs, sm_state + 0x7fe0); env->regs[R_ESP] = x86_ldq_phys(cs, sm_state + 0x7fd8); env->regs[R_EBP] = x86_ldq_phys(cs, sm_state + 0x7fd0); env->regs[R_ESI] = x86_ldq_phys(cs, sm_state + 0x7fc8); env->regs[R_EDI] = x86_ldq_phys(cs, sm_state + 0x7fc0); for (i = 8; i < 16; i++) { env->regs[i] = x86_ldq_phys(cs, sm_state + 0x7ff8 - i * 8); } env->eip = x86_ldq_phys(cs, sm_state + 0x7f78); cpu_load_eflags(env, x86_ldl_phys(cs, sm_state + 0x7f70), ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK)); env->dr[6] = x86_ldl_phys(cs, sm_state + 0x7f68); env->dr[7] = x86_ldl_phys(cs, sm_state + 0x7f60); cpu_x86_update_cr4(env, x86_ldl_phys(cs, sm_state + 0x7f48)); cpu_x86_update_cr3(env, x86_ldq_phys(cs, sm_state + 0x7f50)); cpu_x86_update_cr0(env, x86_ldl_phys(cs, sm_state + 0x7f58)); for (i = 0; i < 6; i++) { offset = 0x7e00 + i * 16; cpu_x86_load_seg_cache(env, i, x86_lduw_phys(cs, sm_state + offset), x86_ldq_phys(cs, sm_state + offset + 8), x86_ldl_phys(cs, sm_state + offset + 4), (x86_lduw_phys(cs, sm_state + offset + 2) & 0xf0ff) << 8); } val = x86_ldl_phys(cs, sm_state + 0x7efc); /* revision ID */ if (val & 0x20000) { env->smbase = x86_ldl_phys(cs, sm_state + 0x7f00); } #else cpu_x86_update_cr0(env, x86_ldl_phys(cs, sm_state + 0x7ffc)); cpu_x86_update_cr3(env, x86_ldl_phys(cs, sm_state + 0x7ff8)); cpu_load_eflags(env, x86_ldl_phys(cs, sm_state + 0x7ff4), ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK)); env->eip = x86_ldl_phys(cs, sm_state + 0x7ff0); env->regs[R_EDI] = x86_ldl_phys(cs, sm_state + 0x7fec); env->regs[R_ESI] = x86_ldl_phys(cs, sm_state + 0x7fe8); env->regs[R_EBP] = x86_ldl_phys(cs, sm_state + 0x7fe4); env->regs[R_ESP] = x86_ldl_phys(cs, sm_state + 0x7fe0); env->regs[R_EBX] = x86_ldl_phys(cs, sm_state + 0x7fdc); env->regs[R_EDX] = x86_ldl_phys(cs, sm_state + 0x7fd8); env->regs[R_ECX] = x86_ldl_phys(cs, sm_state + 0x7fd4); env->regs[R_EAX] = x86_ldl_phys(cs, sm_state + 0x7fd0); env->dr[6] = x86_ldl_phys(cs, sm_state + 0x7fcc); env->dr[7] = x86_ldl_phys(cs, sm_state + 0x7fc8); env->tr.selector = x86_ldl_phys(cs, sm_state + 0x7fc4) & 0xffff; env->tr.base = x86_ldl_phys(cs, sm_state + 0x7f64); env->tr.limit = x86_ldl_phys(cs, sm_state + 0x7f60); env->tr.flags = (x86_ldl_phys(cs, sm_state + 0x7f5c) & 0xf0ff) << 8; env->ldt.selector = x86_ldl_phys(cs, sm_state + 0x7fc0) & 0xffff; env->ldt.base = x86_ldl_phys(cs, sm_state + 0x7f80); env->ldt.limit = x86_ldl_phys(cs, sm_state + 0x7f7c); env->ldt.flags = (x86_ldl_phys(cs, sm_state + 0x7f78) & 0xf0ff) << 8; env->gdt.base = x86_ldl_phys(cs, sm_state + 0x7f74); env->gdt.limit = x86_ldl_phys(cs, sm_state + 0x7f70); env->idt.base = x86_ldl_phys(cs, sm_state + 0x7f58); env->idt.limit = x86_ldl_phys(cs, sm_state + 0x7f54); for (i = 0; i < 6; i++) { if (i < 3) { offset = 0x7f84 + i * 12; } else { offset = 0x7f2c + (i - 3) * 12; } cpu_x86_load_seg_cache(env, i, x86_ldl_phys(cs, sm_state + 0x7fa8 + i * 4) & 0xffff, x86_ldl_phys(cs, sm_state + offset + 8), x86_ldl_phys(cs, sm_state + offset + 4), (x86_ldl_phys(cs, sm_state + offset) & 0xf0ff) << 8); } cpu_x86_update_cr4(env, x86_ldl_phys(cs, sm_state + 0x7f14)); val = x86_ldl_phys(cs, sm_state + 0x7efc); /* revision ID */ if (val & 0x20000) { env->smbase = x86_ldl_phys(cs, sm_state + 0x7ef8); } #endif if ((env->hflags2 & HF2_SMM_INSIDE_NMI_MASK) == 0) { env->hflags2 &= ~HF2_NMI_MASK; } env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK; env->hflags &= ~HF_SMM_MASK; cpu_smm_update(cpu); qemu_log_mask(CPU_LOG_INT, "SMM: after RSM\n"); log_cpu_state_mask(CPU_LOG_INT, CPU(cpu), CPU_DUMP_CCOP); }
void do_smm_enter(X86CPU *cpu) { CPUX86State *env = &cpu->env; CPUState *cs = CPU(cpu); target_ulong sm_state; SegmentCache *dt; int i, offset; qemu_log_mask(CPU_LOG_INT, "SMM: enter\n"); log_cpu_state_mask(CPU_LOG_INT, CPU(cpu), CPU_DUMP_CCOP); env->hflags |= HF_SMM_MASK; cpu_smm_update(env); sm_state = env->smbase + 0x8000; #ifdef TARGET_X86_64 for (i = 0; i < 6; i++) { dt = &env->segs[i]; offset = 0x7e00 + i * 16; stw_phys(cs->as, sm_state + offset, dt->selector); stw_phys(cs->as, sm_state + offset + 2, (dt->flags >> 8) & 0xf0ff); stl_phys(cs->as, sm_state + offset + 4, dt->limit); stq_phys(cs->as, sm_state + offset + 8, dt->base); } stq_phys(cs->as, sm_state + 0x7e68, env->gdt.base); stl_phys(cs->as, sm_state + 0x7e64, env->gdt.limit); stw_phys(cs->as, sm_state + 0x7e70, env->ldt.selector); stq_phys(cs->as, sm_state + 0x7e78, env->ldt.base); stl_phys(cs->as, sm_state + 0x7e74, env->ldt.limit); stw_phys(cs->as, sm_state + 0x7e72, (env->ldt.flags >> 8) & 0xf0ff); stq_phys(cs->as, sm_state + 0x7e88, env->idt.base); stl_phys(cs->as, sm_state + 0x7e84, env->idt.limit); stw_phys(cs->as, sm_state + 0x7e90, env->tr.selector); stq_phys(cs->as, sm_state + 0x7e98, env->tr.base); stl_phys(cs->as, sm_state + 0x7e94, env->tr.limit); stw_phys(cs->as, sm_state + 0x7e92, (env->tr.flags >> 8) & 0xf0ff); stq_phys(cs->as, sm_state + 0x7ed0, env->efer); stq_phys(cs->as, sm_state + 0x7ff8, env->regs[R_EAX]); stq_phys(cs->as, sm_state + 0x7ff0, env->regs[R_ECX]); stq_phys(cs->as, sm_state + 0x7fe8, env->regs[R_EDX]); stq_phys(cs->as, sm_state + 0x7fe0, env->regs[R_EBX]); stq_phys(cs->as, sm_state + 0x7fd8, env->regs[R_ESP]); stq_phys(cs->as, sm_state + 0x7fd0, env->regs[R_EBP]); stq_phys(cs->as, sm_state + 0x7fc8, env->regs[R_ESI]); stq_phys(cs->as, sm_state + 0x7fc0, env->regs[R_EDI]); for (i = 8; i < 16; i++) { stq_phys(cs->as, sm_state + 0x7ff8 - i * 8, env->regs[i]); } stq_phys(cs->as, sm_state + 0x7f78, env->eip); stl_phys(cs->as, sm_state + 0x7f70, cpu_compute_eflags(env)); stl_phys(cs->as, sm_state + 0x7f68, env->dr[6]); stl_phys(cs->as, sm_state + 0x7f60, env->dr[7]); stl_phys(cs->as, sm_state + 0x7f48, env->cr[4]); stl_phys(cs->as, sm_state + 0x7f50, env->cr[3]); stl_phys(cs->as, sm_state + 0x7f58, env->cr[0]); stl_phys(cs->as, sm_state + 0x7efc, SMM_REVISION_ID); stl_phys(cs->as, sm_state + 0x7f00, env->smbase); #else stl_phys(cs->as, sm_state + 0x7ffc, env->cr[0]); stl_phys(cs->as, sm_state + 0x7ff8, env->cr[3]); stl_phys(cs->as, sm_state + 0x7ff4, cpu_compute_eflags(env)); stl_phys(cs->as, sm_state + 0x7ff0, env->eip); stl_phys(cs->as, sm_state + 0x7fec, env->regs[R_EDI]); stl_phys(cs->as, sm_state + 0x7fe8, env->regs[R_ESI]); stl_phys(cs->as, sm_state + 0x7fe4, env->regs[R_EBP]); stl_phys(cs->as, sm_state + 0x7fe0, env->regs[R_ESP]); stl_phys(cs->as, sm_state + 0x7fdc, env->regs[R_EBX]); stl_phys(cs->as, sm_state + 0x7fd8, env->regs[R_EDX]); stl_phys(cs->as, sm_state + 0x7fd4, env->regs[R_ECX]); stl_phys(cs->as, sm_state + 0x7fd0, env->regs[R_EAX]); stl_phys(cs->as, sm_state + 0x7fcc, env->dr[6]); stl_phys(cs->as, sm_state + 0x7fc8, env->dr[7]); stl_phys(cs->as, sm_state + 0x7fc4, env->tr.selector); stl_phys(cs->as, sm_state + 0x7f64, env->tr.base); stl_phys(cs->as, sm_state + 0x7f60, env->tr.limit); stl_phys(cs->as, sm_state + 0x7f5c, (env->tr.flags >> 8) & 0xf0ff); stl_phys(cs->as, sm_state + 0x7fc0, env->ldt.selector); stl_phys(cs->as, sm_state + 0x7f80, env->ldt.base); stl_phys(cs->as, sm_state + 0x7f7c, env->ldt.limit); stl_phys(cs->as, sm_state + 0x7f78, (env->ldt.flags >> 8) & 0xf0ff); stl_phys(cs->as, sm_state + 0x7f74, env->gdt.base); stl_phys(cs->as, sm_state + 0x7f70, env->gdt.limit); stl_phys(cs->as, sm_state + 0x7f58, env->idt.base); stl_phys(cs->as, sm_state + 0x7f54, env->idt.limit); for (i = 0; i < 6; i++) { dt = &env->segs[i]; if (i < 3) { offset = 0x7f84 + i * 12; } else { offset = 0x7f2c + (i - 3) * 12; } stl_phys(cs->as, sm_state + 0x7fa8 + i * 4, dt->selector); stl_phys(cs->as, sm_state + offset + 8, dt->base); stl_phys(cs->as, sm_state + offset + 4, dt->limit); stl_phys(cs->as, sm_state + offset, (dt->flags >> 8) & 0xf0ff); } stl_phys(cs->as, sm_state + 0x7f14, env->cr[4]); stl_phys(cs->as, sm_state + 0x7efc, SMM_REVISION_ID); stl_phys(cs->as, sm_state + 0x7ef8, env->smbase); #endif /* init SMM cpu state */ #ifdef TARGET_X86_64 cpu_load_efer(env, 0); #endif cpu_load_eflags(env, 0, ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK)); env->eip = 0x00008000; cpu_x86_update_cr0(env, env->cr[0] & ~(CR0_PE_MASK | CR0_EM_MASK | CR0_TS_MASK | CR0_PG_MASK)); cpu_x86_update_cr4(env, 0); env->dr[7] = 0x00000400; cpu_x86_load_seg_cache(env, R_CS, (env->smbase >> 4) & 0xffff, env->smbase, 0xffffffff, DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | DESC_A_MASK); cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffffffff, DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | DESC_A_MASK); cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffffffff, DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | DESC_A_MASK); cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffffffff, DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | DESC_A_MASK); cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffffffff, DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | DESC_A_MASK); cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffffffff, DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | DESC_A_MASK); }
void helper_rsm(CPUX86State *env) { target_ulong sm_state; int i, offset; uint32_t val; sm_state = env->smbase + 0x8000; #ifdef TARGET_X86_64 cpu_load_efer(env, ldq_phys(sm_state + 0x7ed0)); for(i = 0; i < 6; i++) { offset = 0x7e00 + i * 16; cpu_x86_load_seg_cache(env, i, lduw_phys(sm_state + offset), ldq_phys(sm_state + offset + 8), ldl_phys(sm_state + offset + 4), (lduw_phys(sm_state + offset + 2) & 0xf0ff) << 8); } env->gdt.base = ldq_phys(sm_state + 0x7e68); env->gdt.limit = ldl_phys(sm_state + 0x7e64); env->ldt.selector = lduw_phys(sm_state + 0x7e70); env->ldt.base = ldq_phys(sm_state + 0x7e78); env->ldt.limit = ldl_phys(sm_state + 0x7e74); env->ldt.flags = (lduw_phys(sm_state + 0x7e72) & 0xf0ff) << 8; env->idt.base = ldq_phys(sm_state + 0x7e88); env->idt.limit = ldl_phys(sm_state + 0x7e84); env->tr.selector = lduw_phys(sm_state + 0x7e90); env->tr.base = ldq_phys(sm_state + 0x7e98); env->tr.limit = ldl_phys(sm_state + 0x7e94); env->tr.flags = (lduw_phys(sm_state + 0x7e92) & 0xf0ff) << 8; EAX = ldq_phys(sm_state + 0x7ff8); ECX = ldq_phys(sm_state + 0x7ff0); EDX = ldq_phys(sm_state + 0x7fe8); EBX = ldq_phys(sm_state + 0x7fe0); ESP = ldq_phys(sm_state + 0x7fd8); EBP = ldq_phys(sm_state + 0x7fd0); ESI = ldq_phys(sm_state + 0x7fc8); EDI = ldq_phys(sm_state + 0x7fc0); for(i = 8; i < 16; i++) env->regs[i] = ldq_phys(sm_state + 0x7ff8 - i * 8); env->eip = ldq_phys(sm_state + 0x7f78); cpu_load_eflags(env, ldl_phys(sm_state + 0x7f70), ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK)); env->dr[6] = ldl_phys(sm_state + 0x7f68); env->dr[7] = ldl_phys(sm_state + 0x7f60); cpu_x86_update_cr4(env, ldl_phys(sm_state + 0x7f48)); cpu_x86_update_cr3(env, ldl_phys(sm_state + 0x7f50)); cpu_x86_update_cr0(env, ldl_phys(sm_state + 0x7f58)); val = ldl_phys(sm_state + 0x7efc); /* revision ID */ if (val & 0x20000) { env->smbase = ldl_phys(sm_state + 0x7f00) & ~0x7fff; } #else cpu_x86_update_cr0(env, ldl_phys(sm_state + 0x7ffc)); cpu_x86_update_cr3(env, ldl_phys(sm_state + 0x7ff8)); cpu_load_eflags(env, ldl_phys(sm_state + 0x7ff4), ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK)); env->eip = ldl_phys(sm_state + 0x7ff0); EDI = ldl_phys(sm_state + 0x7fec); ESI = ldl_phys(sm_state + 0x7fe8); EBP = ldl_phys(sm_state + 0x7fe4); ESP = ldl_phys(sm_state + 0x7fe0); EBX = ldl_phys(sm_state + 0x7fdc); EDX = ldl_phys(sm_state + 0x7fd8); ECX = ldl_phys(sm_state + 0x7fd4); EAX = ldl_phys(sm_state + 0x7fd0); env->dr[6] = ldl_phys(sm_state + 0x7fcc); env->dr[7] = ldl_phys(sm_state + 0x7fc8); env->tr.selector = ldl_phys(sm_state + 0x7fc4) & 0xffff; env->tr.base = ldl_phys(sm_state + 0x7f64); env->tr.limit = ldl_phys(sm_state + 0x7f60); env->tr.flags = (ldl_phys(sm_state + 0x7f5c) & 0xf0ff) << 8; env->ldt.selector = ldl_phys(sm_state + 0x7fc0) & 0xffff; env->ldt.base = ldl_phys(sm_state + 0x7f80); env->ldt.limit = ldl_phys(sm_state + 0x7f7c); env->ldt.flags = (ldl_phys(sm_state + 0x7f78) & 0xf0ff) << 8; env->gdt.base = ldl_phys(sm_state + 0x7f74); env->gdt.limit = ldl_phys(sm_state + 0x7f70); env->idt.base = ldl_phys(sm_state + 0x7f58); env->idt.limit = ldl_phys(sm_state + 0x7f54); for(i = 0; i < 6; i++) { if (i < 3) offset = 0x7f84 + i * 12; else offset = 0x7f2c + (i - 3) * 12; cpu_x86_load_seg_cache(env, i, ldl_phys(sm_state + 0x7fa8 + i * 4) & 0xffff, ldl_phys(sm_state + offset + 8), ldl_phys(sm_state + offset + 4), (ldl_phys(sm_state + offset) & 0xf0ff) << 8); } cpu_x86_update_cr4(env, ldl_phys(sm_state + 0x7f14)); val = ldl_phys(sm_state + 0x7efc); /* revision ID */ if (val & 0x20000) { env->smbase = ldl_phys(sm_state + 0x7ef8) & ~0x7fff; } #endif CC_OP = CC_OP_EFLAGS; env->hflags &= ~HF_SMM_MASK; cpu_smm_update(env); qemu_log_mask(CPU_LOG_INT, "SMM: after RSM\n"); log_cpu_state_mask(CPU_LOG_INT, ENV_GET_CPU(env), X86_DUMP_CCOP); }