static int lpc17_configalternate(lpc17_pinset_t cfgset, unsigned int port,
unsigned int pin, uint32_t alt)
{
/* First, configure the port as an input so that we have a known
* starting point and consistent behavior during the re-configuration.
*/
(void)lpc17_configinput(DEFAULT_INPUT, port, pin);
/* Set up PINSEL registers */
/* Configure as GPIO */
lpc17_pinsel(port, pin, alt);
/* Set pull-up mode */
lpc17_pullup(cfgset, port, pin);
/* Check for open drain output */
if ((cfgset & GPIO_OPEN_DRAIN) != 0)
{
/* Select open drain output */
lpc17_setopendrain(port, pin);
}
return OK;
}
int lpc17_dumpgpio(lpc17_pinset_t pinset, const char *msg)
{
irqstate_t flags;
uint32_t base;
#if defined(LPC176x)
uint32_t pinsel;
uint32_t pinmode;
#elif defined(LPC178x)
uint32_t iocon;
#endif /* LPC176x */
unsigned int port;
unsigned int pin;
/* Get the base address associated with the GPIO port */
port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
#if defined(LPC176x)
pinsel = lpc17_pinsel(port, pin);
pinmode = lpc17_pinmode(port, pin);
#elif defined(LPC178x)
iocon = LPC17_IOCON_P(port, pin);
#endif /* LPC176x */
/* The following requires exclusive access to the GPIO registers */
flags = enter_critical_section();
gpioinfo("GPIO%c pin%d (pinset: %08x) -- %s\n",
port + '0', pin, pinset, msg);
#if defined(LPC176x)
gpioinfo(" PINSEL[%08x]: %08x PINMODE[%08x]: %08x ODMODE[%08x]: %08x\n",
pinsel, pinsel ? getreg32(pinsel) : 0,
pinmode, pinmode ? getreg32(pinmode) : 0,
g_odmode[port], getreg32(g_odmode[port]));
#elif defined(LPC178x)
gpioinfo(" IOCON[%08x]: %08x\n", iocon, getreg32(iocon));
#endif
base = g_fiobase[port];
gpioinfo(" FIODIR[%08x]: %08x FIOMASK[%08x]: %08x FIOPIN[%08x]: %08x\n",
base+LPC17_FIO_DIR_OFFSET, getreg32(base+LPC17_FIO_DIR_OFFSET),
base+LPC17_FIO_MASK_OFFSET, getreg32(base+LPC17_FIO_MASK_OFFSET),
base+LPC17_FIO_PIN_OFFSET, getreg32(base+LPC17_FIO_PIN_OFFSET));
base = g_intbase[port];
gpioinfo(" IOINTSTATUS[%08x]: %08x INTSTATR[%08x]: %08x INSTATF[%08x]: %08x\n",
LPC17_GPIOINT_IOINTSTATUS, getreg32(LPC17_GPIOINT_IOINTSTATUS),
base+LPC17_GPIOINT_INTSTATR_OFFSET, getreg32(base+LPC17_GPIOINT_INTSTATR_OFFSET),
base+LPC17_GPIOINT_INTSTATF_OFFSET, getreg32(base+LPC17_GPIOINT_INTSTATF_OFFSET));
gpioinfo(" INTENR[%08x]: %08x INTENF[%08x]: %08x\n",
base+LPC17_GPIOINT_INTENR_OFFSET, getreg32(base+LPC17_GPIOINT_INTENR_OFFSET),
base+LPC17_GPIOINT_INTENF_OFFSET, getreg32(base+LPC17_GPIOINT_INTENF_OFFSET));
leave_critical_section(flags);
return OK;
}
static inline int lpc17_configinput(lpc17_pinset_t cfgset, unsigned int port, unsigned int pin)
{
uint32_t regval;
uint32_t fiobase;
uint32_t intbase;
uint32_t pinmask = (1 << pin);
/* Set up FIO registers */
fiobase = g_fiobase[port];
/* Set as input */
regval = getreg32(fiobase + LPC17_FIO_DIR_OFFSET);
regval &= ~pinmask;
putreg32(regval, fiobase + LPC17_FIO_DIR_OFFSET);
/* Set up interrupt registers */
intbase = g_intbase[port];
if (intbase != 0)
{
/* Disable any rising edge interrupts */
regval = getreg32(intbase + LPC17_GPIOINT_INTENR_OFFSET);
regval &= ~pinmask;
putreg32(regval, intbase + LPC17_GPIOINT_INTENR_OFFSET);
/* Disable any falling edge interrupts */
regval = getreg32(intbase + LPC17_GPIOINT_INTENF_OFFSET);
regval &= ~pinmask;
putreg32(regval, intbase + LPC17_GPIOINT_INTENF_OFFSET);
/* Forget about any falling/rising edge interrupt enabled */
#ifdef CONFIG_GPIO_IRQ
lpc17_setintedge(port, pin, 0);
#endif
}
/* Set up PINSEL registers */
/* Configure as GPIO */
lpc17_pinsel(port, pin, PINCONN_PINSEL_GPIO);
/* Set pull-up mode */
lpc17_pullup(cfgset, port, pin);
/* Open drain only applies to outputs */
lpc17_clropendrain(port, pin);
return OK;
}
int lpc17_dumpgpio(uint16_t pinset, const char *msg)
{
irqstate_t flags;
uint32_t base;
uint32_t pinsel;
uint32_t pinmode;
unsigned int port;
unsigned int pin;
/* Get the base address associated with the GPIO port */
port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
pinsel = lpc17_pinsel(port, pin);
pinmode = lpc17_pinmode(port, pin);
/* The following requires exclusive access to the GPIO registers */
flags = irqsave();
lldbg("GPIO%c pinset: %08x -- %s\n",
port + '0', pinset, msg);
lldbg(" PINSEL[%08x]: %08x PINMODE[%08x]: %08x ODMODE[%08x]: %08x\n",
pinsel, pinsel ? getreg32(pinsel) : 0,
pinmode, pinmode ? getreg32(pinmode) : 0,
g_odmode[port], getreg32(g_odmode[port]));
base = g_fiobase[port];
lldbg(" FIODIR[%08x]: %08x FIOMASK[%08x]: %08x FIOPIN[%08x]: %08x\n",
base+LPC17_FIO_DIR_OFFSET, getreg32(base+LPC17_FIO_DIR_OFFSET),
base+LPC17_FIO_MASK_OFFSET, getreg32(base+LPC17_FIO_MASK_OFFSET),
base+LPC17_FIO_PIN_OFFSET, getreg32(base+LPC17_FIO_PIN_OFFSET));
base = g_intbase[port];
lldbg(" IOINTSTATUS[%08x]: %08x INTSTATR[%08x]: %08x INSTATF[%08x]: %08x\n",
LPC17_GPIOINT_IOINTSTATUS, getreg32(LPC17_GPIOINT_IOINTSTATUS),
base+LPC17_GPIOINT_INTSTATR_OFFSET, getreg32(base+LPC17_GPIOINT_INTSTATR_OFFSET),
base+LPC17_GPIOINT_INTSTATF_OFFSET, getreg32(base+LPC17_GPIOINT_INTSTATF_OFFSET));
lldbg(" INTENR[%08x]: %08x INTENF[%08x]: %08x\n",
base+LPC17_GPIOINT_INTENR_OFFSET, getreg32(base+LPC17_GPIOINT_INTENR_OFFSET),
base+LPC17_GPIOINT_INTENF_OFFSET, getreg32(base+LPC17_GPIOINT_INTENF_OFFSET));
irqrestore(flags);
return OK;
}
