void i2c_set_baud_rate(uint8_t i2c_interface, uint32_t baud_rate)
{
uint32_t pclksel = 0;
uint32_t prescale = 0;
lpc2387_pclk_scale(CLOCK_CORECLOCK, baud_rate, &pclksel, &prescale);
switch (i2c_interface) {
case I2C0:
PCLKSEL0 &= ~(BIT14 | BIT15); //clear Bits
PCLKSEL0 |= pclksel << 14; //set bits
I20SCLL = prescale / 2;
I20SCLH = prescale / 2;
break;
case I2C1_0:
case I2C1_1:
PCLKSEL1 &= ~(BIT6 | BIT7);
PCLKSEL1 |= pclksel << 6;
I21SCLL = prescale / 2;
I21SCLH = prescale / 2;
break;
case I2C2:
PCLKSEL1 &= ~(BIT20 | BIT21);
PCLKSEL1 |= pclksel << 20;
I22SCLL = prescale / 2;
I22SCLH = prescale / 2;
}
}
void cpu_clock_scale(uint32_t source, uint32_t target, uint32_t* prescale) {
uint32_t pclksel;
lpc2387_pclk_scale(source, target, &pclksel, prescale);
PCLKSEL0 = (PCLKSEL0 & ~(BIT2|BIT3)) | (pclksel << 2); // timer 0
PCLKSEL0 = (PCLKSEL0 & ~(BIT4|BIT5)) | (pclksel << 4); // timer 1
PCLKSEL1 = (PCLKSEL1 & ~(BIT12|BIT13)) | (pclksel << 12); // timer 2
}
void cc110x_spi_init(void)
{
// configure chip-select
FIO0DIR |= BIT6;
FIO0SET = BIT6;
// Power
PCONP |= PCSSP1; // Enable power for SSP1 (default is on)
// PIN Setup
PINSEL0 |= BIT15; // Set CLK function to SSP1
PINSEL0 &= ~BIT14;
PINSEL0 |= BIT17 ; // Set MISO function to SSP1
PINSEL0 &= ~BIT16;
PINSEL0 |= BIT19; // Set MOSI function to SSP1
PINSEL0 &= ~BIT18;
// Interface Setup
SSP1CR0 = 7;
// Clock Setup
uint32_t pclksel;
uint32_t cpsr;
lpc2387_pclk_scale(F_CPU / 1000, 6000, &pclksel, &cpsr);
PCLKSEL0 &= ~(BIT21 | BIT20); // CCLK to PCLK divider
PCLKSEL0 |= pclksel << 20;
SSP1CPSR = cpsr;
// Enable
SSP1CR1 |= BIT1; // SSP-Enable
int dummy;
// Clear RxFIFO:
while (SPI_RX_AVAIL) { // while RNE (Receive FIFO Not Empty)...
dummy = SSP1DR; // read data
}
/* to suppress unused-but-set-variable */
(void) dummy;
}
/*
* datasize (wordsize) in decimal (4-16), cpol&cpha =(0/1) and frequency divided
* by 1000 (e.g. 8 MHz = 8000)
*/
uint8_t SSP0Prepare(uint8_t chip, uint8_t datasize, uint8_t cpol, uint8_t cpha,
uint16_t freq)
{
switch (chip) {
case BMA180_INTERN:
case SMB380_ACC: {
#if USE_CS
PINSEL3 |= BIT8 | BIT9 | BIT10 | BIT11 | BIT14 | BIT15 | BIT16 |
BIT17; //P1.20 1.21 1.23 1.24
#else
// 1.20 1.23 1.24 are not configured as SSEL0
PINSEL3 |= BIT8 | BIT9 | BIT14 | BIT15 | BIT16 | BIT17;
#endif
break;
}
case BMA180_EXTERN:
case L3G_EXTERN:
case NANOPAN:
case ACAMDMS: {
#if USE_CS
PINSEL0 |= BIT31;
PINSEL1 |= BIT1 | BIT3 | BIT5; // P0.15 0.16 0.17 0.18
#else
// Turn on NanoPAN
PINSEL0 |= BIT31;
// 0.15 0.17 0.18 are not configured as SSEL0
PINSEL1 |= BIT3 | BIT5;
#endif
break;
}
case NORDIC: {
PINSEL0 |= BIT31;
PINSEL1 |= BIT3 | BIT5; // 0.15 0.17 0.18 SSEL0 (No)
break;
}
default: {
printf("wrong CHIP selected\n");
return 0;
}
}
uint32_t SSP0CR0tmp = 0;
switch (datasize) {
case 4:
SSP0CR0tmp = BIT0 | BIT1;
break;
case 5:
SSP0CR0tmp = BIT2;
break;
case 6:
SSP0CR0tmp = BIT0 | BIT2;
break;
case 7:
SSP0CR0tmp = BIT1 | BIT2;
break;
case 8:
SSP0CR0tmp = BIT0 | BIT1 | BIT2;
break;
case 9:
SSP0CR0tmp = BIT3;
break;
case 10:
SSP0CR0tmp = BIT0 | BIT3;
break;
case 11:
SSP0CR0tmp = BIT1 | BIT3;
break;
case 12:
SSP0CR0tmp = BIT0 | BIT1 | BIT3;
break;
case 13:
SSP0CR0tmp = BIT2 | BIT3;
break;
case 14:
SSP0CR0tmp = BIT0 | BIT2 | BIT3;
break;
case 15:
SSP0CR0tmp = BIT1 | BIT2 | BIT3;
break;
case 16:
SSP0CR0tmp = BIT0 | BIT1 | BIT2 | BIT3;
break;
default:
return 0;
}
if (cpol) {
SSP0CR0tmp |= BIT6;
}
if (cpha) {
SSP0CR0tmp |= BIT7;
}
SSP0CR1 = 0x00; // SSP0 disabled
// Setting xx-Bit Datasize, CPOL and CPHA
SSP0CR0 = SSP0CR0tmp;
// Clock Setup
uint32_t pclksel;
uint32_t cpsr;
lpc2387_pclk_scale(CLOCK_CORECLOCK / 1000, freq, &pclksel, &cpsr);
PCLKSEL1 &= ~(BIT10 | BIT11); // CCLK to PCLK divider ???
PCLKSEL1 |= pclksel << 10;
SSP0CPSR = cpsr;
// Enable
SSP0CR1 |= BIT1; // SSP0 enabled
uint32_t dummy;
for (uint32_t i = 0; i < FIFOSIZE; i++) {
dummy = SSP0DR; // clear the RxFIFO
}
/* to suppress unused-but-set-variable */
(void) dummy;
return 1;
}
int spi_init_master(spi_t dev, spi_conf_t conf, spi_speed_t speed)
{
(void ) conf;
if (dev) {
return -1;
}
uint32_t f_baud = 0;
switch(speed)
{
case SPI_SPEED_100KHZ:
f_baud = 100;
break;
case SPI_SPEED_400KHZ:
f_baud = 400;
break;
case SPI_SPEED_1MHZ:
f_baud = 1000;
break;
case SPI_SPEED_5MHZ:
f_baud = 5000;
break;
case SPI_SPEED_10MHZ:
f_baud = 10000;
break;
}
#if 0
/* TODO */
switch(conf)
{
case SPI_CONF_FIRST_RISING:
/**< first data bit is transacted on the first rising SCK edge */
cpha = 0;
cpol = 0;
break;
case SPI_CONF_SECOND_RISING:
/**< first data bit is transacted on the second rising SCK edge */
cpha = 1;
cpol = 0;
break;
case SPI_CONF_FIRST_FALLING:
/**< first data bit is transacted on the first falling SCK edge */
cpha = 0;
cpol = 1;
break;
case SPI_CONF_SECOND_FALLING:
/**< first data bit is transacted on the second falling SCK edge */
cpha = 1;
cpol = 1;
break;
}
#endif
/* Power*/
PCONP |= PCSSP0; /* Enable power for SSP0 (default is on)*/
/* PIN Setup*/
spi_conf_pins(dev);
/* Interface Setup*/
SSP0CR0 = 7;
/* Clock Setup*/
uint32_t pclksel;
uint32_t cpsr;
lpc2387_pclk_scale(F_CPU / 1000, f_baud, &pclksel, &cpsr);
PCLKSEL1 &= ~(BIT10 | BIT11); /* CCLK to PCLK divider*/
PCLKSEL1 |= pclksel << 10;
SSP0CPSR = cpsr;
/* Enable*/
SSP0CR1 |= BIT1; /* SSP-Enable*/
int dummy;
/* Clear RxFIFO:*/
while (SPI_RX_AVAIL) { /* while RNE (Receive FIFO Not Empty)...*/
dummy = SSP0DR; /* read data*/
}
/* to suppress unused-but-set-variable */
(void) dummy;
return 0;
}
