void ARMCore::thumbDataLo(uint4 opcode, uint3 ird, uint3 irm) {
auto &rd = r[ird], rm = r[irm];
r[15] += 2;
if(opcode == 2) { SOut r = lsl(rd, rm); bitf(true, rd = r, r); } // lsls
else if(opcode == 3) { SOut r = lsr(rd, rm); bitf(true, rd = r, r); } // lsrs
else if(opcode == 4) { SOut r = asr(rd, rm); bitf(true, rd = r, r); } // asrs
else if(opcode == 7) { SOut r = ror(rd, rm); bitf(true, rd = r, r); } // rors
else if(opcode == 9) sumf(true, rd = -rm, 0, ~rm); // negs
else if(opcode == 13) bitf(true, rd = rm * rd, {rm*rd, Cf}); // muls
else alu(2*opcode+1, rd, rd, {rm,Cf}); // others are same as ARM
}
void tbh(int i){
int n,m,halfwords;
*((int *)(&TbH)) = i;
n = TbH.rn;
m = TbH.rm;
if(n == 13 || Bad_Reg(m))
printf(" It is unpredictable!");
else if(InITBlock() && !LastInITBlock())
printf(" It is unpredictable!");
else{
halfwords = get_MemU(get_general_register(n) + lsl(get_general_register(m),1),1);
halfwords = halfwords << 1;
BranchWritePC(get_pc() + halfwords);
//printf(" *****tbh");
}
}
void armv7a::ror_c(bits* result, uint32_t* carry_out, const bits& x, uint32_t shift)
{
//pseudo_assert(shift != 0, "ror_c assert error");
//pseudo_assert(shift < 32, "ror_c assert error"); //hit, but no need?
if(shift == 0)
{
(*result) = x;
*carry_out = 0;
}
else
{
uint32_t m = shift % x.n;
bits r1, r2;
lsr(&r1, x, m);
lsl(&r2, x, x.n - m);
result->val = r1.val | r2.val;
result->n = x.n;
printd(d_inst, "x=%X:%d shift:%d lsr_r1:%X lsr_r2:%X result:%X, result.n:%d", x.val, x.n, shift, r1.val, r2.val, result->val, result->n);
*carry_out = (*result)(x.n - 1);
}
}
// Returns the next random number based on seeds
// and updates the seeds accordingly.
dodBYTE RNG::RANDOM()
{
int x, y;
dodBYTE a, b;
carry = 0;
for (x = 8; x != 0; --x)
{
b = 0;
a = (SEED[2] & 0xE1);
for (y = 8; y != 0; --y)
{
a = lsl(a);
if (carry != 0)
++b;
}
b = lsr(b);
SEED[0] = rol(SEED[0]);
SEED[1] = rol(SEED[1]);
SEED[2] = rol(SEED[2]);
}
return SEED[0];
}
void execALU(){
switch(controle_alu.op_code){
case 1: add(); break;
case 2: addinc(); break;
case 3: and(); break;
case 4: andnota(); break;
case 5: asl(); break;
case 6: asr(); break;
case 7: deca(); break;
case 8: inca(); break;
case 9: j(); break;
case 10: jal(); break;
case 11: jf(); break;
case 12: jr(); break;
case 13: jt(); break;
case 14: lch(); break;
case 15: lcl(); break;
case 16: load(); break;
case 17: loadlit(); break;
case 18: lsl(); break;
case 19: lsr(); break;
case 20: nand(); break;
case 21: nor(); break;
case 22: ones(); break;
case 23: or(); break;
case 24: ornotb(); break;
case 25: passa(); break;
case 26: passnota(); break;
case 27: store(); break;
case 28: sub(); break;
case 29: subdec(); break;
case 30: xnor(); break;
case 31: xor(); break;
case 32: zeros(); break;
}
}
