Esempio n. 1
0
File: nand.c Progetto: janfj/dd-wrt
int xway_nand_probe(struct platform_device *pdev)
{
//	ltq_gpio_request(PIN_CS1, 1, 0, 1, "NAND_CS1");
	ltq_gpio_request(PIN_CLE, 1, 0, 1, "NAND_CLE");
	ltq_gpio_request(PIN_ALE, 1, 0, 1, "NAND_ALE");
	if (ltq_is_ar9() || ltq_is_vr9()) {
		ltq_gpio_request(PIN_RDY, 1, 0, 0, "NAND_BSY");
		ltq_gpio_request(PIN_RD, 1, 0, 1, "NAND_RD");
	}

	ltq_ebu_w32((NAND_BASE_ADDRESS & 0x1fffff00)
		| ADDSEL1_MASK(3) | ADDSEL1_REGEN, LTQ_EBU_ADDSEL1);

	ltq_ebu_w32(BUSCON1_SETUP | BUSCON1_BCGEN_RES | BUSCON1_WAITWRC2
		| BUSCON1_WAITRDC2 | BUSCON1_HOLDC1 | BUSCON1_RECOVC1
		| BUSCON1_CMULT4, LTQ_EBU_BUSCON1);

	ltq_ebu_w32(NAND_CON_NANDM | NAND_CON_CSMUX | NAND_CON_CS_P
		| NAND_CON_SE_P | NAND_CON_WP_P | NAND_CON_PRE_P
		| NAND_CON_IN_CS0 | NAND_CON_OUT_CS0, LTQ_EBU_NAND_CON);

	ltq_w32(NAND_WRITE_CMD_RESET, ((u32*)(NAND_BASE_ADDRESS | NAND_WRITE_CMD)));
	while((ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0);

	return 0;
}
Esempio n. 2
0
static int ltq_stp_hw_init(void)
{
	/* the 3 pins used to control the external stp */
	ltq_gpio_request(4, 1, 0, 1, "stp-st");
	ltq_gpio_request(5, 1, 0, 1, "stp-d");
	ltq_gpio_request(6, 1, 0, 1, "stp-sh");

	/* sane defaults */
	ltq_stp_w32(0, LTQ_STP_AR);
	ltq_stp_w32(0, LTQ_STP_CPU0);
	ltq_stp_w32(0, LTQ_STP_CPU1);
	ltq_stp_w32(LTQ_STP_CON_SWU, LTQ_STP_CON0);
	ltq_stp_w32(0, LTQ_STP_CON1);

	/* rising or falling edge */
	ltq_stp_w32_mask(LTQ_STP_EDGE_MASK, LTQ_STP_FALLING, LTQ_STP_CON0);

	/* per default stp 15-0 are set */
	ltq_stp_w32_mask(0, LTQ_STP_GROUP0, LTQ_STP_CON1);

	/* stp are update periodically by the FPI bus */
	ltq_stp_w32_mask(LTQ_STP_UPD_MASK, LTQ_STP_UPD_FPI, LTQ_STP_CON1);

	/* set stp update speed */
	ltq_stp_w32_mask(LTQ_STP_SPEED_MASK, LTQ_STP_8HZ, LTQ_STP_CON1);

	/* tell the hardware that pin (led) 0 and 1 are controlled
	 *  by the dsl arc
	 */
	ltq_stp_w32_mask(0, LTQ_STP_ADSL_SRC, LTQ_STP_CON0);

	ltq_pmu_enable(PMU_LED);
	return 0;
}