void Topology::init() { assert(m_nodes >= MachineType_NUM); if (m_nodes == MachineType_NUM) { SwitchID id = newSwitchID(); for (int machine=0; machine<MachineType_NUM; machine++) { addLink(machine, id, g_param_ptr->NETWORK_LINK_LATENCY()); addLink(id, m_nodes+machine, g_param_ptr->NETWORK_LINK_LATENCY()); } return; } Vector<SwitchID> network_in_switches; Vector<SwitchID> network_out_switches; for (int node = 0; node < m_nodes; node++) { network_in_switches.insertAtBottom(node); // numbered [0...m_nodes-1] network_out_switches.insertAtBottom(node+m_nodes); // numbered [m_nodes-1...m_nodes+m_nodes-1] } // topology-specific set-up switch (g_param_ptr->NETWORK_TOPOLOGY()) { case TopologyType_TORUS_2D: make2DTorus(network_in_switches, network_out_switches); break; case TopologyType_HIERARCHICAL_SWITCH: makeHierarchicalSwitch(network_in_switches, network_out_switches, g_param_ptr->FAN_OUT_DEGREE()); break; case TopologyType_CROSSBAR: makeHierarchicalSwitch(network_in_switches, network_out_switches, 1024); break; default: ERROR_MSG("Unexpected typology type") } }
void Topology::init() #endif { if (m_nodes == 1) { SwitchID id = newSwitchID(); addLink(0, id, NETWORK_LINK_LATENCY); addLink(id, 1, NETWORK_LINK_LATENCY); return; } // topology-specific set-up TopologyType topology = string_to_TopologyType(g_NETWORK_TOPOLOGY); switch (topology) { case TopologyType_TORUS_2D: make2DTorus(); break; case TopologyType_HIERARCHICAL_SWITCH: makeHierarchicalSwitch(FAN_OUT_DEGREE); break; case TopologyType_CROSSBAR: makeHierarchicalSwitch(1024); break; case TopologyType_PT_TO_PT: makePtToPt(); break; case TopologyType_FILE_SPECIFIED: makeFileSpecified(topoType); break; default: ERROR_MSG("Unexpected typology type") } cout << "setupNet value = " << setupNet << endl; #ifdef SIM_MEMORY #ifdef CS_NOC if(!setupNet) { cout << "SimicsMemoryInterface::SetMemoryPortCount " << RubyConfig::numberOfMemories() << endl; SimicsMemoryInterface::SetMemoryPortCount(RubyConfig::numberOfMemories()); } #else SimicsMemoryInterface::SetMemoryPortCount(RubyConfig::numberOfMemories()); #endif #endif // initialize component latencies record m_component_latencies.setSize(0); m_component_inter_switches.setSize(0); }